AlGaN/GaN HEMT多偏置下CV特性的研究

电容电压特性是分析半导体器件性能的一个有效手段,而且是GaN HEMT器件大信号模型建模的重要步骤之一。本文提出一种多偏置电容电压的测试方法,并讨论了Cgs和Cgd的物理意义及其随偏置电压Vgs和Vds的变化规律。提出一种能够反映Cgs和Cgd特性的电容模型,与测试电容数据有很好的拟合效果,并且用器件的功率特性验证了该电容模型在非线性仿真的准确性。     

Panel capacitance estimation method for three-electrode AC-PDP

A new approach for estimating AC-PDP parasitic capacitances is proposed. The method uses easily obtainable data such as resonant period of energy recovery and address power consumptions on specific test images for extracting the capacitances formed among three electrodes of scan (Y), sustain (X), and data electrodes. The proposed capacitance estimation method may assist in cell structure and system design.     

Parameter extraction technique for HBT equivalent circuit usingcutoff mode measurement

A parameter extraction method based on the S-parameter measurements of the heterojunction bipolar transistors (HBTs) biased to cutoff is proposed. This method is applied to confirm the results for the RF probe pad and interconnection pattern parasitics obtained from the special test structures, and to determine some of the device capacitances of the HBT. The remaining device parameters are extracted by the S-parameter measurements of the devices biased to the active mode. The extraction technique gives good agreement between the equivalent circuit and the measured S-parameters of the HBT including probe pads and interconnections     

An approach to determine small-signal model parameters for InP-based heterojunction bipolar transistors

A new method for the extraction of the small-signal model parameters of InP-based heterojunction bipolar transistors (HBT) is proposed. The approach is based on the combination of the analytical and optimization technology. The initial values of the parasitic pad capacitances are extracted by using a set of closed-form expressions derived from cutoff mode S-parameters without any test structure, and the intrinsic elements determined by using the analytical method are described as functions of the parasitic elements. An advanced design system is then used to optimize only the parasitic parameters with very small dispersion of initial values. Good agreement is obtained between simulated and measured results for an InP HBT with 5/spl times/5 /spl mu/m/sup 2/ emitter area over a wide range of bias points up to 40 GHz.     

An efficient solver for the three-dimensional capacitance of theinterconnects in high speed digital circuit by the multiresolutionmethod of moments

The computation of the equivalent capacitances for three-dimensional (3-D) interconnects features large memory usage and long computing time. In this paper, a matrix sparsification approach based on multiresolution representation is applied with the method of moments (MoM) to calculate 3-D capacitances of interconnects in a layered media. Instead of direct expansion of the charge distribution by the orthogonal wavelet basis functions, the large full matrix resulting from discretization of the integral equations is taken as a discrete image and sparsified by two-dimensional (2-D) multiresolution representations. The inverse of the obtained sparse matrix is efficiently implemented by Schultz's iterative approach. Several numerical examples are given and the results obtained show that the proposed method significantly sparsifies the matrix equation and the capacitance parameters computed by the matrix equation with high sparsity agree well with the results of other reports and those computed by an established capacitance extractor FASTCAP     

Multi-bias capacitance voltage characteristic of AlGaN/GaN HEMT

The method of multi-bias capacitance voltage measurement is presented. The physical meaning of gate-source and gate-drain capacitances in AlGaN/GaN HEMT and the variations in them with different bias con-ditions are discussed. A capacitance model is proposed to reflect the behaviors of the gate-source and gate-drain ca-pacitances, which shows a good agreement with the measured capacitances, and the power performance obtains good results compared with the measured data from the capacitance model.     

Computation of sensitivities of IC interconnect parasitic capacitances to the process variation with dual discrete geometric methods

Sensitivity analysis methods help to deal with the challenges of process variation in extraction of parasitic capacitances in an integrated circuit. The dual discrete geometric methods (DGMs), which have been recently utilized to extract parasitic capacitances, are reviewed. The computation method based on the dual DGMs for sensitivities of capacitances with respect to the given process parameters is presented. As the dual DGMs utilize scalar electric potential is unknown, the capacitances are obtained effectively, and then the sensitivities are calculated conveniently.     

一种对三维芯片中硅通孔进行完整建模与寄生参数提取的有效方法

针对三维芯片中硅通孔（through-silicon via, TSV）的准确电学建模问题,本文提出了一种电阻电容（RC）电路模型以及相应的有效参数提取技术。该电路模型同时考虑了半导体效应与静电场影响,适合于低频与中频的电路信号范围。该方法采用一种基于悬浮随机行走（floating random walk, FRW）算法的静电场电容提取技术,然后将它与刻画半导体效应的MOS电容结合,形成等效电路模型。与Synopsys公司软件Sdevice所采用的对静电场/半导体效应进行完整仿真的方法相比,本文方法计算效率更高,并且也能处理一般的TSV电路版图。对多个含TSV的结构进行了计算实验,结果验证了本文方法在从10KHz到1GHz频率范围内的建模准确性,也显示出它相比Sdevice方法最多有47倍的加速比。     

A peeling algorithm for extraction of the HBT small-signal equivalent circuit

Direct extraction is the most accurate method for the determination of equivalent-circuits of heterojunction bipolar transistors (HBTs). The method is based on first determining the parasitic elements and then the intrinsic elements analytically. The accuracy and robustness of the whole algorithm therefore is determined by the quality of the extraction of the extrinsic elements. This paper focuses on a new extraction method for the extrinsic capacitances which have proven to be the main source of uncertainty compared to the other extrinsic parameters. Concerning the intrinsic parameters, all the elements are extracted using exact closed-form equations, including exact expressions for the base-collector capacitances, which model the distributed nature of the base. The expressions for the base-collector capacitances are valid for both the hybrid-/spl pi/ and the physics-based T-topology equivalent circuits. Extraction results for InP HBT devices on measured S-parameters up to 100 GHz demonstrate good modeling accuracy.     

Accurate closed-form expressions for the frequency-dependent line parameters of on-chip interconnects on lossy silicon substrate

Accurate closed-form expressions for the complete frequency-dependent R, L, G, C line parameters of microstrip lines on lossy silicon substrate are presented. The closed-form expressions for the frequency-dependent series impedance parameters are obtained using a complex image method. The frequency-dependent shunt admittance parameters are expressed in closed form in terms of the shunt capacitances obtained in the low and high frequency limits. The proposed closed-form solutions are shown to be in good agreement with the electromagnetic solutions.     

太赫兹平面肖特基二极管参数模型

根据太赫兹平面肖特基二极管物理结构,在理想二极管SPICE参数模型的基础上建立了二极管小信号等效电路模型。依据该二极管等效电路模型设计了基于共面波导（CPW）去嵌方法的二极管S参数在片测试结构,并对其在0.1~50 GHz、75~110 GHz频率范围内进行了高频小信号测试,利用测试结果提取了高频下二极管电路模型中各部分电容、电阻以及电感参数。将相应的高频下电容与电阻参数分别与低频经验公式电容值和直流I-V测试提取的电阻值进行了对比,并利用仿真手段对高频参数模型进行了验证。完整的参数模型以及测试手段相较于理想二极管SPICE模型和传统的参数提取方法可以更为准确地表征器件在高频下的工作状态。该建模思路可用于太赫兹频段非线性电路的优化设计。     

Current mode single-input multi-output MOSFET-only filter

In this paper, a very simple topology of a current mode MOSFET-only filter with single-input and multi-output is proposed. It is very important to emphasize that it is possible to obtain five of the filter functions, namely low-pass (LP), band-pass (BP), high-pass (HP), band-stop (BS) and all-pass (AP) using the proposed topology without using external passive elements. The core circuit of the proposed filter employs only four MOS transistors; therefore, it occupies very small chip area. It is also possible to adjust the filter gain with the biasing voltage. In addition, the circuit exhibits a very low input impedance and also high output impedances which make it possible for cascading. The MOSFET capacitances which determine the transfer functions are all grounded, so physical capacitances can be used instead of MOSFET parasitic capacitances to operate the filter at very low frequencies. Moreover, proposed filter structure has low supply voltage as 1 V in order to be applicable to low voltage operations. Detailed simulation results, including noise and Monte Carlo analysis, are provided using 0.18 µm TSMC technology parameters to verify the feasibility of the filter circuit.     

Modeling and characterization of the bonding-wire interconnection

In this paper, the bonding-wire interconnection has been studied from the points of view of its modeling and electrical characterization. Both singleand double-wire structures have been considered, the latter under the assumption of parallel wires. Two electrical models of the bonding wire are discussed. First, the finite-difference time-domain (FDTD) method is proposed for the rigorous analysis of such structures. This method uses a suitable discretization technique, which accounts for the wire curvature by means of a polygonal approximation. A quasi-static model of the bonding wire, suitable for commercial microwave computer-aided-design tools is then proposed. This model is based on the representation of the structure with four sections of a uniform transmission line and the model parameters are evaluated analytically from the dimensions of the interconnection. Accuracy and applicability of the quasi-static model have been assessed by analyzing several test structures, the reference results being obtained with the FDTD method. Finally, the quasi-static model has been used to provide an extensive electrical characterization of the bonding wire versus its main geometrical parameters. This characterization is given in terms of an equivalent series inductance and two equivalent shunt capacitances forming a π low-pass network. This representation is particularly useful in the matching of the bonding-wire discontinuity     

Design Parameters of Inhomogeneous Asymmetric Coupled Transmission Lines

The parameters of asymmetric coupled lines in an inhomogeneous medium (mode numbers and mode impedances) are derived in terms of self and mutual static capacitances of the system in the filled and empty structures. These capacitances are computed by using the network analog method. The effect of dispersion is accounted for by introducing an approximate dispersion model. A set of design curves for different geometric configurations are presented which can help in the design of couplers and filters. The obtained numerical results, taking into consideration the dispersion effect, were found to be in a good agreement with the only available published data.     

Fast and accurate quasi-three-dimensional capacitance determinationof multilayer VLSI interconnects

A new fast and accurate capacitance determination methodology for intricate multilayer VLSI interconnects is presented. Since a multilayer interconnect structure is too complicated to be directly tractable, it is simplified by investigating charge distributions within the system. The quasi-three-dimensional (3-D) capacitances of the structure are then determined by combining a set of solid-ground-based two-dimensional (2-D) capacitances and shielding effects that can be independently calculated from the simplified structure. The shielding effects due to the neighboring lines of a line can be analytically determined from the given layout dimensions. The solid-ground-based 2-D capacitances can also be quickly computed from the simplified structure. Thus, the proposed capacitance determination methodology is much more cost-efficient than conventional 3-D-based methods. It is shown that the calculated quasi-3-D capacitances have excellent agreement with 3-D field-solver-based results within 5% error     

实际应用条件下Power MOSFET开关特性研究(下)

从功率MOSFET内部结构和极间电容的电压依赖关系出发,对功率MOSFET的开关现象及其原因进行了较深入分析。从实际应用的角度,对功率MOSFET开关过程的功率损耗和所需驱动功率进行了研究,提出了有关参数的计算方法,并对多种因素对开关特性的影响效果进行了实验研究,所得出的结论对于功率MOSFET的正确运用和设计合理的MOSFET驱动电路具有指导意义。     

An Approach for Extracting Small-Signal Equivalent Circuit of Double Heterojunction δ-Doped PHEMTs for Millimeter Wave Applications

Pseudomorphic high electron mobility transistors (PHEMTs) are very important in millimeterwave application. A simple and accurate method for extracting small-signal equivalent curcuit for Double Heterojunction δ-doped PHEMT valid up to 40GHz is presented. First, the parasitic parameters of the equivalent circuit are determined using pinch off PHEMT except for PAD capacitances. The initial intrinsic elements are then determined by conventional analytical method. Advanced Design System is then used to optimize the whole model parameters with very small dispersion of initial values. Good agreement is obtained between simulation results and measured results for a 0.25um DH PHEMT.     

Effect of parameter variations at chip and wafer level on clockskews

In this paper, a methodology is proposed to determine clock skews and the performance of clock architectures considering parameter variations in an early stage of technology development. With this methodology, it is possible to separate process-induced clock skew from other effects like imperfect loading. Parameter variations are seen as one of the most important effects influencing chip performance in future. By comparing a 0.45- and a 0.25-μm technology, it is shown that in the future, process variations will increase clock skew. The clock skews are determined by measuring the relevant device and metal line parameters as a function of position over chip and wafer. In the past, parameters like IDS, Vth, and resistances could be measured very precisely, although it was difficult to measure low capacitances of single metal lines in the range of femto farad. Thus a new measurement method is used to determine interconnect capacitances extremely precisely. Based on these measurement data, a netlist of a defined clock tree is created by a C-program, and the clock signal delay is simulated. From the delay simulation, we calculate the clock skew for each chip dependent on the parameter variations. Experimental results are separated into a basic random fluctuation part and processing-related contributions on the chip and wafer levels. In addition, the effect of temperature gradients on each chip to the clock skew is simulated. The methodology presented is not restricted to just one clocktree but allows investigation of all kinds of clock distribution circuits. The method has clear advantages with respect to chip area against clocktree realizations on a testchip. No direct and costly measurement of signal delays by voltage contrast methods is required, since all parameters are determined by measurement on the device level     

Chebyshev collocation and Newton-type optimization methods for the inverse problem on nonuniform transmission lines

A frequency-domain inverse problem for the nonuniform LCRG transmission line is considered. The parameters of the nonuniform line are interpolated by Chebyshev polynomials, and the Telegraphers equations are solved by a collocation method using the same polynomials. The interpolation coefficients for the unknown parameters are reconstructed by means of Newton-type optimization methods for which the Jacobian matrix has been calculated explicitly. For the reconstruction of one or two parameters, the algorithm is tested on synthetic data, and the necessity to use regularization is discussed. Finally, the algorithm is tested with measured reflection data to reconstruct shunt capacitances with piecewise constant profiles.     

一种用于混沌保密的新型混沌信号产生电路

混沌信号被广泛用于数据加密、保密通信、流体混合等众多领域,论文提出了一种基于参数周期扰动产生混沌信号的方法,使得一个二阶系统混沌化,并设计了该二阶系统的电路,由于该电路只采用了LM358、AD734、MAX038和若干电容、电阻,因此可应用到家电、智能仪表、IC卡等中低档消费电子产品中以实现数据加密。