Numerical study on thermal impacts of different void patterns on performance of chip-scale packaged power device

Chip scale package (CSP) technology offers promising solutions to package power device due to its relatively good thermal performance among other factors. Solder thermal interface materials (STIMs) are often employed at the die bond layer of a chip-scale packaged power device to enhance heat transfer from the chip to the heat spreader. Nonetheless, the presence of voids in the solder die-attach layer impedes heat flow and could lead to an increase in the peak temperature of the chip. Such voids which form easily in the solder joint during reflow soldering process at manufacturing stage are primarily occasioned by out-gassing phenomenon and defective metallisation. Apparently, the thermal consequences of voids have been extensively studied, but not much information exist on precise effects of different patterns of solder die-attach voids on the thermal performance of chip-level packaged power device. In this study, three-dimensional finite element analysis (FEA) is employed to investigate such effects. Numerical studies were carried out to characterise the thermal impacts of various voids configurations, voids depth and voids location on package thermal resistance and chip junction temperature. The results show that for equivalent voiding percentage, thermal resistance increases more for large coalesced void type in comparison to the small distributed voids configuration. In addition, the study suggests that void extending through the entire thickness of solder layer and voids formed very close to the heat generating area of the chip can significantly increase package thermal resistance and chip junction temperature. The findings of this study indicate that void configurations, void depth and void location are vital parameters in evaluating the thermal effects of voids.     

粘结层空洞对功率器件封装热阻的影响

功率器件的热阻是预测器件结温和可靠性的重要热参数,其中芯片粘接工艺过程引起的粘结层空洞对于器件热性能有很大的影响。采用有限元软件Ansys Workbench对TO3P封装形式的功率器件进行建模与热仿真,精确构建了不同类型空洞的粘结层模型,包括不同空洞率的单个大空洞和离散分布小空洞、不同深度分布的浅层空洞和沿着对角线分布的大空洞。结果表明,单个大空洞对器件结温和热阻升高的影响远大于相同空洞率的离散小空洞;贯穿粘结层的空洞和分布在芯片与粘结层之间的浅空洞会显著引起热阻上升;分布在粘结层边缘的大空洞比中心和其他位置的大空洞对热阻升高贡献更大。     

Durability of Pb‐free solder between copper interconnect and silicon in photovoltaic cells

The thermal cycling durability of large‐area Pb‐free (Sn3.5Ag) solder between silicon semiconductor and copper interconnects in photovoltaic (PV) cells is assessed and compared to benchmark results from Pb‐based (Sn36Pb2Ag) PV cells. Accelerated thermal cycling tests have been conducted on PV cells of both solder compositions, and the increase in series resistance due to interconnect damage has been characterized using in situ dark I–V measurements. Both the Pb‐free and Pb‐based cells show a steep initial rise followed by a steady rate of increase in degradation histories, with the Pb‐free cells showing a more pronounced ‘knee’ in the degradation curves. Extrapolation of the degradation data for both solders suggests that Pb‐free cells are four times more durable than the Pb‐based cells at the test condition. This superior thermal cycling fatigue durability of Pb‐free cells was also confirmed with physics of failure (PoF) analysis, consisting of nonlinear finite element (FE) stress analysis and an energy‐partitioning (E‐P) solder fatigue model. FE models error‐seeded with manufacturing voids in the solder interconnect predicted a significant reduction in the thermal cycling durability with increasing solder void density. However, even the most voided Pb‐free cells modeled are predicted to be twice as durable as void‐free Pb‐based cells, under the accelerated temperature cycle used in the test. The acceleration factor (AF) predicted by the PoF analysis for a typical service environment is three times higher for Pb‐free cells than that for Pb‐based cells. Copyright © 2010 John Wiley & Sons, Ltd.     

A new and efficient approach for estimating the accurate time-domain response of single and capacitive coupled distributed RC interconnects

This paper describes a novel yet highly efficient approach for estimating the time-domain response of capacitive coupled distributed RC interconnects. By using this method, the voltage signal at any particular point in such wires can be accurately and quickly obtained with very low computational cost. The proposed model exhibits a very good agreement with HSPICE simulations with worst-case error less than 3% and can be readily implemented in CAD analysis tools. This paper also presents an efficient model to estimate the capacitive crosstalk in high-speed very large scale integration (VLSI) circuits. Experimental results show that the maximum error of our peak noise predictions is less than 2.5%. In addition, this work presents an efficient artificial neural network (ANN)-based technique for modeling the time-domain response of interconnects and crosstalk noise. While existing fast noise estimation metrics may overestimate or underestimate the coupling noise, the simulation results demonstrate the ability of this approach to successfully predict coupling noise with a very good accuracy as compared to HSPICE in modest CPU times. Thereby, the proposed models and techniques can be used to predict the signal integrity for designing high-speed and high-density VLSI circuits.     

Near Void-Free Assembly Development of Flip Chip Using No-Flow Underfill

The advanced flip-chip-in-package (FCIP) process technology, using no-flow underfill material for high I/O density (over 3000 I/O) and fine-pitch (down to 150 mum) interconnect applications, presents challenges for flip chip processing because underfill void formation during reflow drives interconnect yield down and degrades reliability. In spite of such challenges, a high yield, reliable assembly process (>99.99%) has been achieved using commercial no-flow underfill material with a high I/O, fine-pitch FCIP. This has been obtained using design of experiments with physical interpretation techniques. Statistical analysis determined what assembly conditions should be used in order to achieve robust interconnects without disrupting the FCIP interconnect structure. However, the resulting high yield process had the side effect of causing a large number of voids in the FCIP assemblies. Parametric studies were conducted to develop assembly process conditions that would minimize the number of voids in the FCIP induced by thermal effects. This work has resulted in a significant reduction in the number of underfill voids. This paper presents systematic studies into yield characterization, void formation characterization, and void reduction through the use of structured experimentation which was designed to improve assembly yield and to minimize the number of voids, respectively, in FCIP assemblies.     

Morphology of electromigration-induced damage and failure in Al alloy thin film conductors

Distinct morphologies of electromigration-induced voids and failures are shown for Al, Al-2%Cu, and Al-2%Cu-l% Si narrow (1–6 μm) unpassivated thin film conductors. SEM and TEM images typically show large non-fatal voids and narrow slit-like open circuit failures for all film conditions and accelerated test conditions. Evidence for transgran-ular slit failures is shown for 1.33 μm wide conductors. A simple model for void growth is presented which accounts for the void morphologies seen. The observed morphologies and the results of void growth modelling suggest that slit voids nucleate after other voids and rapidly produce failure. These conclusions are discussed in terms of ‘classical’ models for electromigration failure processes and resistance and noise power monitoring techniques.     

Temperature-dependent stress-induced voiding in dual-damascene Cu interconnects

Temperature-dependent stress-induced voiding (SIV) of Cu dual-damascene interconnects in via-line structures has been studied by stress modeling and focused-ion-beam (FIB) cross-section analysis. The via-line structures have been studied at temperatures ranging from 100 to 250 °C, with highest voiding rate being detected at 200 °C. The hydrostatic stress and stress gradient reach each peak values and lead to void nucleation symmetrically underneath the edge of the via. Stress gradient instead of stress shows crucial effect on the SIV process. Voids tend to grow horizontally along the Cu/SiN interface under larger stress gradient in the line length direction as compared to the line height direction.A voiding model based on Nabarro–Herring equations has been proposed and the relation between the voiding rate and stress gradient has been built. The voiding model shows that the stress-induced voiding is a process by which vacancies diffuse and concentrate to form voids under the force of stress gradient. The stress and the diffusional factors grow oppositely with temperature and the maximum voiding rate is reached at a medium temperature.     

3D Modeling of electromigration combined with thermal–mechanical effect for IC device and package

This paper studies the numerical simulation method for electromigration in IC device and solder joint in a package under the combination of high current density, thermal load and mechanical load. The three dimensional electromigration finite element model for IC device/interconnects and solder joint reliability are developed and tested. Numerical experiment is carried out to obtain the electrical, thermal and stress fields with the migration failure under high current density loads. The direct coupled analysis and in-direct coupled analysis that include electrical, thermal and stress fields are investigated and discussed. The viscoplastic ANAND constitutive material model with both SnPb and SnAgCu lead-free solder materials is considered in the paper. An IC device is studied to show the modeling methodology and the comparison with previous test data. A global CSP package with PCB is modeled using relative coarse elements. In order to reduce the computational costs and to improve the calculation accuracy, a refined mesh sub-model is constructed. The sub-model technique is studied in a direct and indirect coupled multiple fields. The comparison of voids generation through numerical example in this paper and previous experimental result is given.     

On the assessment of voids in the thermal interface material on the thermal performance of a silicon chip package

The current investigation assesses the effect of voids in the thermal interface material (TIM) on the thermal performance of silicon chip packages. The effects of the voids were included in the TIM using a series of analytical and numerical models that employed an effective volume-averaged thermal conductivity for the TIM and the actual voids within the TIM. Different void concentrations and distributions were evaluated using this numerical simulation process. The junction-to-air thermal resistance of the package was calculated in order to effectively evaluate the thermal performance of the chip package. A series of parametric studies were conducted and indicated that a 3-D numerical model using actual holes up to a number of 100 and at different concentrations in volume predicts similar results as a 3-D model using a volume-average effective thermal conductivity of the TIM. Finally, it was found that the analytical model developed here provides results that compare favorably with those obtained using more complex and time intensive 3-D models (approximately 7–10%).     

The evolution of the resistance of aluminum interconnects during electromigration

Resistance monitoring is a traditional method to investigate electromigration failure. It is important to understand how much information can be extracted from the data generated by these experiments. To this end, precision resistance measurements were included as part of accelerated electromigration tests performed inside of a high voltage scanning electron microscope (HVSEM). Twenty-two passivated Al interconnects were tested at 30 mA/μm² and at two temperatures, half at 212°C and half at 269°C. During every test, our automated apparatus stored images of each 300 μm long structure several times per hour. The resistance of each line was also precisely measured and recorded. Changing the temperature affected only the time scale of the resistance evolution. There were resistance changes before voids formed that were neither due to temperature fluctuations nor solute effects. In most cases, the nucleation of the first void to form in a line was signaled by an increase in the time derivative of the resistance. Due to the strong effect of void shape, the void volume could not be determined by the magnitude of the resistance change. The width of a void (transverse to the line) rather than the volume largely determined the resistance change.     

Analysis of electromigration induced early failures in Cu interconnects for 45 nm node

Bi-directional current stressing was used for monitoring electromigration (EM) lifetime evolution in 45 nm node interconnects. Experimental results show that an initial bimodal distribution of lifetimes can be modified into a more robust mono-modal distribution. Since the bi-directional tests provide successive void nucleation and void healing phases, the Cu microstructure is thought to evolve once the formed void is filled thanks to EM induced matter displacement. FEM modeling is used to compare the predicted location of void nucleation for given microstructures at the cathode end: a multigrain structure is compared to a perfect bamboo microstructure. Experimental and modeling results let us assume that small grains (<linewidth or via diameter) at the cathode end present a risk of EM induced early fails. Indeed at this location void nucleates and grows nearby the via opening it shortly. On the contrary, the bamboo microstructure is thought to provide more robust lifetime because voids nucleate a few hundred nanometers in the line and grow down reaching the bottom diffusion barrier of the line. This latter case provides larger void size before circuit opening.     

The effect of die attach voiding on the thermal resistance of chip level packages

The presence of voids in the die bond region is known to adversely affect the thermal resistance of the packaged chip-level device. Unfortunately, such voids are easily formed in the solder layer during manufacturing, and are found to nucleate, grow and coalesce with thermal cycling. Although the relationship between package thermal resistance and voids has been examined extensively, little data exist concerning the precise effects of void size, configuration and position. The present study allows the experimental investigation of these effects through application of an innovative experimental technique that carefully controls void geometry and distribution. The results show that for small, random voids, the thermal resistance, θ_jc, increases linearly with void volume percentage, V_%, according to the equation θ_jc = 0.007V + 1.4987, and for large, contiguous voids the increase follows the exponential relationship, θ_jc = 1.427e^0.015V. At 73% voiding, θ_jc was found to increase 30% and 200% for random and contiguous voids, respectively.     

贴片电阻焊点内部空洞缺陷自适应检测

贴片电阻在回流焊过程中,受工艺影响,焊点内部或多或少会存在空洞缺陷,空洞占比率过高会严重降低器件的可靠性。该文融合局部预拟合(LPF)活动轮廓模型和自适应圆形卷积核,提出一种贴片电阻焊点内部空洞缺陷自适应检测方法。首先,根据贴片电阻图像具有明暗两个明显区域的特点,通过求解区域平均灰度差异最大的优化问题将其自适应地分为较暗和较亮两个区域。然后,针对较暗区域中空洞与背景之间对比度低、空洞分布较稀疏、面积偏大等特点,采用局部预拟合活动轮廓模型进行空洞检测;针对较亮区域中空洞与背景之间差异明显、空洞分布密集、面积偏小等特点,提出一种自适应圆形卷积核检测空洞。最后,采用形状因子和平均灰度策略剔除误检测,实现贴片电阻焊点内部空洞精细检测。实验结果表明,该文算法相较于其他检测算法性能有明显的提升,平均Dice系数高达0.8846。     

车载IGBT器件封装装片工艺中空洞的失效研究

IGBT芯片在TO-220封装装片时容易形成空洞,焊料层中空洞大小直接影响车载IGBT器件的热阻与散热性能,而这些性能的好坏将直接影响器件的可靠性。文章分析了IGBT器件在TO-220封装装片时所产生的空洞的形成机制,并就IGBT器件TO-220封装模型利用FEA方法建立其热学模型,模拟结果表明:在装片焊料层中空洞含量增加时,热阻会急剧增大而降低IGBT器件的散热性能,IGBT器件温度在单个空洞体积为10%时比没有空洞时高出28.6℃。同时借助工程样品失效分析结果,研究TO-220封装的IGBT器件在经过功率循环后空洞对于IGBT器件性能的影响,最后确立空洞体积单个小于2%,总数小于5%的装片工艺标准。     

Experimental characterization and modelling of electromigration lifetime under unipolar pulsed current stress

The electromigration behaviour of Cu/SiCOH interconnects carrying unipolar pulsed current with long periods (i.e. 2, 16, 32 and 48 h) is presented in this study. Experimental observations suggest that the electromigration behaviour during void growth can be described by the ON-time model and that the lifetime of the Cu/SiCOH interconnects is inversely related to the duty cycle. Numerical simulation is carried out to compute the time required to nucleate a void under unipolar pulsed current stress conditions. The time to void nucleation is found to vary proportionally to the inverse square of the duty cycle and is independent of frequency at 1 Hz and higher. By computing the stress evolution in interconnects with short length, it was shown that the product of the unipolar pulsed current’s duty cycle and current density, i.e. average current density, is equivalent to the current density of a constant current (D.C.) stress. The simulation results suggest (d · jL)_crit as the equivalent critical current density-length product under unipolar pulsed current condition. Both the experimental and simulation results show that duty cycle has an effect on the electromigration lifetime of interconnects carrying unipolar pulsed current.     

Finite element analysis of the effect of process-induced voids on the fatigue lifetime of a lead-free solder joint under thermal cycling

Process-induced voids remain one of the key concerns in thermo-mechanical reliability of solder alloys. Previous studies reported that the void effect on fatigue failure reliability of solder joints depends on the void configuration and some other specific characteristics of the electronic package. This paper investigates the void effect on the solder material layers used in power modules subjected to thermal passive cycles. The Anand's visco-plastic model of the solder alloy is identified based on experimental data obtained with a micro-tester. The constitutive model is then used in a finite element analysis to study the behaviour of Innolot Pb-free solder joint used in an electronic assembly. An algorithm called Monte Carlo Representative Volume Element Generator is used to generate, based on the statistical probability law for the diameters, the 2D disk distribution of the voids (thereafter extruded in the form of cylinders) within the solder layer. The dissipated plastic energy is considered as a damage variable indicator representing the void effect on the fatigue lifetime of the solder. Results suggest that the fatigue reliability of solder joints depends not only on the size, location and ratio of the voids but also on their statistical distribution. The critical sites for damage are located at the corners of the joint, as well as at the border of voids. Fatigue lifetime of the solder joint decreases as the volume fraction of voids increases. Moreover, voids near the critical sites facilitate initiation of damage significantly. On the contrary, the solder joint behaviour is almost not affected by voids located far from the critical sites.     

Thermal-Mechanical Process Simulation of an Advanced NCF Technology

The paper introduces an advanced nonconductive film (NCF) typed FC technology employing a novel compliant composite interconnect structure. The interconnect reliability and bondability of the technology are demonstrated through experimental thermal humidity (TH) test in conjunction with a two-point daisy chain resistance measurement. The alternative goal of the study aims to look into the insight of the thermal-mechanical behaviors of the novel packaging technology during NCF bonding process and thermal testing through numerical modeling and experimental validation. For effectively simulating the bonding process, a process-dependent finite-element (FE) simulation methodology is performed. The validity of the proposed methodology is verified through several experimental methods, including a Twyman-Green (T/G) interferometry technique for warpage measurement, and a four-point probe method for contact resistance measurement. At last, a design guideline for improved process-induced thermal-mechanical behaviors is presented through parametric FE analysis. Both numerical and experimental results demonstrate the feasibility in applying the novel compliant interconnects to achieve a proper contact stress at various temperature environments so as to hold a low and stable connection resistance at elevated temperature. Most importantly, the novel interconnects survive the 85degC/85%RH TH test for 500 hours.     

Stress-voiding of narrow conductor lines

The growth of voids in conductor lines that have no applied voltage nor imposed thermal or concentration gradients is examined. Such voids can cause narrow aluminium conductors in silicon ICs to fail spontaneously. Recent attempts to describe void growth mathematically as a stress-driven diffusive phenomenon are reviewed, and an expression for the time dependent void size is derived. The equation is used to explore the many variables of the void-growth problem     

Correlation of electromigration lifetime distribution to failure mode in dual Damascene Cu/SiLK interconnects

The electromigration cumulative percent lifetime probability of dual Damascene Cu/SiLK interconnects was fitted using three, individual lognormal functions where the functional populations were grouped by void growth location determined from focused ion beam failure analysis of all 54 of the stressed structures. The early, first mode failures were characterized by small voids in the bottom of the vias. The intermediate mode failures had voids in the line and via bottom while the late mode failures had voids that formed in the line only. The three, individual lognormal functions provided good fits of the data. Failure mode population separation using comprehensive failure analysis suggested that only the first mode failures should be used in the prediction of the chip design current.     

Crosstalk modeling for coupled RLC interconnects with application to shield insertion

On-chip interconnect delay and crosstalk noise have become significant bottlenecks in the performance and signal integrity of deep submicrometer VLSI circuits. A crosstalk noise model for both identical and nonidentical coupled resistance-inductance-capacitance (RLC) interconnects is developed based on a decoupling technique exhibiting an average error of 6.8% as compared to SPICE. The crosstalk noise model, together with a proposed concept of effective mutual inductance, is applied to evaluate the effectiveness of the shielding technique.