倒装焊器件封装结构设计

倒装焊是今后高集成度半导体的主要发展方向之一。倒装焊器件封装结构主要由外壳、芯片、引脚(焊球、焊柱、针)、盖板(气密性封装)或散热片(非气密性封装)等组成。文章分别介绍外壳材料、倒装焊区、频率、气密性、功率等方面对倒装焊封装结构的影响。低温共烧陶瓷(LTCC)适合于高频、大面积的倒装焊芯片。大功率倒装焊散热结构主要跟功率、导热界面材料、散热材料及气密性等有关系。倒装焊器件气密性封装主要有平行缝焊或低温合金熔封工艺。     

助焊剂残留对底部填充粘接强度的影响

随着封装工艺的不断发展,芯片I/O数越来越多,高密度芯片封装必须采用倒装焊的形式。底部填充作为芯片倒装焊封装后的加固工艺,填充胶与倒装焊使用的助焊剂的兼容性对于研究倒装焊电路的长期可靠性至关重要。分析了底部填充胶与助焊剂的兼容性,以及助焊剂的残留对底部填充胶加固效果的影响。若助焊剂清洗不干净,会导致底部填充胶的粘接力下降,影响器件的质量。     

Cu镀Au腔体气密性封装工艺研究

Cu镀Au腔体是微波器件常用封装载体之一。在目前应用中,Cu镀Au腔体微波器件的气密性封装一直是工程化技术难题,大幅影响了微波器件的可靠性和使用寿命。对基于Cu镀Au腔体的微波器件进行了气密性封装研究,探讨了Cu镀Au腔体实现气密性封装可能的工艺路线。通过比较激光封焊和真空钎焊等传统气密性封装工艺方法,提出了＂小孔密封...     

采用金锡合金的气密性封装工艺研究

根据功率器件的气密性封装要求,设计了完整的金锡封焊工艺方法和流程,研究了工艺中的技术难点,提出了确保封装工艺稳定性和可靠性的技术要点.实验选甩Au80Sn20预成型焊环作为封接材料对器件进行气密性封装.通过大量试验得出了最佳工艺曲线(包括温度、时间、气氛和压力等).密封后的产品在经受各项环境试验和机械试验后,其结构完整性、电学特性、机械牢固性和封装气密性均能很好地满足要求,证明了采用倒置型装配的金锡封焊工艺的可行性及优越性.     

倒装焊封装工艺缺陷及检测方法研究

针对面阵列倒装焊封装结构内部互连工艺质量检测难度大的问题,提出了适用于倒装焊封装典型工艺缺陷的检测方法,阐述了光学二维视觉检测、X射线检测等常用缺陷检测技术的原理和工艺适用性,为倒装焊封装工艺质量提升提供有效技术参考.     

倒装焊结构对太赫兹对数周期天线的影响

设计了一种倒装焊结构,用于340GHz的肖特基二极管探测器。探测单元是基于砷化镓（GaAs）工艺设计的。薄膜陶瓷支撑层旨在为太赫兹检测单元提供封装。通常,导电胶用作天线和输出电路之间的附接。分别对倒装焊结构和无倒装焊结构（类引线键合结构）模型对太赫兹接收天线性能的影响进行研究。为了比较的目的,使用相同的测试系统表征FC结构模型和无FC结构模型（引线键合结构）。通过引线键合与倒装焊测试增益的结果比较,表明倒装焊结构可以作为大规模太赫兹检测阵列封装的低成本解决方案。     

倒装焊结构对太赫兹对数周期天线的影响（英文）

设计了一种倒装焊结构,用于340 GHz的肖特基二极管探测器.探测单元是基于砷化镓(GaA s)工艺设计的.薄膜陶瓷支撑层旨在为太赫兹检测单元提供封装.通常,导电胶用作天线和输出电路之间的附接.分别对倒装焊结构和无倒装焊结构(类引线键合结构)模型对太赫兹接收天线性能的影响进行研究.为了比较的目的,使用相同的测试系统表征FC结构模型和无FC结构模型(引线键合结构).通过引线键合与倒装焊测试增益的结果比较,表明倒装焊结构可以作为大规模太赫兹检测阵列封装的低成本解决方案.     

应用于MEMS气密性封装测试的微型湿度传感器的设计与制作

MEMS器件的封装一直是MEMS技术的难点之一 ,在封装设计中 ,如何测试封装的有效性就显得尤为重要。本文叙述了一种基于MEMS技术的微型湿度传感器的原理、设计以及工艺流程。在其上进行气密性封装 ,则可通过对封装内的湿度测量来判断该封装的气密性能。在设计中 ,充分考虑了尺寸、工艺以及灵敏度等各方面要求。制作采用的是传统的光刻、刻蚀工艺。该湿度传感器结构简单 ,易于制作 ,其性能能够满足气密性封装测试的要求     

晶片级无铅CSP器件的底部填充材料

晶片级器件底部填充作为一种新工艺仍需进一步提高及优化，其工艺为：在晶片级器件制作过程中，晶圆底部加填充材料，这种填充材料在芯片成型时一步到位，免掉了外封装工艺，这种封装体积小，工艺简单，可谓经济实惠。然而，该新型封装器件面临一个严峻的考验，即：用于无铅焊接工艺。这就意味着：即要保证器件底部填充材料与无铅焊料的兼容，又要满足无铅高温焊接要求，保证焊接点的可靠性及生产产量。 近期为无铅CSP底部填充研发了几种新型材料，这些填充材料滴涂到晶圆上，呈透明胶状（半液态）物质，经烘烤，呈透明状固态物质，这样分割晶圆时可保证晶片外形的完整性，不会出现晶片分层或脆裂。在这篇章中，我们探讨一下烘烤对晶圆翘曲度的影响？烘烤是否引发底部填充材料的脆裂？以及回流过程中底部填充物的流动引起的焊料拖尾问题？因为底部填充材料即要保证焊料不拖尾，又要保证焊点的可靠性，及可观察到的焊料爬升角度，同时，底部填充材料的设计必须保证烘烤阶段材料的流动，固化情况处于可控工艺窗口之内。另外，底部填充材料与焊接材料的匹配标准在本中也有讨论。[编按]     

应用于MEMS气密性封装测试的微型湿度传感器的设计与制作

MEMS器件的封装一直是MEMS技术的难点之一,在封装设计中,如何测试封装的有效性就显得尤为重要.本文叙述了一种基于MEMS技术的微型湿度传感器的原理、设计以及工艺流程.在其上进行气密性封装,则可通过对封装内的湿度测量来判断该封装的气密性能.在设计中,充分考虑了尺寸、工艺以及灵敏度等各方面要求.制作采用的是传统的光刻、刻蚀工艺.该湿度传感器结构简单,易于制作,其性能能够满足气密性封装测试的要求.     

AuSn合金在电子封装中的应用及研究进展

AuSn合金焊料因其具有优良的抗腐蚀、抗疲劳特性和高强度、高可靠性等优点而在气密性封装、射频和微波封装、发光二极管(LED)、倒装芯片(Flip-chip)、激光二极管(LD)、芯片尺寸封装(CSP)等方面得到广泛的应用。从电子封装无铅化和合金焊料的可靠性等方面,对AuSn合金焊料的物相结构和材料性能进行了讨论,并对AuSn合金焊料在电子封装中的应用及其研究进展进行了总结和展望。     

Wafer-level hermetic MEMS packaging by anodic bonding and its reliability issues

This paper reviews wafer-level hermetic packaging technology using anodic bonding from several reliability points of view. First, reliability risk factors of high temperature, high voltage and electrochemical O₂ generation during anodic bonding are discussed. Next, electrical interconnections through a hermetic package, i.e. electrical feedthrough, is discussed. The reliability of both hermetic sealing and electrical feedthrough must be simultaneously satisfied. In the last part of this paper, a new wafer-level MEMS packaging material, anodically-bondable low temperature cofired ceramic (LTCC) wafer, is introduced, and its reliability data on hermetic sealing, electrical interconnection and flip-chip mounting on a printed circuit board (PCB) are described.     

Flip-chip packaging solution for CMOS image sensor device

Chip scaled opto-electronic packaging is introduced as a cost and size effective packaging solution for mobile phone with built in camera. The chip scaled assembly includes gold bumped CMOS image sensor device and its flip-chip bonding on substrate using the anisotropic conductive material. Two types of flip-chip module were designed to have flip-chip on flex and flip-chip on glass. It is shown that well controlled bumping process of thin film deposition and wet etching gives no damage to image sensing surface during the deposition and stripping of metal film. As results, smart and high degree miniaturized image sensor module is actualized for mobile phone and the reliability test results proved the robustness of module structure having flip-chip. Solder bumping was also reviewed and successfully introduced to verify the alternative of image sensor bumping.     

高密度陶瓷倒装焊封装可靠性试验开路后的失效定位

陶瓷材料具有优良的综合特性,被广泛应用于高可靠微电子封装.陶瓷倒装焊封装的特殊结构使得对其进行失效分析相较其他传统封装形式更为困难.针对一款在可靠性试验中发生开路的高密度陶瓷倒装焊封装器件,制定了一套从非破坏性到破坏性的试验方案对其进行分析.通过时域反射计(TDR)测试排除了基板内部失效的可能性,通过X射线(X-ray)检测、超声扫描显微镜(SAM)和光学显微分析初步断定失效位置,并最终通过扫描电子显微镜和X射线能谱仪实现了对该器件的准确的失效定位,确定失效位置为基板端镀Ni层.该失效分析方法对其他陶瓷倒装焊封装的失效检测及分析有一定的借鉴意义.     

高压倒装LED照明组件的热性能

高压(HX)倒装LED是一种新型的光源器件,在小尺寸、高功率密度发光光源领域有广泛的应用前景.设计了4种不同工作电压的高压倒装LED芯片,进行了流片验证,并对其进行了免封装芯片(PFC)结构的封装实验,在其基础上研制出一种基于高压倒装芯片的PFC-LED照明组件.建立了9V高压倒装LED芯片、PFC封装器件及照明组件的模型,利用流体力学分析软件进行了热学模拟和优化设计;利用T3Ster热阻测试分析仪进行了热阻测试,验证了设计的可行性.结果表明,基于9V高压倒装LED芯片的PFC封装器件的热阻约为0.342 K/W,远小于普通正装LED器件的热阻.实验结果为基于高压倒装LED芯片的封装及应用提供了热学设计依据.     

Three-dimensional flip-chip on flex packaging for power electronicsapplications

We have extended the concept of flip-chip technology, which is widely used in IC packaging, to the packaging of three-dimensional (3-D) integrated power electronics modules (IPEMs). We call this new approach flip-chip on flex IPEM (FCOF-IPEM), because the power devices are flip-chip bonded to a flexible substrate with control circuits. We have developed a novel triple-stacked solder bump metallurgy for improved and reliable device interconnections. In this multilayer structure, we have carefully selected packaging materials that distribute the thermo-mechanical stresses caused by mismatching coefficients of thermal expansion (CTEs) among silicon chips and substrates. We have demonstrated the feasibility of this packaging approach by constructing modules with two insulated gate bipolar transistors (IGBTs), two diodes, and a simple gate driver circuit. Fabricated FCOF-IPEMs have been successfully tested at power levels up to 10 kW. This paper presents the materials and reliability issues in the package design along with electrical, mechanical, and thermal test results for a packaged IPEM     

Development of no-flow underfill materials for lead-free solderbumped flip-chip applications

No-flow underfill process in flip-chip assembly has become a promising technology toward a smaller, faster and more cost-efficient packaging technology. The current available no-flow underfill materials are mainly designed for eutectic tin-lead solders. With the advance of lead-free interconnection due to the environmental concerns, a new no-flow underfill chemistry needs to be developed for lead-free solder bumped flip-chip applications. Many epoxy resin/hexahydro-4-methyl phthalic anhydride/metal acetylacetonate material systems have been screened in terms of their curing behavior. Some potential base formulations with curing peak temperatures higher than 200°C (based on differential scanning calorimetry at a heating rate of 5°C/min) are selected for further study. The proper fluxing agents are developed and the effects of fluxing agents on the curing behavior and cured material properties of the potential base formulations are studied using differential scanning calorimetry, thermomechanical analysis, dynamic-mechanical analysis, thermogravimetric analysis, and rheometer. Fluxing capability of the developed no-flow formulations is evaluated using the wetting test of lead-free solder balls on a copper board. The developed no-flow underfill formulations show sufficient fluxing capability and good potential for lead-free solder bumped flip-chip applications     

CMOS LSI-based multichip flexible neural stimulation device with embedded bulk Pt electrodes

A CMOS LSI-based flexible neural stimulation device application with new fabrication technologies has been developed. The device was designed for application in retinal prosthesis. The device is based on multichip architecture, which enables the LSI-based stimulation device to be flexible. A fabrication process of arrayed bulk Pt electrodes, and a packaging structure of LSI chips with flip-chip bonding technology have been developed. These features provide the fabricated device with a lifetime of ten days in saline solution     

Electrical and optical characterization of GaN-based light-emitting diodes fabricated with top-emission and flip-chip structures

We investigated the electrical and optical characteristics of GaN-based light-emitting diodes (LEDs) fabricated with top-emission and flip-chip structures. Compared with top-emission LEDs, flip-chip LEDs exhibited a 0.25 V smaller forward voltage and an 8.7 Ω lower diode resistance. The light output power of the flip-chip LED was also larger than that of the top-emission LED by factors of 1.72 and 2.0 when measured before and after packaging, respectively. The improved electrical and optical output performances of flip-chip LEDs were quantitatively analyzed in terms of device resistance and ray optics, respectively.     

A reliable and environmentally friendly packagingtechnology-flip-chip joining using anisotropically conductive adhesive

There is an increasing demand to move the radio base station closer to the antenna for future mobile telecommunication systems. This requires a significant reduction in weight and volume and increased environmental compatibility. This work provides an evaluation of environmental impact and reliability when using anisotropically conductive adhesives (ACA) for flip-chip joining in radio base station applications. Conventional FR-4 substrate has been used to assemble a digital ASIC chip using an anisotropically conductive adhesive and flip-chip technology. The chip has a minimum pitch of 128 μm with 7.8 mm in chip 8 and has in total 144 bumps with a bump size of 114×126 μm². Bumping was made using electroless nickel/gold technology. Bonding quality has been characterized by optical and scanning electron microscopy and substrate planarity measurement. The main parameters affecting quality are misalignment and softening of the FR-4 substrate during assembly, leading to high joint resistance. Reliability testing was conducted in the form of a temperature cycling test between -40 and ±125°C for 1000 cycles, a 125°C aging test for 100 h and a 85/85 humidity test for 500 h. The results show that relatively small resistance changes were observed after the reliability test. The environmental impact evaluation was done in the form of a material content declaration and a life cycle assessment (LCA). By using flip-chip ACA joining technology, the content of environmentally risky materials has been reduced more than ten times, and the use of precious metals has been reduced more than 30 times compared to conventional surface mount technology