Reliability of Single-Error Correction Protected Memories

Reliability is a critical factor for systems operating in radiation environments. Among the different components in a system, memories are one of the parts most sensitive to soft errors due to their relatively large area. Due to their large cost, traditional techniques like Triple Modular Redundancy are not used to protect memories. A typical approach is to apply Error Correction Codes to correct single errors, and detect double errors. This type of codes, for example those based on Hamming, provides an initial level of protection. Detected single errors are usually corrected using scrubbing, by which the memory positions are periodically re-written after a fixed (deterministic scrubbing), or variable period (probabilistic scrubbing). These traditional models usually offer good results when calculating the reliability of memories (e.g. through the Mean Time To Failure). However, there are some particularities that are not modeled through these approaches, to the best of our knowledge. One of these particularities is how double errors are handled. In a traditional approach, two errors in the same word produce always a system failure (only single errors can be corrected). However, if the two (or more) errors affect the same bit, either the second one reinforces the first one (keeping just a single error), or corrects it. In both scenarios, the resulting situation does not trigger a system failure, which has a direct impact on the reliability of the memory. In this paper, traditional reliability models are refined to handle the mentioned scenarios, which produces a more precise analysis in the calculation of mean time to failure for memory systems.      

Reliability Modeling and Analysis of Fault-Tolerant Memories

A memory array reliability model is developed that can be applied to a wide range of memory organizations including random-access memories (RAM) and read-only memories (ROM). The model is particularly useful for computing the reliability of fault-tolerant memories that employ techniques such as hardware redundancy, error-correcting codes, and software error-correcting algorithms. The model accommodates the effect of faults masked by data. Reliability models that incorporate the array model are given for a simplex RAM, an N-modular-redundant RAM, a spared RAM, a single-error-correcting RAM, a multiple-error-correcting RAM, and a ROM. Reliability characteristics of these memories are compared. The results suggest that memories with error-correcting capability and spare bit-planes provide the best reliability. Memories with sparing at the array level are next best followed by NMR and simplex organizations. ROM reliability is shown to be more optimistic when masked faults are considered.     

Energy-Aware Flash Memory Management in Virtual Memory System

The traditional virtual memory system is designed for decades assuming a magnetic disk as the secondary storage. Recently, flash memory becomes a popular storage alternative for many portable devices with the continuing improvements on its capacity, reliability and much lower power consumption than mechanical hard drives. The characteristics of flash memory are quite different from a magnetic disk. Therefore, in this paper, we revisit virtual memory system design considering limitations imposed by flash memory. In particular, we focus on the energy efficient aspect since power is the first-order design consideration for embedded systems. Due to the write-once feature of flash memory, frequent writes incur frequent garbage collection thereby introducing significant energy overhead. Therefore, in this paper, we propose three methods to reduce writes to flash memory. The HotCache scheme adds an SRAM cache to buffer frequent writes. The subpaging technique partitions a page into subunits, and only dirty subpages are written to flash memory. The duplication-aware garbage collection method exploits data redundancy between the main memory and flash memory to reduce writes incurred by garbage collection. We also identify one type of data locality that is inherent in accesses to flash memory in the virtual memory system, intrapage locality. Intrapage locality needs to be carefully maintained for data allocation in flash memory. Destroying intrapage locality causes noticeable increases in energy consumption. Experimental results show that the average energy reduction of combined subpaging, HotCache, and duplication-aware garbage collection techniques is 42.2%.     

嵌入式存储器MBIST设计中内建自诊断功能研究

针对大规模嵌入式存储器可测性设计技术——存储器内建自测试（MBIST）中的故障诊断问题,介绍了MBIST设计的扩展功能——存储器内建自诊断（MBISD）。在引入存储器内建自测试的基础上,详细分析了存储器内建自诊断模块根据输出故障信息自动分析器件失效原因、并对失效单元进行故障定位和识别的基本原理及其中的关键算法,并用一块SRAM的MBIST设计（采用Mentor公司的MBISTArchitect完成）中的MBISD具体实例进行了仿真验证。存储器内建自诊断的应用,大大提高了存储器的成品率。     

内存芯片封装技术的发展

本文主介绍了国际上内存芯片封装技术的现状以及未来的发展等。     

内存芯片封装技术的发展

本文主要介绍了国际上内存芯片封装技术的现状以未来的发展等．     

GPS基带芯片中存储器的可测性设计

GPS基带芯片中嵌入的存储器采用存储器内建自测试(Memory Built-in-Self-Test,MBIST)技术进行可测性设计,并利用一种改进型算法对存储器内建自测试电路的控制逻辑进行设计,结果表明整个芯片的测试覆盖率和测试效率均得到显著提高,电路性能达到用户要求,设计一次成功.     

单片机自身的可靠性技术发展

本文介绍单片机目前的发展趋势，以及在提供系统可靠性方面单片机自身的技术发展，以便于用户选用单片机来实现高可靠性的单片机应用系统。     

单片机系统中大容量数据存储器的系统扩展

在单片机应用系统中，有一些特殊的应用场合需要大容量的数据存储器，文章根据作者实际使用的应用系统，介绍了一种大容量数据存储器的扩展方法，包括其硬件组成及软件处理方法。     

一种单片机虚拟实验室的建立方法

为了解决传统基于硬件的单片机实验室诸多弊端,建立基于PC和软件的虚拟实验室,即在Proteus中建立单片机硬件系统,通过Keil和Proteus的连接实现单片机系统的软硬件调试,通过虚拟串口实现上下位机的联合仿真调试.与现有基于Proteus的虚拟实验室相比,不仅实现了下位机的仿真调试,更实现了包括上位机在内的联合调试的虚拟环境.实验证明,该方法可用于单片机学习和单片机项目开发的前期工作,具有一定的实用性和工程应用价值.     

一种高可靠性上电复位芯片的设计

为了解决传统上电复位电路二次上电时易失效的问题,提出以比较器结构为基础,由带隙基准、电阻网络和逻辑电路等组成的高可靠性的上电复位解决方案.并增加复位延时电路,进一步提高复位可靠性.使用0.6 μm双层多晶硅N阱CMOS工艺模型,利用HSpice对其功能仿真,结果表明该电路3.3 V工作电压下的阈值电压为3.08 V,复位延时时间为100 ms,能稳定可靠地提供复位信号,可适用于电脑、微控制器以及便携式电子产品的电源监控.     

声表面波器件压电芯片粘接工艺的可靠性研究

对声表面波(SAW)器件失效模式以及SAW器件粘片分离模式进行了初步分类和探讨，通过对粘片工序几种分离模式的对比试验，总结了一套针对该工序的较为完整的粘片可靠性增长的控制措施。     

IC芯片凸点的制作与可靠性考核

用多种方法制作了Ａｕ凸点、Ｃｕ／Ａｕ凸点、Ｎｉ／Ａｕ凸点、Ｃｕ／Ｐｂ－Ｓｎ凸点及Ｃ４凸点微型Ａｕ凸点直径为１０μｍ,间距３０μｍ高度５～８μｍ,芯片上微凸点近１０００个,还对各种不同的制作方法进行了研究,并对芯片凸点的可靠性进行了一定的考核,效果良好。文中给出一组试验芯片的Ｃｕ／Ｐｂ－Ｓｎ凸点可靠性考核数据：经１２５℃,１０００ｈ电老化,其接触电阻变化范围为０．１％～０．７％,经－５５℃～＋１２５     

Optimizing Trade-Offs of Reliability vs Weight

The necessary mathematical conditions are derived for maximizing system reliability for a given system weight or minimizing system weight for a given reliability. Cost may also be introduced. Several efficient methods of calculation are reviewed for determining the optimized reliability-weight relations.     

Reliability vs component tolerances in microelectronic circuits

It is well known that the reliability of a circuit can be increased by designing it for worst-case conditions so that, even if component characteristics drift, the circuit will still operate satisfactorily. However, it is shown in this paper that extreme worst-case design can lead to increased operating temperature and, therefore, again reduced reliability. A method, illustrated by two practical examples, is indicated to find the compromise in component and circuit design tolerances leading to maximum reliability at any specified time or over any specified time interval.     

用于低开销容错设计的存储部件可靠性评估研究

低开销容错技术是当前软错误研究领域的热点。为了对微处理器进行低开销容错保护,首先就需要对微处理器可靠性(即体系结构弱点因子AVF (Architectural Vulnerability Factor))进行准确评估。然而,现有的AVF评估工具的精确性和适用范围都受到不同程度的限制。该文以微处理器上的核心部件(即存储部件)作为研究对象,对AVF评估方法进行改进,提出了一种访存操作分析和指令分析相结合的AVF评估策略HAES (Hybrid AVF Evaluation Strategy)。该文将HAES融入到通用的模拟器中,实现了更精确和更通用的AVF评估框架。实验结果表明相比其它AVF评估工具,利用该文提出的评估框架得到的AVF平均降低22.6%。基于该评估框架计算得到的AVF更加精确地反映了不同应用程序运行时存储部件的可靠性,对设计人员对微处理器进行低开销的容错设计具有重要指导意义。     

一种1kb相变存储芯片的设计

以中科院上海微系统与信息技术研究所自主研发的相变存储器工艺为基础,开发了一款容量为1 kb、可应用于射频标签(RFID)的嵌入式相变存储芯片.该芯片以1T1R为基本单元结构,采用箝位读出方式以及电流镜式写驱动电路,成功实现了相变存储器的读写功能.测试结果显示,该芯片可重复擦写次数达到107次,在80℃条件下数据保持力达...     

CSP引发内存封装技术的革命

简要介绍了几种内存芯片封装技术的特点。CSP是内存芯片封装技术的新概念,它的出现促进内存芯片的发展和革新,并将成为未来高性能内存的最佳选择。