Electrothermal simulation of an IGBT PWM inverter

An electrothermal network simulation methodology is used to analyze the behavior of a full-bridge, pulse-width-modulated (PWM), voltage-source inverter, which uses insulated gate bipolar transistors (IGBTs) as the switching devices. The electrothermal simulations are performed using the Saber circuit simulator and include control logic circuitry, IGBT gate drivers, the physics-based IGBT electrothermal model, and thermal network component models for the power-device silicon chips, packages, and heat sinks. It is shown that the thermal response of the silicon chip determines the IGBT temperature rise during the device switching cycle. The thermal response of the device TO247 package and silicon chip determines the device temperature rise during a single phase of the 60-Hz sinusoidal output. Also, the thermal response of the heat sink determines the device temperature rise during the system startup and after load-impedance changes. It is also shown that the full electrothermal analysis is required to accurately describe the power losses and circuit efficiency     

Electrothermal modelling of GaAs MESFETs

In this paper a new analytic electrothermal model of a GaAs FET is proposed in order to evaluate the thermal field in the semiconductor body for an easy, fast and reliable layout design using a personal computer. The contribution to the thermal resistance of all the top and bottom layers of a typical chip and the interaction of the channel temperature with the drain current are taken into account. A comparison with a three-dimensional finite-difference simulator and experimental data confirms the accuracy of the model. The CAD tool in which the mathematical model has been implemented can be used for the layout design since it is able to calculate the optimal spacing between contiguous devices to minimize the mutual thermal coupling and also the optimal number of gate fingers and gate-to-gate spacing of a single power device with a multigate layout. The proposed technique is general and can be applied to silicon as well as to heterojunction FET devices.     

Development and characterisation of pressed packaging solutions for high-temperature high-reliability SiC power modules

SiC is a wide bandgap semiconductor with better electrothermal properties than silicon, including higher temperature of operation, higher breakdown voltage, lower losses and the ability to switch at higher frequencies. However, the power cycling performance of SiC devices in traditional silicon packaging systems is in need of further investigation since initial studies have shown reduced reliability. These traditional packaging systems have been developed for silicon, a semiconductor with different electrothermal and thermomechanical properties from SiC, hence the stresses on the different components of the package will change. Pressure packages, a packaging alternative where the weak elements of the traditional systems like wirebonds are removed, have demonstrated enhanced reliability for silicon devices however, there has not been much investigation on the performance of SiC devices in press-pack assemblies. This will be important for high power applications where reliability is critical. In this paper, SiC Schottky diodes in pressure packages have been evaluated, including the electrothermal characterisation for different clamping forces and contact materials, the thermal impedance evaluation and initial thermal cycling studies, focusing on the use of aluminium graphite as contact material.     

Steady state thermal characterization and junction temperatureestimation of multichip module packages using the response surfacemethod

The steady state thermal performance of semiconductor packages has been traditionally reported through the utilization of a single junction-to-ambient thermal resistance constant commonly referred to as &thetas;_ja. This is particularly inadequate for multichip modules where several devices reside within the same package structure. This paper discusses how a central composite design of experiments can be applied to provide a more accurate thermal characterization of a multichip module package. The end product is a series of linear or polynomial equations which can be utilized by the customer to calculate individual device junction temperatures over a wide variation of convection cooling environments and multiple device power dissipations. A 352 plastic ball grid array package, which encompasses three individual integrated circuit devices, is used as an example. The paper steps through the sensitivity analysis and evaluates the accuracy of the resulting equations. This method of thermal characterization can be easily applied to single chip modules of varying power and cooling regimes, or multiple output devices where several power junctions reside within the same integrated circuit     

Spatially resolved thermal characterization of packaged verticalcavity surface-emitting lasers

The experimental thermal characterization of ion implanted vertical cavity surface-emitting lasers (VCSELs) and their own packages was carried out by means of an enhanced version of the thermal resistance analysis by induced transient (TRAIT) based on the analysis of the heat source temperature transients. This technique allowed the measurement of the thermal resistance of the device-package system with a spatial resolution so that the heat conduction properties of all the parts of the structure were separately and directly evaluated. The increased time and temperature resolution of the experimental measuring set-up allowed us to calculate up to 12 rows of the time constant spectrum and therefore to obtain equivalent thermal circuits with 12 resistance-capacitance low-pass cells. The experiments performed on packaged devices from different manufacturers enabled us to identify the origin of possible critical points of the assembling structures, despite their negligible contributions to the total thermal resistance in comparison to those of the semiconductor chip. The experimental results were also found to be in agreement with the data obtained using analytical models for the calculation of the thermal resistance in such laser devices     

Analytical approach to temperature evaluation in bonding wires andcalculation of allowable current

Wirebonding is still the most common technique being applied to device assembly. Since the entire electrical power for the chip has to be delivered through the wires, considerable current densities may occur. As a result, bond wires are heated up and in case of too excessive current wires or surrounding materials might suffer and subsequently fail. In order to increase reliability of semiconductor devices it is important to know the resultant temperature due to a given current and deduced from this, the allowable loading so that a maximum temperature will not be exceeded. In this paper universally valid formulas for steady state, single pulse and periodic loading are introduced. They are derived from the heat diffusion equation resulting from a mathematical model which is proposed for simplification. In case of ceramic packages radiation and convection effects are considered whereas conduction through the molding compound is taken into account if the wire is encapsulated in plastic. The formulas also enable comparison between the effects of heat conduction through the wire and through the molding compound. Besides, the system of differential equations considers the temperature dependence of the specific resistance and the thermal conductivity of the wire material. Corrections for very thin plastic packages and multiple bonding are suggested. The formulas have been checked by both experimental data and numerical computation by means of Finite Element Analysis     

Integrated electro-thermomechanical analysis of nonuniformly chip-powered microelectronic system

An integrated electrical, fluid flow and thermomechanical analysis is presented to study a product reliability and thermal management solution in an actual or nonuniform chip power distribution of an integrated circuit device in a realistic system application environment. This study aims to improve the existing limitations both on electrothermal analysis where simplified thermal boundary conditions is mostly used and on the current thermal and fluid flow analysis where uniform chip power is widely used to calculate the temperature. In this approach, the localized on-chip power distribution is obtained by using a transistor-level circuit model for simulating the interaction between the macro and functional blocks. A computational fluid dynamics analysis is used to calculate the fluid flow and heat transfer solution with a realistic thermal boundary conditions. To address the ultimate thermal induced mechanical stress and reliability effects on the chip-packaged assembly due to the nonuniform chip power distribution, finite element model is employed for the sequential steady-state heat transfer and mechanical analysis. The results are then discussed and specifically compared with the solutions based on the uniform chip power conditions.     

Cost-effective chip-on-heat sink leadframe package for 800-Mb/s/lead applications

Chip-on-heat sink leadframe (COHS-LF) packages offer a simple, low-cost chip encapsulation structure with advanced electrical and thermal performance for high-speed integrated circuit applications. The COHS-LF package is a novel solution to the problems of increased power consumption and signal bandwidth demands that result from high-speed data transmission rates. Not only does it offer high thermal and electrical performance, but also provides a low-cost short time-to-market package solution for high-speed applications. In general, there are two main memory packages employed by the most popular high-speed applications, double data rate (DDR) SDRAM. One is the cheaper, higher parasitic leadframe packages, such as the thin small outline packages (TSOPs), and the other is the more expensive, lower parasitic substrate-based packages, such as the ball grid array (BGA). Due to the requirement for higher ambient temperature and operating frequency for high-speed devices, DDR2 SDRAM packages were switched from conventional TSOPs to more expensive chip-scale packages (i.e., BGA) with lower parasitic effects. And yet, by using an exposed heat sink pasted on the surface of the chip and packed in a conventional leadframe package, the COHS-LF is a simpler, lower cost design. Results of a three-dimensional full-wave electromagnetic field solver and SPICE simulator tests show that the COHS-LF package achieves less signal loss, propagation delay, edge rate degradation, and crosstalk than the BGA package. Furthermore, transient analysis using the wideband T-3/spl pi/ models optimized up to 5.6 GHz for signal speeds as high as 800 Mb/s/lead demonstrates the accuracy of the equivalent circuit model and reconfirms the superior electrical characteristics of COHS-LF package.     

Electrothermal simulation of multichip-modules with novel transient thermal model and time-dependent boundary conditions

The ability of monitoring the chip temperatures of power semiconductor modules at all times under various realistic working conditions is the basis for investigating the limits of the maximum permissible load. A novel transient thermal model for the fast calculation of temperature fields and hot spot temperature evolution presented recently is extended to include time-dependent boundary conditions for variations of ambient temperature and surface heat flows. For this a Green's function representation of the temperature field is used. Also, general initial temperature conditions are included. The method is exemplified by application to a dc/ac converter module for automotive hybrid drives. The thermal model, which can be represented by a thermal equivalent circuit, then is combined with an electrical PSpice-metal-oxide semiconductor field-effect transistor (MOSFET) model to allow for the fully self-consistent electrothermal circuit simulation of 42-V/14-V dc/dc-converter modules. 670 converter periods with altogether 8000MOSFET switching cycles in the six-chip module can be simulated within 1-h computing time on a Pentium PC. Various simulation results are presented, which demonstrate the feasibility of the simulation method and allow for the optimization of converter losses. Short circuit modes of converter operation are investigated with a high temperature increase also revealing the thermal interaction between different chips.     

半导体激光抽运源大通道水冷热沉的接口设计

针对普通大功率半导体激光抽运源用大通道水冷热沉热阻高、工作时热沉表面在大通道水流方向存在明显温升进而导致加载其上的激光bar寿命不一致以及抽运源整体光谱宽度难以控制的问题,利用商用有限元软件ANSYS仿真获得抽运源工作时不同冷却水流量条件下热沉内部温度场分布,分析该结构热沉热阻系统的构成及整体热阻瓶颈所在。实际中通过改变冷却水接口结构,获得“入口效应”,提高了大通道热沉整体换热性能,进一步减小热沉表面温度梯度。利用所设计的新接口大通道水冷热沉获得3 bar线阵120 W连续(CW)输出半导体激光器抽运源,输出中心波长为807.7 nm,光谱宽度(FWHM)为2.8 nm。     

Thermal design of a broadband communication system with detailed modeling of TBGA packages

This paper presents a thermal modeling of a broadband network communication box partitioned into two stacked modules. A printed circuit board (PCB) is inside each module where an array of 16 tape ball grid array (TBGA) packages is surface mounted to the PCB. The TBGA package dissipates 6 W power each. In addition, 12 W of power is dissipated from four plastic ball grid array (PBGA) packages on the PCB. Pin-fin heat sinks are attached to the TBGA packages using silica-filled epoxy to enhance heat dissipation. Pin-fin heat sinks are also attached to the PBGA packages. Two exhaust fans are mounted at the flow exit to draw ambient air into the system at approximately 200 linear feet per minute (LFM) of velocity. The full Navier–Stokes equations for airflow are solved to simulate the forced convection cooling in the electronic module. Buoyancy effect was considered in the numerical model by incorporating Boussinesq-approximation. The TBGA packages are modeled in detail in order to obtain the package junction temperatures for system reliability evaluation and thermal design optimization. Detailed models of the attached pin-fin heat sinks and the epoxy interfaces are also utilized in this study. Compact heat sink model composed of a base plate and a resistance fluid volume is applied to model heat dissipation from the heat sinks attached to the four PBGA packages. System fan curve is used to simulate the fan operating conditions. The effect of changing system thermal design on the TBGA package junction temperatures as well as the hydraulic operating conditions of the system fans are examined and reported herein. The effect of radiation heat transfer is also examined. The importance of detailed modeling of the high power TBGA packages is demonstrated in this study. Simulation results were compared with JEDEC thermal test data under similar conditions of airflow.     

超薄型圆片级芯片尺寸封装技术

ShellCase公司的圆片级封装技术工艺,采用商用半导体圆片加工设备,把芯片进行封装并包封到分离的腔体中后仍为圆片形式。圆片级芯片尺寸封装(WL-CSP)工艺是在固态芯片尺寸玻璃外壳中装入芯片。玻璃包封防止了硅片的外露,并确保了良好的机械性能及环境保护功能。凸点下面专用的聚合物顺从层提供了板级可靠性。把凸点置于单个接触焊盘上,并进行回流焊,圆片分离形成封装器件成品。WL-CSP封装完全符合JEDEC和SMT标准。这样的芯片规模封装(CSP),其测量厚度为300μm-700μm,这是各种尺寸敏感型电子产品使用的关键因素。     

Short-timescale thermal mapping of semiconductor devices

We report spatial mapping of temperature fields in semiconductor devices with sub-microsecond temporal resolution. The measurements are performed at a facility that integrates scanning laser-reflectance thermometry with electrical stressing capability. Data for SOI LDMOS transistors investigate transient heat diffusion within the buried silicon dioxide and capture large temperature gradients in the drift region, which result from the spatially-varying impurity concentration. The new thermometry facility is promising for the study of transistor and interconnect thermal failure due to electrostatic discharge (ESD)     

Thermal and package performance limitations in LDMOSFET's for RFICapplications

This paper presents a systematic study of the limitations imposed by thermal and packaging considerations on radio-frequency (RF) performance of Si bulk and silicon-on-insulator (SOI) lateral DMOSFET's (LDMOSFET's). Several bulk and SOI devices are studied with the help of measurements as well as two-dimensional device simulations incorporating electrothermal models. Model parameters are extracted and used in circuit simulators to perform RF characterization of these devices. Further, a new three-region theory for the LDMOSFET is discussed and used to evaluate the static and RF performance of the devices in a nonisothermal environment. This paper shows that the package plays an important role in RF performance of SOI and bulk devices due to self-heating effects within the device. A detailed DC and RF performance evaluation is presented. Significant drift is observed in RF performance of bulk and SOI devices due to self-heating considerations. The physical understanding of these thermal effects within the device can facilitate the design of better packages for bulk and SOI devices     

Improved thermal characterization method of integrated microscale heat sinks

The thermal management of semiconductor devices is still a hot topic. Most designers, who are aware of the thermal aspects of IC design, know that new, cheaper and more efficient methods are required to keep the temperature of electronic systems low. Research by different teams regarding the cooling of stacked die structures is in progress.In this paper an improved thermal characterization method will be presented to determine the flow dependent partial thermal resistance of integrated microchannel based heat sinks. This reliable characterization method does not demand thermal isolation during the measurements, only constant environment conditions. The measurements are based on the industrial standard thermal transient testing method.On the other hand we present an approach to realize an integrated microfluidic channel based heat sink, which can be realized in the backside of the silicon chip itself. The approach is based on a cheap wet etching process instead of reactive ion etching or LIGA technologies, which enables batch processing.     

Electro-thermal simulation including a temperature distribution inside power semiconductor devices

The idea of including non-uniform temperature distribution into power semiconductor device models is not new, as accurate electro-thermal simulations are required for designing compact power electronic systems (as integrated circuits or multi-chip modules). Electro-thermal simulations of a PIN-diode based on the finite-element method, show a non-uniform temperature distribution inside the device during switching transients. Hence the implicit assumption of a uniform temperature distribution when coupling an analytical electrical model and a thermal model yields inaccurate electro-thermal behaviour of the PIN-diode so far. If literature reports procedures regarding complex thermal network modelling, few papers address the problem of mixing adequately electrical and thermal issues. Instead of using a one-dimensional finite difference or element method, the bond graphs and the hydrodynamic method are used to build a 1D electro-thermal model of the PIN-diode. The paper focuses on electrical issues and the proper expression and localization of power losses to feed the thermal network model. The results by this original technique are compared with those given by a commercial finite-element simulator. The results are similar but the computation effort attached to the proposed technique is a fraction of that required by finite-element simulators. Moreover the proposed technique may be applied easily to other power semiconductor devices.     

A structure oriented compact thermal model for multiple heat source ASICs

This paper proposes a methodology for the extraction of a compact thermal model for multiple heat source devices, which can be used for estimation of the overall temperature field. This extraction is based on the physical parameters as well as on the layout and the packaging of the device. The model directly represents the regions surrounding a source by a resistance network containing the specific parameters of source and chip in analytical form, so that it is easy to vary parameters like power dissipation and thermal conductivity within a wide range. In order to obtain a good and fast approximation of the continuous case, the shape of the volume elements represented by a node in the network is chosen regarding the direction of the heat flow within these elements. Therefore these volume elements are not rectangular but pyramid- or parallelogram-like structures. The temperature fields of multiple sources add up for the total temperature distribution, by the use of a matrix field representation.     

超大面积芯片烧结技术研究

随着半导体大功率器件的发展,芯片的散热一直是制约功率器件发展的因素之一。而器件内部散热主要是通过芯片背面向外传导,芯片焊接工艺是直接影响器件散热好坏的关键因素之一,合金焊料的一个显著优点就是其导热性能好,因此在散热要求高的大功率器件中使用较为广泛(如Au80Sn20、Au99.4Sb0.6等),但由于合金焊料烧结后会产生较大的残余应力,在尺寸大于8 mm×8 mm的芯片上,烧结工艺应用较少。文章针对11.5 mm×11.5 mm超大面积芯片进行金锡合金烧结试验,经过对应力产生的原因进行分析,从材料、封装工艺等方面采取措施来降低缓释应力,并对封装产品进行可靠性考核验证。试验结果表明,没有芯片存在裂纹、碎裂现象,产品通过了可靠性验证。     

Electrothermal analysis of the self-excited push-pull DC-DC converter

The SPICE-aided electrothermal analysis of a self-excited push-pull DC-DC converter is considered in the paper. The new electrothermal model of a pulse transformer, which constitutes the basic component element of the considered converter, is proposed. This model contains among others: two different temperatures of the windings and the core, the influence of temperature on losses in the core and in the windings, the dependence of the magnetization curve on the core temperature, the Curie temperature, selfheating and mutual thermal interactions between the core and the windings. The semiconductor devices are described with the use of the hybrid electrothermal models. The measurements and electrothermal calculations of the characteristics of the investigated converter with the use of the models proposed in the paper are performed. A good agreement between the results of the calculations and the measurements achieved with this model testifies to correctness of the presented models.