Investigation of iridium as a gate electrode for deep sub-micron CMOS technology

The physical and electrical properties of an Ir/SiO₂/Si stack were evaluated for advanced gate electrode application. The thermal stability of the stack was studied on MOS capacitors annealed at temperatures between 500 and 1000 °C in N₂ ambient for 30 s followed by forming gas anneal (FGA) at 420 °C for 20 min. The work function of iridium, found to be 4.9 eV, is stable up to 900 °C, making it a good candidate as PMOS electrode. In addition, no evidence was found for any chemical reaction at the interface between Ir and SiO₂.     

Characterization of P-channel power trench MOSFETs with polycrystalline silicon germanium gate electrode for faster switching

Electrical switching characteristics using polycrystalline silicon–germanium (poly-Si_l?xGe_x) gate for P-channel power trench MOSFETs was investigated. Switching time reduction of over 22% was observed when the boron-doped poly-Si gate was replaced with a similarly boron-doped poly-SiGe gate on the P-channel power MOSFETs. The fall time (T_f) on MOSFETs with poly-SiGe gate, was found to be ～11 ns lesser than the poly-Si gate MOSFET which is ～60% improvement in switching performance. However, all the switching improvement was observed during the fall times (T_f). The reason could be the higher series resistance in the switching test circuit masking any reduction in the rise times (T_r). Faster switching is achieved due to a lower gate resistance (R_g) offered by the poly-SiGe gate electrode as compared to poly-silicon (pSi) material. The pSi gate resistance was found to be 6.25 Ω compared to 3.75 Ω on the poly-SiGe gate measured on the same device. Lower gate resistance (R_g) also means less power is lost during switching thereby less heat is generated in the device. A very uniform boron doping profile was achieved with-in the pSiGe gate electrode, which is critical for uniform die turn on and better thermal response for the power trench MOSFET. pSiGe thin film optimization, properties and device characteristics are discussed in details in the following sections.     

Growth of lanthanum oxide films for application as a gate dielectric in CMOS technology

We have investigated properties of insulating lanthanum oxide (La₂O₃) films in connection with the replacement of silicon oxide (SiO₂) gate dielectrics in new generation of CMOS devices. The La₂O₃ layers were grown using metal organic chemical vapour deposition (MOCVD) at 500 °C. X-ray diffraction analysis revealed polycrystalline character of the films grown above 500 °C. The X-ray photoemission spectroscopy detected lanthanum carbonate as a principal impurity in the films and lanthanum silicate at the interface with silicon. Density of oxide charge, interface trap density, leakage currents and dielectric constant ( κ) were extracted from the C-V and I-V measurements. Electrical properties, in particular dielectric constant of the MOCVD grown La₂O₃ are discussed with regard to the film preparation conditions. The as grown film had κ11. Electrical measurements indicate possible presence of oxygen vacancies in oxide layer. The O₂-annealed La₂O₃ film had κ17.     

A high-performance polycrystalline silicon thin film transistorwith a silicon nitride gate insulator

We have fabricated a high performance polycrystalline silicon (poly-Si) thin film transistor (TFT) with a silicon-nitride (SiN_x ) gate insulator using three stacked layers: very thin laser of hydrogenated amorphous silicon (a-Si:H), SiN_x and laser annealed poly-Si. After patterning thin a-Si:H/SiN_x layers, gate, and source/drain regions were ion-doped and then Ni layer was deposited. This structure was annealed at 250°C to form a NiSi silicide phase. The low resistive Ni silicides were introduced as gate/source/drain electrodes in order to reduce the process steps. The poly-Si with a grain size of 250 nm and low resistance n⁺ poly-Si for ohmic contact were introduced to achieve a high performance TFT. The fabricated poly-Si TFT exhibited a field effect mobility of 262 cm²/Vs and a threshold voltage of 1 V     

Electrical properties of oxidized polycrystalline silicon as a gate insulator for n-type 4H-SiC MOS devices

MOS capacitors were produced on n-type 4H-SiC using oxidized polycrystalline silicon (polyoxide). The polyoxide samples grown by dry oxidation without an anneal had a high interface state density (D_it) of 1.8 × 10¹² cm⁻² eV⁻¹ and the polyoxide samples grown by wet oxidation had a lower D_it of 1.2 × 10¹² cm⁻² eV⁻¹ (both at 0.5 eV below the conduction band). After 1 h Ar annealing, the D_it of wet polyoxide was reduced significantly to 2.6 × 10¹¹ cm⁻² eV⁻¹ (at 0.5 eV below the conduction band). Dry polyoxide exhibits higher breakdown electric fields than wet polyoxide. The interface quality and breakdown characteristics of polyoxide are comparable to published results of low-temperature CVD deposited oxides.     

Thermally robust HfN metal as a promising gate electrode for advanced MOS device applications

A systematic study of thermally robust HfN metal gate on conventional SiO/sub 2/ and HfO/sub 2/ high-/spl kappa/ dielectrics for advanced CMOS applications is presented. Both HfN-SiO/sub 2/ and HfN-HfO/sub 2/ gate stacks demonstrates robust resistance against high-temperature rapid thermal annealing (RTA) treatments (up to 1000/spl deg/C), in terms of thermal stability of equivalent oxide thickness (EOT), work function, and leakage current. This excellent property is attributed to the superior oxygen diffusion barrier of HfN as well as the chemical stability of HfN-HfO/sub 2/ and HfN-SiO/sub 2/ interfaces. For both gate dielectrics, HfN metal shows an effective mid-gap work function. Furthermore, the EOT of HfN-HfO/sub 2/ gate stack has been successfully scaled down to less than 10 /spl Aring/ with excellent leakage, boron penetration immunity, and long-term reliability even after 1000/spl deg/C annealing, without using surface nitridation prior to HfO/sub 2/ deposition. As a result, the mobility is improved significantly in MOSFETs with HfN-HfO/sub 2/ gate stack. These results suggest that HfN metal electrode is an ideal candidate for ultrathin body fully depleted silicon-on-insulator (SOI) and symmetric double-gate MOS devices.     

A low-temperature metal-doping technique for engineering the gate electrode of replacement metal gate CMOS transistors

This work describes a low-temperature metal annealing technique that can be a helpful tool for fabricating the gate electrode of replacement metal gate CMOS transistors. The goal of the technique is to form doped metal (TaSiN, TiSiN, TaCN, TaPN, etc.) to change the work function of the metal gate electrode. The low-temperature doping process was performed in an ambient containing the precursors of the dopants, including silane, phosphine, and carbon-rich organic precursors. Experiments have been conducted to incorporate dopants such as P, C, Si into TaN or TiN. The transistor and C-V data show the resultant doped metals are suitable materials for P- and N-MOSFETs by providing the right metal work function.     

A new conduction model for polycrystalline silicon films

A new quantitative electrical model is introduced to solve earlier modeling inadequacies in polycrystalline silicon films. An analytical J-V expression is developed in normalized closed form, which includes the thermionic field emission through a space-charge potential barrier and through a grain-boundary scattering potential barrier and the thermionic emission over these barriers. The modeling validity has been verified experimentally for films with grain sizes of 230 to 1220 Å, doping concentrations from 1 × 10¹⁶to 8 × 10¹⁹cm^-3and over a temperature range from -176° to 144°C.     

A polycide gate electrode with a conductive diffusion barrierformed with ECR nitrogen plasma for dual gate CMOS

A simple diffusion barrier technology for polycide gate electrodes is presented. An extremely thin silicon nitride layer is formed by poly Si surface nitridation with ECR nitrogen plasma of only nitrogen gas and without substrate heating. The silicon nitride layer acts as an excellent barrier to impurity diffusion from polysilicon to silicide. It was found that barrier formation with ECR nitrogen plasma results in no fatal degradation in the MOS interface characteristics. This technology is very effective for making dual polycide gates inexpensively due to its simplicity and a good affinity with conventional ULSI fabrication processes     

Resistivity of phosphorus-doped sputter-deposited polycrystalline silicon films

The resistivity of phosphorus-doped sputter-deposited polycrystalline silicon films has been extensively investigated as a function of many technological parameters with the aim of establishing whether these films can be doped to the desired resistivity values for MOS applications. An empirical expression has been determined for a standard doping process which relates the final sheet resistance of the film to the deposition rate and to the temperature of an annealing treatment carried out before predeposition. Once specified the desired sheet resistance, the two above parameters can be chosen in such a way as to minimize the annealing temperature, if high-temperature processing is to be prevented.     

Ultrathin gate oxide grown on nitrogen-implanted silicon for deepsubmicron CMOS transistors

Nitrogen implantation on the silicon substrate was performed before the gate oxidation at a fixed energy of 30 keV and with the split dose of 1.0×10¹⁴/cm² and 2.0×10¹⁴ /cm². Initial O₂ injection method was applied for gate oxidation. The method is composed of an O₂ injection/N₂ anneal/main oxidation, and the control process is composed of a N₂ anneal/main oxidation. CMOS transistors with gate oxide thickness of 2 nm and channel length of 0.13 μm have been fabricated by use of the method. Compared to the control process, the initial O₂ injection process increases the amount of nitrogen piled up at the Si/SiO₂ interface and suppresses the growth of gate oxide effectively. Using this method, the oxidation retarding effect of nitrogen was enhanced. Driving currents, hot carrier reliability, and time-zero dielectric breakdown (TZDB) characteristics were improved     

A large-bias conduction model of polycrystalline silicon films

There exists a need for a large-bias conduction model of polysilicon films used in VLSI/ULSI and in high power integrated circuits. A large-bias conduction model has been developed by extending the emission-based models of Lu et al. (1983) and Mandurah et al. (1981) valid for small-bias, small-signal conditions. The following large-bias effects have been taken into account: (1) asymmetry of potential distribution around grain boundaries and (2) avalanche multiplication of carriers in the grain boundary layers at high electric fields. Since the exact nature of the grain boundary material is not yet known, and there is no direct method for determining the model parameters relating to grain boundaries, these were extracted by the parametric fitting of resistance versus temperature data of polysilicon resistors near room temperature with the above small-signal resistivity models modified by including Fermi-Dirac distribution. The model has been validated with experimental data on the current-voltage characteristics of ion-beam sputtered polysilicon resistors of different sizes and aspect ratios. The dependence of model parameters relating to grain boundary scattering and avalanche multiplication on the dimensions of resistors have been explained physically. The increased kink effect in polysilicon TFT's may also be predicted from the present theory. Some results on the I-V characteristics of polyresistors trimmed by high current pulses have been discussed qualitatively in the light of the present model. Although the model involves numerical integrations and a few iterations, it is reasonably fast in execution     

Physical structure of light-emitting porous polycrystalline silicon thin films

This paper reports the surface electronic structure of light-emitting porous polycrystalline silicon (PPS) using X-ray photoelectron spectroscopy (XPS). We find that the PPS films with strong photoluminescence (PL) effect can only be observed in thin film with trace amount of silicon nanoclusters and the luminescence can be enhanced remarkably with proper passivation of the PPS surface. Incomplete oxidation of silicon (Si³⁺ or Si²⁺) does not lead to visible PL. We further estimate that the average size of silicon nanoclusters is in the range of 20–30 Å in the sample having PL emission.     

Photoluminescence of silicon after deposition of polycrystalline diamond films

Low-temperature (5K) photoluminescence of silicon substrates in the range 0.8–1.2 eV is studied before and after deposition of polycrystalline diamond films. The diamond films were deposited in the microwave plasma onto high-purity dislocation-free silicon (with the resitivity ρ ≈ 3 kΩ cm) subjected to mechanical polishing or more delicate chemical and mechanical polishing. The deposition temperature was 750–850°C. In the photoluminescence spectra of the samples with the substrates polished chemically and mechanically, two lines, D ₁ and D ₂, corresponding to the dislocation-related emission are recorded. Generation of dislocations in the substrates is caused by efficient adhesion of the diamond film and, as a result, by internal stresses that relax with the formation of dislocations. The experimental spectra are practically identical to the photoluminescence spectra observed in silicon (ρ ≈ 100 Ω cm) with the density of dislocations ∼10⁴ cm⁻².     

SrHfO3 as gate dielectric for future CMOS technology

Thin epitaxial films of the high-κ perovskite SrHfO₃ were grown by molecular beam epitaxy on Si(100) and investigated by ellipsometry and X-ray photoelectron spectroscopy to determine its band gap and valence band offset. Conducting AFM shows a good correlation between topography and current mapping, pointing to direct tunneling conduction. Long channels MOSFETs with low equivalent oxide thickness (EOT) were fabricated and their channel mobility measured. Mobility enhancement can be achieved by post processing annealing in various gases but at the cost of interfacial regrowth. An alternative approach is to increase mobility without changing EOT is by electrically stressing the gate dielectric at ∼150 °C.     

Silicon-on-insulator approach for power IC's integrating verticalDMOS and polycrystalline silicon CMOS thin-film transistors

A novel approach for the monolithic integration of low-voltage logic and analog control circuits with vertical-current flow power transistors is described. This is achieved by fabricating a CMOS device family, using polycrystalline-silicon thin-film transistors (TFTs), on the field oxide of a single-crystal power device. Parasitic interactions between the control and power devices are eliminated in a simple, inexpensive, and easily manufacturable process. The technology is capable of supporting both MOS and bipolar power devices and the presence of the TFT circuits places no restriction on the maximum voltage or current of the power device. The TFTs exhibit good electrical characteristics and the power devices are not compromised by the addition of the TFT control circuits. This concept is demonstrated by the fabrication of a vertical DMOS power transistor with >100-V, >45-A capability, monolithically integrated with current-limiting and temperature-limiting functions     

Evaporated polycrystalline silicon films for photovoltaic applications - grain size effects

Vacuum deposited, polycrystalline silicon films were fabricated into planar photovoltaic diodes by double diffusion techniques. Scanning electron microscopy showed that the crystallites are columnar in shape, with grain lengths several times larger than grain diameters. The dependency of average grain diameter on deposition conditions is discussed. Secondary ion mass spectrometry was used to obtain doping profiles and junction depths. Dark and illuminated I-V curves, spectral responses, and minority carrier diffusion lengths are presented for photovoltaic devices having grain sizes in the range 0.2 to 5 μm. Samples formed on sapphire and on a special alkaline-earth aluminosillcate glass processed under the same conditions had similar photovoltaic characteristics. Data on open-circuit voltage, short-circuit current, and solar cell efficiency are presented as functions of average grain diameter.     

Laser forming of silicon films using nanoparticle precursor

Polycrystalline silicon films containing cubic silicon crystallites of size 3–4 μm have been formed on nickel substrates by fusing and sintering silicon nanoparticle precursors using a laser. A mechanism for the fusion and sintering of these nanoparticles, resulting in reduced heat input and continuous film formation by surface and grain boundary diffusion, is discussed. Films were characterized by optical microscopy, scanning electron microscopy, energydispersive spectroscopy, and Raman spectroscopy. Films were doped with n- as well as p-type dopants by using a laser doping technique and their current-voltage (I–V) characteristics were measured.     

Physical and electrical characteristics of HfN gate electrode for advanced MOS devices

In this letter, the physical and electrical properties of physical vapor deposited (PVD) hafnium nitride (HfN) is studied for the first time as the metal gate electrode for advanced MOS devices applications. It is found that HfN possesses a midgap work function in tantalum nitride (TaN)/HfN/SiO/sub 2//Si MOS structures. TaN/HfN stacked metal-gated MOS capacitors exhibit negligible variations on equivalent oxide thickness (EOT), leakage current, and work function upon high-temperature treatments (up to 1000 /spl deg/C), demonstrating the excellent thermal stability of HfN metal gate on SiO/sub 2/. Our results suggest that HfN metal electrode is an ideal candidate for the fully depleted SOI and/or symmetric double gate MOS devices application.     

A novel structure of silicon field emission cathode with sputteredTiW for gate electrode and TEOS oxide for gate dielectric

A novel silicon field emission cathode structure with a narrow spacing between tip and gate electrode is proposed, based on the filling characteristics of the sputtered Ti_0.1W_0.9 beneath the disc-shaped tip-mask oxide. Without advanced lithography technologies, the hole diameter of the gate is reduced to a sub-half-micrometer of ~0.4 μm from an initial tip-mask size of ~1.2 μm, and the gate electrode easily approaches the cathode, leading to a low-voltage operation. A uniform and stable field emission cathode is obtained using well-established VLSI process technologies. The current-voltage (I-V) characteristics of the cathodes show low turn-on voltages of ~30 V