Laser Bonding of Glass to Silicon Using Polymer for Microsystems Packaging

Laser joining is a promising technique for wafer-level bonding. It avoids subjecting the complete microelectromechanical system (MEMS) package to a high temperature and/or the high electric field associated with conventional wafer-level bonding processes, using the laser to provide only localized heating. We demonstrate that a benzocyclobutene (BCB) polymer, used as an intermediate bonding layer in the packaging of MEMS devices, can be satisfactorily cured by using laser heating with a substantial reduction of curing time compared with an oven-based process. A glass-on-silicon (Si) cavity bonded with a BCB ring can be produced in a few seconds at a typical laser intensity of 1 W/mm² resulting in a local temperature of ~300degC. Hermeticity and bond strength tests show that such cavities have similar or better performance than cavities sealed by commercial substrate bonders. The influence of exposure time, laser power, and applied pressure on the degree of cure, bond strength, and hermeticity is investigated. The concept of using a large area uniform laser beam together with a simple mirror mask is tested, demonstrating that such a mask is capable of protecting the center of the cavity from the laser beam; however, to prevent lateral heating via conduction through the Si, a high-conductivity heat sink is required to be in good thermal contact with the rear of the Si.     

Wafer-level BCB bonding using a thermal press for microfluidics

Benzocyclobutene (BCB) is a thermosetting polymer that can form microfluidics and bond top and bottom layers of the microfluidics at the same time, and yields high repeatability and high bonding strength. This paper reports using photosensitive BCB to fabricate microfluidics and to bond with a thermal press for 4 in. wafers. By optimizing the parameters for pattern development and using a three-stage temperature and pressure increment BCB bonding, we realize the whole wafer glass–Si or glass–glass bonding in thermal press without any crack. The wafer-level bonding shows a bonding percentage above 70%, a tensile stress above 4.94 MPa, and a bonding repeatability over 95%. Furthermore, the bonding is compatible with thick electrode integration, that microfluidics with 380 nm thick electrodes underneath can be well-bonded. Our bonding method much reduces the cost compared with bonding BCB in a wafer bonding machine. Electronic supplementary material  The online version of this article (doi:) contains supplementary material, which is available to authorized users.     

Wafer bonding with nano-imprint resists as sacrificial adhesive for fabrication of silicon-on-integrated-circuit (SOIC) wafers in 3D integration of MEMS and ICs

In this paper, we present the use of thermosetting nano-imprint resists in adhesive wafer bonding. The presented wafer bonding process is suitable for heterogeneous three-dimensional (3D) integration of microelectromechanical systems (MEMS) and integrated circuits (ICs). Detailed adhesive bonding process parameters are presented to achieve void-free, well-defined and uniform wafer bonding interfaces. Experiments have been performed to optimize the thickness control and uniformity of the nano-imprint resist layer in between the bonded wafers. In contrast to established polymer adhesives such as, e.g., BCB, nano-imprint resists as adhesives for wafer-to-wafer bonding are specifically suitable if the adhesive is intended as sacrificial material. This is often the case, e.g., in fabrication of silicon-on-integrated-circuit (SOIC) wafers for 3D integration of MEMS membrane structures on top of IC wafers. Such IC integrated MEMS includes, e.g., micro-mirror arrays, infrared bolometer arrays, resonators, capacitive inertial sensors, pressure sensors and microphones.     

InP dies transferred onto silicon substrate for optical interconnects application

We bonded quantum well InP dies on a photonic layer transferred on silicon CMOS processed wafer using direct molecular bonding. This approach is suitable for new applications, viz., photonics on silicon, 3D packaging and integrated sensors. The chips are diced from a bulk substrate and bonded directly onto a silicon substrate without any organic nor metallic adhesive layer. A thin silicon dioxide layer can be added on both assembled surfaces to enhance bonding quality. After bonding, the dies can mechanically be thinned down to 20 μm and chemically etched. The InAsP quantum well stack of the InP dies keeps its optoelectronics features and performances after being transferred onto a silicon substrate.     

Adhesive wafer bonding with photosensitive polymers for MEMS fabrication

Adhesive wafer bonding is a technique that uses an intermediate layer (typically a polymer) for bonding two substrates. The main advantages of using this approach are: low temperature processing (maximum temperatures lower than 400°C), surface planarization and tolerance to particles contamination (the intermediate layer can incorporate particles with the diameter in the layer thickness range). The main bonding layers properties required by a large field of applications/designs can be summarized as: isotropic dielectric constants, good thermal stability, low Young’s modulus, and good adhesion to different substrates. This paper reports on wafer-to-wafer adhesive bonding using SINR^TM polymer materials. Substrate coating process as well as wafer bonding process parameters optimization was studied. Statistical analysis methods were used to show repeatability and reliability of coating processes. Features of as low as 15 μm size were successfully resolved by photolithography and bonded. An unique megasonic-enhanced development process of the patterned film using low cost solvent was established and proven to exceed standard development method performance.     

A study on effect of wafer bow in wafer-level BCB cap transfer packaging

This paper investigates the effects of wafer bow of Si carrier wafer to achieve high-yield BCB cap transfer in wafer-scale packaging. BCB caps are built-up on Si carrier wafer and then they are bonded and transferred to a target wafer. The height of BCB cap is 25 μm and the thickness of Si carrier wafer is 380 μm. Through several experiments, it is found that BCB cap transfer rate is mainly dependent on wafer bow of Si carrier wafer rather than that of the target wafer due to relatively large thickness of BCB caps. Therefore, Si carrier wafer bow with the BCB layers is investigated as a function of temperature. It is to figure out the effect of the wafer bow at certain temperature and applying pressure on BCB cap transfer rate. Through the study, it is found that zero wafer bow is very important for the cap transfer. Hence, aluminum metal layer is introduced to compensate the existing wafer bow of the Si carrier wafer.     

MEMS packaging process by film transfer using an anti-adhesive layer

A low cost and low temperature thin film packaging process based on the transfer of an electroplated Nickel 3D cap is proposed. This process is based on adhesion control of a thick molded cap Ni film on the carrier wafer by using a plasma deposited fluorocarbon film, on mechanical debonding and on adhesive bonding of the microcaps on the host wafer with BCB sealing rings. Mechanical characterizations show that the transferred microcaps have a high stiffness, a low stress and a high adhesion. Because this process is simple and only involves a low temperature (250°C) heating of the host wafer, it is highly versatile and suitable for the encapsulation of micro and nano devices, circuits and systems elaborated on a large range of substrate materials.     

Super‐high‐resolution transfer printing for full‐color OLED display patterning

Abstract— A transfer‐printing method for the patterning of thin polymer layers is described. A hard stamp with a raised feature is brought into contact with a spin‐coated organic film under elevated pressure and temperature to break the films. The patterned film is then transfer printed onto the devices. This method is used to print red/green/blue subpixel arrays with a pattern size as small as 12 μm at a resolution of 530 ppi to demonstrate its ability for full‐color organic light‐emitting‐display fabrication. Devices with printed organic layers have similar performance to spin‐coated controls under optimized printing temperature and pressure settings. The critical physical parameters include a soft intermediate plate for the sharp breaking of edge patterns, control of surface energies, and printing at moderate temperature and pressure to achieve intimate contact between the printed layer and the underlying substrate.     

Localized silicon fusion and eutectic bonding for MEMS fabricationand packaging

Silicon fusion and eutectic bonding processes based on the technique of localized heating have been successfully demonstrated. Phosphorus-doped polysilicon and gold films are applied separately in the silicon-to-glass fusion bonding and silicon-to-gold eutectic bonding experiments. These films are patterned as line-shape resistive heaters with widths of 5 or 7 μm for the purpose of heating and bonding. In the experiments, silicon-to-glass fusion bonding and silicon to gold eutectic bonding are successfully achieved at temperatures above 1000°C and 800°C, respectively, by applying 1-MPa contact pressure. Both bonding processes can achieve bonding strength comparable to the fracture toughness of bulk silicon in less than 5 min. Without using global heating furnaces, localized bonding process is conducted in the common environment of room temperature and atmospheric pressure. Although these processes are accomplished within a confined bonding region and under high temperature, the substrate temperature remains low. This new class of bonding scheme has potential applications for microelectromechanical systems fabrication and packaging that require low-temperature processing at the wafer level, excellent bonding strength, and hermetic sealing characteristics     

Influences of interface oxidation on transmission laser bonding of wafers for microsystem packaging

In the fabrication of micro-devices and systems, wafer bonding offers a unique opportunity for constructing complicated three-dimensional structures. In this paper, a wafer bonding technique, called transmission laser bonding (TLB), is studied with focus on the effects of interface oxidation and contact pressure on the bonding strength. The TLB is implemented for bonding Pyrex glass-to-silicon wafers, with and without interface oxide layers, using a Q-switch pulsed Nd:YAG laser. The tensile strengths of the TLB bonded specimens are comparable to those generated by the existing major wafer bonding techniques. The advantages of TLB are also discussed with some details. The oxide thickness is measured by spectro-reflectometry while the roughness of the oxidized surfaces is quantified using Atomic Force Microscopy (AFM). The bonded interfaces are analyzed by X-ray Photoelectron Spectroscopy (XPS) and Auger Electron Spectroscopy (AES) to study the migration and diffusion of different atoms across the bonding interface and to provide the necessary information for the understanding of the bonding mechanism. A thermal penetration analysis is also provided to validate the findings of the bond strength and spectroscopic evaluations.     

Characterization of low-temperature wafer bonding using thin-film parylene

This paper presents detailed experimental data on wafer bonding using a thin Parylene layer, and reports results on: 1) bond strength and its dependence on bonding temperature, bonding force, ambient pressure (vacuum), and time, 2) bond strength variation and stability up to two years post bond, and 3) bond strength variation after exposure to process chemicals. Wafer bonding using thin (<381 nm) Parylene intermediate layers on each wafer in a standard commercial bonder and aligner has been successfully developed. The Parylene bond strength is optimized at 230/spl deg/C, although Parylene bonding is possible at as low as 130/spl deg/C. The optimized bonding conditions are a low-temperature of /spl sim/230/spl deg/C, a vacuum of /spl sim/ 0.153 mbar, and 800 N force on a 100 mm wafer. The resultant Parylene bond strength is 3.60 MPa, and the strength for wafers bonded at or above 210/spl deg/C is maintained within 93% of its original value after two years. The bond strength is also measured after exposure to several process chemicals. The bond strength was reduced most in undiluted AZ400K (base) by 69% after one week, then in BHF (acid), MF319 (base), Acetone (solvent), and IPA (solvent) by 56%, 33%, 20%, and 8%, respectively, although less than one hour exposure to these chemicals did not cause a significant bond strength change (less than 11%). [1487].     

Stamp-and-stick room-temperature bonding technique for microdevices

Multilayer MEMS and microfluidic designs using diverse materials demand separate fabrication of device components followed by assembly to make the final device. Structural and moving components, labile bio-molecules, fluids and temperature-sensitive materials place special restrictions on the bonding processes that can be used for assembly of MEMS devices. We describe a room temperature "stamp and stick (SAS)" transfer bonding technique for silicon, glass and nitride surfaces using a UV curable adhesive. Alternatively, poly(dimethylsiloxane) (PDMS) can also be used as the adhesive; this is particularly useful for bonding PDMS devices. A thin layer of adhesive is first spun on a flat wafer. This adhesive layer is then selectively transferred to the device chip from the wafer using a stamping process. The device chip can then be aligned and bonded to other chips/wafers. This bonding process is conformal and works even on surfaces with uneven topography. This aspect is especially relevant to microfluidics, where good sealing can be difficult to obtain with channels on uneven surfaces. Burst pressure tests suggest that wafer bonds using the UV curable adhesive could withstand pressures of 700 kPa (7 atmospheres); those with PDMS could withstand 200 to 700 kPa (2-7 atmospheres) depending on the geometry and configuration of the device.     

Sacrificial wafer bonding for planarization after very deep etching

A new technique is presented that provides planarization after a very deep etching step in silicon. This offers the possibility for resist spinning and layer patterning as well as realization of bridges or cantilevers across deep holes or grooves. The sacrificial wafer bonding technique contains a wafer bond step followed by an etch back. Results of polymer bonding followed by dry etching and anodic bonding combined with KOH etching are discussed. The polymer bonding has been applied in a strain based membrane pressure sensor to pattern the strain gauges and to provide electrical connections across a deep corrugation in a thin silicon nitride membrane by metal bridges     

Bond-quality characterization of silicon-glass anodic bonding

A simple testing method is presented that allows the comparison of the bond quality for anodically bonded wafers. An array of parallel metal lines of predetermined thickness is formed on a glass wafer. The estimation of the bond quality can be performed by visual inspection after the bonding. This method enables comparison of the anodic-bonding process performance for different glasses, for intermediate layers and various bonding conditions. The optimization of silicon-glass anodic bonding with an intermediate phosphosilicate glass (PSG) layer is shown using this technique.     

Laser transmission bonding of silicon to silicon with metallic interlayers for wafer-level packaging

For packaging of silicon components with low thermal load and high spatial selectivity laser transmission bonding (LTB) of silicon–silicon compounds with intermediate layers using a cw-thulium fiber laser (wavelength 1,940 nm) is investigated. The intermediate layer combination titanium and gold is examined with respect to the bond characteristics and the achievable mechanical properties of the bonded specimens. The tensile strength is measured by using tensile test. Similar specimens bonded with corresponding standard bond process using the same bond geometry are also analyzed in order to compare the measurements.     

Fabrication method of spacers with high aspect ratio – Used in a field emission display (FED)

Glass to glass anodic bonding using a metal interlayer was used to develop a fabrication method of spacer for field emission display (FED). In this paper, spacers with width 100 μm and height 1000 μm and a 3.54 inch mono color anode plate patterned with Al/Cr film as an interlayer were bonded by the anodic bonding. To bond the spacers on the anode plate vertically, two types of spacer holders were designed and fabricated with photoetchable glass and n(110) Si wafer. The spacer holder using Si wafer was used to fabricate for evacuated FED panel. Received: 22 November 1999/Accepted: 27 January 2000     

Room temperature bonding for vacuum applications: climatic and long time tests

A detailed and quantitative motivation for the necessity of room temperature (RT) bonding for wafer level packaging of silicon micro-mirrors will be given. Results on RT 6 inch wafer bonding with vacuum encapsulation on test structures are presented. Structured as well as unstructured wafers have been bonded at RT using a Mitsubishi Heavy Industries bonder. Unstructured wafers were used for the determination of the bonding strength, whereas the structured wafers were used for the evaluation of vacuum level and its stability with time.     

A dielectrophoretic chip packaged at wafer level

The paper presents a dielectrophoretic chip, fully enclosed, with bulk silicon electrodes fabricated using wafer-to-wafer bonding techniques and packaged at the wafer level. The silicon electrodes, which are bonded to two glass dies, define in the same time the walls of the microfluidic channel. The device is fabricated from a silicon wafer that is bonded (at wafer level) anodically and using SU8 photoresist between two glass wafers. The first glass die includes drilled holes for inlet/outlet connections while the second glass die assure the electrical connections, through via holes and a metallization layer, between the silicon electrodes and a printing circuit board.     

Aluminum–germanium wafer bonding of (AlGaIn)N thin-film light-emitting diodes

Eutectic aluminum–germanium wafer bonding was used to fabricate (AlGaIn)N thin-film light-emitting diodes (LEDs). Wafer bonding was carried out on 2″ wafer level at a bond temperature of 470 °C using patterned Al bond pads on the GaN-on-sapphire LED epiwafer and plain Ge substrates. The microstructure of the joint formation was characterized via cross-section analysis using scanning electron microscopy and energy dispersive X-ray spectroscopy (EDX). Scanning acoustic microscopy was used to investigate the bond interface. The shear strength was determined to be 1–2 kN/cm². The formation of a liquid Al–Ge phase is evident from cross-section analysis and optical microscopy. During solidification, Al and Ge are separated into distinct phases again, which is revealed by EDX. The obtained bond is not free of micro-voids, yet it is mechanically stable and suited for the fabrication of thin-film LEDs by removing the sapphire substrate via laser lift-off, which is also demonstrated.     

Enhancement of bonding strength of packaging based on BCB bonding for RF devices

This paper presents a Si cap zero-level packaging technique based on a double-layer BCB sealing ring. The BCB ring is defined before the housing cavity etching to achieve high BCB bonding strength. It is found that the non-uniformity of the BCB ring defined on a Si cap with housing cavity prevents the package having high bonding strength. Three different packages have been prepared for shear test; a Si cap without cavity, a recessed Si cap with a conventional BCB ring and a recessed Si cap with pre-defined BCB ring. The three samples for each type of package are measured. The average measured bonding strengths of the test samples are 71, 16 and 42?MPa, respectively, and hence the proposed BCB sealing ring process provides 60?% of bonding strength of Si cap package without cavity for Si cap package with cavity. In addition, the insertion loss change of the packaged CPW is less than 0.1?dB up to 67?GHz while the return loss better than 15?dB at the measured frequency range.