Analysis of Self-Heating Effects in Ultrathin-Body SOI MOSFETs by Device Simulation

This paper discusses self-heating (SHE) effects in silicon-on-insulator (SOI) CMOS technology and applies device simulation to analyze the impact of thermal effects on the operation of nanoscale SOI n-MOSFETs. A 2-D drift-diffusion electrothermal simulation, using an electron transport model calibrated against Monte Carlo simulations at various temperatures, is employed in the analysis. We report the effects of device-structure parameters, such as SOI layer thickness, buried-oxide (BOX) thickness, source/drain (S/D) extension length, and thickness of the elevated S/D region, on the SHE of nanoscale MOSFETs. The SHE effects become significant due to the adoption of thin silicon layers and to the low thermal conductivity of the BOX, leading to the rise of large temperature under nominal operation conditions for high-performance digital circuits. The ac performance of SOI MOSFETs is influenced as well, and in particular, a severe degradation of the cutoff frequency of very short MOSFETs is predicted by numerical electrothermal device simulations. Although the effects of SHE on device performance are found to be somewhat modest and might be mitigated through device design, they may result in a degradation of the long-term reliability.     

Fault detection in CMOS/SOI mixed-signal circuits using the quiescent current test

Main stream bulk CMOS and the variants of silicon-on-insulator (SOI) CMOS technologies are discussed with respect to testing for the quiescent current of mixed-signal integrated SOI circuits. The 2–3 times lower static power consumption in fully depleted CMOS/SOI compared to bulk CMOS allows quiescent current testing also for high performance analogue circuits at an acceptable defect resolutions. From first simulations and technological considerations, it turned out that quiescent current tests are able to detect not only commonly known defects, but also SOI specific defects such as self-heating, kink-effect or the parasitic bipolar behaviour. It is further shown that in partially depleted thick-film SOI, the kink-effect and parasitic bipolar transistor support the quiescent current test for some specific defects as they elevate the defective quiescent current level. In fully depleted kink-free SOI circuits, the kink-effect may occur due to process failures but then can be detected by quiescent current tests. A special fault simulation model for the kink-effect is presented. The I_ccq test technique is studied for a CMOS/SOI Miller operational amplifier. Normal 6-σ variation of the aspect ratio and the threshold voltage do not jeopardise the defect detection in the quiescent current. First, results confirm the good detection capabilities of the quiescent current test, in particular, of failures which are not visible in the output voltage.     

Fully coupled electrothermal mixed-mode device simulation of SiGeHBT circuits

It is well known that for the design and simulation of state-of-the-art circuits thermal effects like self-heating and coupling between individual devices must be taken into account. As compact models for modern or experimental devices are not readily available, a mixed-mode device simulator capable of thermal simulation is a valuable source of information, Considering self-heating and coupling effects results in a very complex equation system which can only be solved using sophisticated techniques. We present a fully coupled electrothermal mixed-mode simulation of an SiGe HBT circuit using the design of the μA709 operational amplifier. By investigating the influence of self-heating effects on the device behavior we demonstrate that the consideration of a simple power dissipation model instead of the lattice heat flow equation is a very good approximation of the more computation time consuming solution of the lattice heat flow equation     

An effective thermal circuit model for electro-thermal simulation of SOI analog circuits

A physics-based thermal circuit model is developed for electro-thermal simulation of SOI analog circuits. The circuit model integrates a non-isothermal device thermal circuit with interconnect thermal networks and is validated with high accuracy against finite element simulations in different layout structures. The non-isothermal circuit model is implemented in BSIMSOI to account for self-heating effect (SHE) in a Spice simulator, and applied to electro-thermal simulation of an SOI cascode current mirror constructed using different layouts. Effects of layout design on electric and thermal behaviors are investigated in detail. Influences of BOX thickness are also examined. It has been shown that the proposed non-isothermal approach is able to effectively account for influences of layout design, self-heating, high temperature gradients along the islands, interconnect temperature distributions, thermal coupling, and heat losses via BOX and interconnects, etc., in SOI current mirror structures. The model provides basic concepts and thermal circuits that can be extended to develop an effective model for electro-thermal simulation of SOI analog ICs.     

Thermal Modeling and Device Noise Properties of Three-Dimensional–SOI Technology

Thermal test structures and ring oscillators (ROs) are fabricated in 0.18-$ muhbox{m}$ three-dimensional (3-D)–SOI technology. Measurements and electrothermal simulations show that thermal and parasitic effects due to 3-D packaging have a significant impact on circuit performance. A physical thermal model is parameterized to provide better prediction of circuit performance in 3-D technologies. Electrothermal simulations using the thermal model show good agreement with measurement data; the model is applicable for different circuits designed in the 3-D–SOI technology. By studying the phase noise of ROs, the device noise properties of 3-D–SOI technology are also characterized and compared with conventional bulk CMOS technology.      

Thermal and package performance limitations in LDMOSFET's for RFICapplications

This paper presents a systematic study of the limitations imposed by thermal and packaging considerations on radio-frequency (RF) performance of Si bulk and silicon-on-insulator (SOI) lateral DMOSFET's (LDMOSFET's). Several bulk and SOI devices are studied with the help of measurements as well as two-dimensional device simulations incorporating electrothermal models. Model parameters are extracted and used in circuit simulators to perform RF characterization of these devices. Further, a new three-region theory for the LDMOSFET is discussed and used to evaluate the static and RF performance of the devices in a nonisothermal environment. This paper shows that the package plays an important role in RF performance of SOI and bulk devices due to self-heating effects within the device. A detailed DC and RF performance evaluation is presented. Significant drift is observed in RF performance of bulk and SOI devices due to self-heating considerations. The physical understanding of these thermal effects within the device can facilitate the design of better packages for bulk and SOI devices     

A 0.5-V power-supply scheme for low-power system LSIs using multi-V/sub th/ SOI CMOS technology

This paper proposes a novel power-supply scheme suitable for 0.5-V operating silicon-on-insulator (SOI) CMOS circuits. The system contains an on-chip buck DC-DC converter with over 90% efficiency, 0.5-V operating logic circuits, 100-MHz operating flip-flops at 0.5-V power supply, and level converters for the interface between the 0.5-V operating circuit and on-chip digital-to-analog (D/A) converters or external equipment. Based on the theory, the values of on-resistance and threshold voltage of SOI transistors are clarified for the 0.5-V/10-mW output DC-DC converter, which satisfies both high efficiency and low standby power. The proposed flip-flop can hold the data during the sleep with the use of the external power supply, while maintaining high performance during the active. The level converter comprises dual-rail charge transfer gates and a CMOS buffer with a cross-coupled nMOS amplifier to operate with high speed even in a conversion gain of higher than 6, where the conversion gain is defined as the ratio of the output and input signal swings. The test chip was fabricated for the 0.5-V power supply scheme by using multi-V/sub th/ SOI CMOS technology. The experimental results showed that the buck DC-DC converter achieved a conversion efficiency of 91% at 0.5-V/10-mW output with stable recovery characteristics from the sleep, and that the dual-rail level converter operated with a maximum data rate of 300 Mb/s with the input signal swing of 0.5 V.     

Design of integrated analog CMOS circuits-a multichannel telemetry transmitter [single-stage differential amplifier]

A single-stage differential amplifier, implemented in a standard metal-gate process, serves as a basis for consideration of specific characteristics of analog CMOS circuits. The dependence of important circuit parameters like open-loop gain and gain-bandwidth product on transistor geometries, and biasing current are derived. Furthermore, it is shown how to improve the amplifier characteristics by optimizing the layout. The differential amplifier stage is compared with an equivalent one based on a standard bipolar process. This comparison shows that the CMOS stage exceeds in the low-current region (nanoamperes) not only the possible voltage gain but also the gain-bandwidth product of a bipolar stage. The results are applied to the design of a multichannel telemetry transmitter for patient monitoring. The transmitter chip incorporates a digital part for the multiplex control and a precise analog part for the modulation unit. The modulator is a voltage controlled oscillator and consists of two parts: a voltage-to-current converter and a current controlled oscillator. The linear range of the voltage-to-current converter is limited to at most three decades due to the offset of MOS transistors. The current controlled oscillator, however, has a linear range of more than seven decades. This was made possible by applying a new design principle, which is specific for CMOS technology. Besides the large linear range the multivibrator has excellent temperature stability. The chip area is 4 mm/SUP 2/.     

Physical modeling of temperature dependences of SOI CMOS devicesand circuits including self-heating

To simulate and examine temperature and self-heating effects in Silicon-On-Insulator (SOI) devices and circuits, a physical temperature-dependence model is implemented into the SOISPICE fully depleted (FD) and nonfully depleted (NFD) SOI MOSFET models. Due to the physical nature of the device models, the temperature-dependence modeling, which enables a device self-heating option as well, is straightforward and requires no new parameters. The modeling is verified by DC and transient measurements of scaled test devices, and in the process physical insight on floating-body effects in temperature is attained. The utility of the modeling is exemplified with a study of the temperature and self-heating effects in an SOI CMOS NAND ring oscillator. SOISPICE transient simulations of the circuit, with floating and tied bodies, reveal how speed and power depend on ambient temperature, and they predict no significant dynamic self-heating, irrespective of the ambient temperature     

Transient drain current and propagation delay in SOI CMOS

The transient overshoot in drain current that occurs in thin-film SOI (Si-on-SiO2) MOSFET's because of the floating body in analyzed, and the benefit it can provide to propagation delay (speed) in SOI CMOS digital circuits is assessed. The analysis accounts for the charge coupling between the front and back gates, and hence describes the dependence of the transient drain (saturation) current and propagation delay on the back-gate bias as well as on the switching frequency. Measurements of the transient current in recrystallized SOI MOSFET's and of propagation delay in SOI CMOS inverters and ring oscillators are described and shown to support the theoretical analysis. The current overshoot is especially beneficial in low-voltage circuits, although at high frequencies other floating-body effects can degrade the speed.     

Scaling constraints imposed by self-heating in submicron SOIMOSFET's

The presence of a buried oxide layer in silicon causes enhanced self-heating in Silicon-On-Insulator (SOI) n-channel MOSFETs. The self-heating becomes more pronounced as device dimensions are reduced into the submicron regime because of increased electric field density and reduced silicon volume available for heat removal. Two-dimensional numerical simulations are used to show that self-heating manifests itself in the form of degraded drive current due to mobility reduction and premature breakdown. The heat flow equation was consistently solved with the classical semiconductor equations to study the effect of power dissipation on carrier transport. The simulated temperature increases in the channel region are shown to be in close agreement with recently measured data. Numerical simulation results also demonstrated accelerated turn-on of the parasitic bipolar transistor due to self-heating. Simulation results were used to identify scaling constraints caused by the parasitic bipolar transistor turn-on effect in SOI CMOS ULSI. For a quarter-micron n-channel SOI MOSFET, results suggest a maximum power supply of 1.8 V. In the deep submicron regime, SOI devices exhibited a negative differential resistance due to increased self-heating with drain bias voltage. Detailed comparison with bulk devices suggested significant reduction in the drain-source avalanche breakdown voltage due to increased carrier injection at the source-body junction     

N+多晶硅栅薄膜全耗尽SOI CMOS器件与电路的研究

选用SIMOX(Separation by Implantation of Oxygen)衬底材料,对全耗尽SOI CMOS工艺进行了研究,开发出了N 多晶硅栅全耗尽SOI CMOS器件及电路工艺,获得了性能良好的器件和电路。nMOS和pMOS的驱动电流都比较大,且泄漏电流很小,在工作电压为3V时,1．2μm101级环振的单级延迟仅为50．5ps。     

A CMOS uncooled heat-balancing infrared imager

In this paper, we report the fabrication, design, and testing of an uncooled 8×8 infrared imager based on an active pixel heat balancing technique. The imager is fabricated using a commercial CMOS process plus a simple electrochemical etch stop releasing step. The basic active pixel detector structure consists of a simple cascode CMOS amplifier in which the PMOS devices are built inside a thermally isolated floating n-well. The intrinsic coupling of the cascode currents with the self-heating of the well forms an electrothermal feedback loop that tends to maintain the well temperature constant, By employing the heat balance between incoming infrared radiation and the PMOS device power dissipation, the responsivity of the detector is controlled by the cascode biasing current. Measurements show responsivities between 0.3-1.2×10⁶ V/W when the infrared source is chopped at 20 Hz and a detectivity D*=3×10⁷ cm√(Hz)W^-1 at 30 Hz. Noise measurements suggest that a D* of 10⁸ cm√(Hz)W^-1 is achievable in this design     

Characterization of layout dependent thermal coupling in SOI CMOScurrent mirrors

A current mirror is proposed as a suitable structure for the characterization of layout dependent thermal coupling between MOSFETs. Using current and voltage measurements, and compensating for series resistance effects, very small changes in local device temperature can be made visible. For the first time it is demonstrated that thermal coupling can be observed in a 2 μm SOI CMOS technology, with devices separated by as much as 20 μm. Measurements were verified by electro-thermal SPICE simulations, using a simple lumped model to express thermal coupling. The observations reinforce the need for accurate circuit level models, including self heating and thermal coupling effects, for analogue applications in VLSI SOI CMOS technologies     

A physical charge-based model for non-fully depleted SOI MOSFET'sand its use in assessing floating-body effects in SOI CMOS circuits

A new model for the non-fully depleted (NFD) SOI MOSFET is developed and used to study floating-body effects in SOI CMOS circuits. The charge-based model is physical, yet compact and thus suitable for device/circuit simulation. Verified by numerical device simulations and test-device measurements, and implemented in (SOI)SPICE, it reliably predicts floating-body effects resulting from free-carrier charging in the NFD/SOI MOSFET, including the purportedly beneficial supra-ideal sub-threshold slope due to impact ionization and a saturation current enhancement due to thermal generation. SOISPICE CMOS circuit simulations reveal that the former effect is not beneficial and could be detrimental, but the latter effect can be beneficial, especially in low-voltage applications, when accompanied by a dynamic floating-body effect that effectively reduces static power. The dynamic floating-body effects are hysteretic, however, and hence exploitation of the beneficial ones will necessitate device/circuit design scrutiny aided by physical models such as the one presented herein     

铁氧体驱动与双路功率MOS单片集成电路研究

介绍了一种集成低压铁氧体驱动器和功率MOS管的单片集成电路。其内建驱动器工作电压9 V,功率MOS管极限电压大于80 V,工作电流3 A。该电路内含D/A转换器、双路比较器、触发器和组合逻辑电路,以及过频过压保护等功能,采用键合SOI深槽的CMOS/LDMOS工艺制作。     

Theory of electrothermal behavior of bipolar transistors: Part I -single-finger devices

A detailed theoretical and numerical analysis of the electrothermal behavior of single-finger bipolar transistors is proposed. Two models of different complexities are introduced to investigate self-heating effects in bipolar junction transistors (BJTs) and heterojunction bipolar transistors (HBTs) biased with a constant base-emitter voltage source or with a constant base current source. In the constant base-emitter voltage case, simple relations are derived for determining the onset of the flyback behavior in the output characteristics which defines the boundary of the safe operating region. The model indicates that the flyback behavior disappears at high V/sub BE/ values, and predicts a thermal hysteresis phenomenon at high currents. It is also shown that at high current levels the electrothermal behavior is dominated by ohmic base pushout. If a constant base current is applied, the model shows that both BJTs and HBTs are unconditionally thermally stable. The transient behavior is also considered, and the temperature evolution is investigated for different bias conditions. The model shows that, if the device is biased in the thermally unstable region, thermal breakdown occurs within a finite time instant in the limit case of a zero ballast resistance. Finally, the reduction in the safe operating area due to avalanche effects and to the temperature dependence of thermal conductivity is discussed, and a simplified model is proposed.     

LDO中过温保护电路的设计

LDO是一个微型的片上系统,他包括调整管、采样网络、精密基准源、差分放大器、过流保护、过温保护等电路。分析了LDO中过温保护电路的设计,主要介绍了LDO中双极型过温保护电路和CMOS过温保护电路。由于双极器件开发早、工艺相对成熟、稳定,而且用双极工艺可以制造出速度高、驱动能力强、模拟精度高的器件,适用于高精度的模拟集成电路。因此,双极型集成稳压器应用广泛,其设计技术和制造工艺比较成熟和完善。但双极型过温保护电路本身存在热振荡的问题。给出一种新型的CMOS过温保护电路,他具有温度迟滞功能,有效地避免了芯片出现热振荡。     

A 10 b 50 MHz pipelined CMOS A/D converter with S/H

A single 5 V, 10 b, 50 MHz pipelined CMOS analog-to-digital (A/D) converter with internal sample-and-hold (S/H) circuits was developed. The A/D converter features a newly developed S/H circuit with an 80 dB, 300 MHz operational amplifier, three-stage pipelined 4 b flash A/D converters with digital error correction functions, and double analog signal conversion paths whose operations are interleaved. The new A/D converter was fabricated with 0.8 μm CMOS technology