How to Select the System Voltage of MV Drives—A Comparison of Semiconductor Expenses

The application of a particular medium-voltage converter in a certain application depends on numerous criteria. However, in completely new installations, the choice of the system voltage is very often uninhibited of external constraints. Then, the voltage level shall be selected to enable the most efficient power conversion at the lowest cost. This paper is dedicated to help in finding the best voltage level for three-level neutral-point-clamped voltage source converters (3L-NPC VSCs) with respect to the power semiconductor devices. Three insulated-gate-bipolar-transistor-based 3L-NPC VSCs of different voltage levels (2.3, 3.3, and 4.16 kV) are investigated and compared regarding their maximum output power, semiconductor efficiency, and semiconductor cost per MVA output power. The effects of thermal cycling, the loss distribution within the converter, and switching frequencies from 300 to 1050 Hz are considered in the evaluation.      

Current Sensing for Automotive Electronics—A Survey

Current sensing is widely used in power electronic applications such as dc-dc power converters and adjustable-speed motor drives. Such power converters are the basic building blocks of drivetrains in electric, hybrid, and plug-in hybrid electric vehicles. The performance and control of such vehicles depend on the accuracy, bandwidth, and efficiency of its sensors. Various current-sensing techniques based on different physical effects such as Faraday's induction law, Ohm's law, Lorentz force law, the magnetoresistance effect, and the magnetic saturation effect are described in this paper. Each technique is reviewed and examined. The current measurement methods are compared and analyzed based on their losslessness, simplicity, and ease of implementation.     

A Review of FPGA-Based Custom Computing Architecture for Convolutional Neural Network Inference

Convolutional neural network (CNN) has been widely adopted in many tasks. Its inference process is usually applied on edge devices where the computing resources and power consumption are limited. At present, the performance of general processors cannot meet the requirement for CNN models with high computation complexity and large number of pa-rameters. Field-programmable gate array (FPGA)-based custom computing architecture is a promising solution to further enhance the CNN inference performance. The software/hardware co-design can effectively reduce the computing overhead, and improve the inference performance while ensuring accuracy. In this paper, the mainstream methods of CNN structure design, hardware-oriented model compression and FPGA-based custom architecture design are summarized, and the improvement of CNN inference performance is demonstrated through an example. Challenges and possible research directions in the future are concluded to foster research efforts in this domain.     

On Some Nonlinear Current Controllers for Three-Phase Boost Rectifiers

Several flatness-based current controllers for three-phase three-wire boost rectifiers are compared. For this purpose, the flatness of a rectifier model is shown, and a trajectory planning algorithm that nominally achieves voltage regulation in finite time is given. The main focus lies on the inner loop current controllers. On one hand, linearization-based controllers using exact feedback linearization, exact feedforward linearization, and input–output linearization are discussed. On the other hand, two passivity-based approaches are compared. The first one is the energy shaping and damping injection method, and the other one uses exact tracking error dynamics passive output feedback. Furthermore, a reduced-order load observer is given, and a method that allows the prevention of invalid switching patterns is presented. The presented control algorithms are tested by simulations on a switched model.      

Evaluation of Current Controllers for Distributed Power Generation Systems

This paper discusses the evaluation of different current controllers employed for grid-connected distributed power generation systems having variable input power, such as wind turbines and photovoltaic systems. The focus is mainly set on linear controllers such as proportional-integral, proportional-resonant, and deadbeat (DB) controllers. Additionally, an improved DB controller robust against grid impedance variation is also presented. Since the paper discusses the implementation of these controllers for grid-connected applications, their evaluation is made in three operating conditions. First, in steady-state conditions, the contribution of controllers to the total harmonic distortion of the grid current is pursued. Further on, the behavior of controllers in the case of transient conditions like input power variations and grid voltage faults is also examined. Experimental results in each case are presented in order to evaluate the performance of the controllers.     

基于FPGA的液晶控制器设计

介绍了一种基于 FPGA 的集成液晶控制器.系统由显示模块和控制模块组成,显示模块(LEM101)为10 bit 多功能通用型器件,内含看门狗(WDT)/时钟发生器,2 种频率的蜂鸣驱动电路,内置显示RAM,及3-4线串行接口.控制器基于1.5万门 FPGA 芯片(Xilinx XC3S1500),易于扩展和升级.利用 Verilog 语言,在 FPGA 芯片中实现了控制模块的设计,通过 GR-XC3S-1500 开发板验证,本设计完全满足对液晶模块的控制要求,并成功应用于光栅测量显示控制系统中.控制模块由四部分组成:存储、译码、串并转换器、输出控制.文章讨论了设计方法和设计过程,给出了部分 Verilog 代码.此外,本设计还创造性地在电源和 FPGA 芯片间插入低成本元件,满足了液晶上电后,初始化命令的延迟要求,从而节约了 FPGA 的硬件资源.     

Polyanion Sodium Vanadium Phosphate for Next Generation of Sodium‐Ion Batteries—A Review

Polyanion‐type sodium (Na) vanadium phosphate in the form of Na₃V₂(PO₄)₃ has demonstrated reasonably high capacity, good rate capability, and excellent cyclability. Two of three Na ions per formula can be deintercalated at a potential 3.4 V versus Na⁺/Na with oxidation of V^3+/4+. In the reversible process, two Na ions intercalate back resulting in a discharge capacity of 117.6 mAh g^?1. Further intercalation is possible but at a low potential of 1.4 V versus Na⁺/Na accompanied by vanadium reduction V^3+/2+, leading to a capacity of 60 mAh g^?1. Due to its marvelous electrochemical performance, it has attracted a lot of attention since its discovery in the 1990s. To develop truly useable polyanion‐type vanadium phosphate, better understanding of its crystal configuration, sodium ions' transportation, and electronic structure is essential. Therefore, this review only focuses on the inside of crystal configuration and electronic structure of polyanion‐type vanadium phosphate, Na₃V₂(PO₄)₃, since there are a few good reviews on various processing technologies.     

A Multiwindow Partial Buffering Scheme for FPGA-Based 2-D Convolvers

Two-dimensional (2-D) convolution is widely used in image and video processing. Although the operation is simple, 2-D convolution is however both computationally expensive and memory-intensive. Field-programmable-gate-array (FPGA)-based parallel processing architectures were proposed to accelerate calculations for 2-D convolution. And data buffers implemented with FPGA on-chip resources were used to avoid direct access to external memories. Full buffering and partial buffering (PB) schemes were adopted in previous works. The former would consume a large amount of FPGA resources, while the latter would cause a sharp increase in external memory bus bandwidth. In this brief, we present a multiwindow PB scheme for FPGA-based 2-D convolvers. Compared with the aforementioned methods, the new buffering strategy exhibits a good balance between on-chip resource utilization and external memory bus bandwidth, and therefore is suitable for low-cost FPGA implementation     

Photovoltaic Degradation Rates—an Analytical Review

As photovoltaic penetration of the power grid increases, accurate predictions of return on investment require accurate prediction of decreased power output over time. Degradation rates must be known in order to predict power delivery. This article reviews degradation rates of flat‐plate terrestrial modules and systems reported in published literature from field testing throughout the last 40 years. Nearly 2000 degradation rates, measured on individual modules or entire systems, have been assembled from the literature, showing a median value of 0·5%/year. The review consists of three parts: a brief historical outline, an analytical summary of degradation rates, and a detailed bibliography partitioned by technology. Copyright © 2011 John Wiley & Sons, Ltd.     

A Unified FPGA-Based System Architecture for 2-D Discrete Wavelet Transform

This paper presents a novel unified and programmable 2-D Discrete Wavelet Transform (DWT) system architecture, which was implemented using a Field Programmable Gate Array (FPGA)-based Nios II soft-core processor working in combination with custom hardware accelerators generated through high-level synthesis. The proposed system architecture, synthesized on an Altera DE3 Stratix III FPGA board, was developed through an iterative design space exploration methodology using Altera’s C2H compiler. Experimental results show that the proposed system architecture is capable of real-time video processing performance for grayscale image resolutions of up to 1920?×?1080 (1080p) when ran on the Altera DE3 board, and it outperforms the existing 2-D DWT architecture implementations known in literature by a considerable margin in terms of throughput. While the proposed 2-D DWT system architecture satisfies real-time performance constraints, it can also perform both forward and inverse DWT, support a number of popular DWT filters used for image and video compression and provide architecture programmability in terms of number of levels of decomposition as well as image width and height. Based from the design principles used to implement the proposed 2-D DWT system architecture, a system design guideline can be formulated for SOC designs which plan to incorporate dedicated 2-D DWT hardware acceleration.     

A Miniaturized Ground Edge Current Choke—Design, Measurement, and Applications

We propose a miniaturized microwave current choke for blocking the current flowing along the edge of a substrate's ground plane. The proposed current choke is composed of a printed inductor and a printed capacitor, which possesses a size much smaller than a conventional quarter-wavelength current choke. By introducing the choke at one side of the ground plane, an effective electrical open circuit is performed for reflecting the ground edge current. The size of the proposed ground edge current choke (GECC) is as small as around 0.06 wavelength in free space. Two applications of the GECC are presented in this paper. The first is the radiation pattern regulation of a printed monopole antenna with long ground plane. The GECC in this application reflects the induced traveling-wave current along the ground plane edge and changes it to a standing-wave one, thus regulating the tilted radiation pattern due to the traveling-wave current to a broadside pattern. The other application is the decoupling of two nearby monopole antennas. By placing the proposed compact GECC in between the antennas, it is found that the isolation between the antenna ports can be enhanced from 8 dB to 32 dB. The experimental results agree well with the simulation, which demonstrate the feasibility of the proposed GECC.      

高速数字直接电流控制器——一类新的满足未来需要的智能控制器

由于电力电子驱动应用要求不断增加,并越来越重要。为满足未来需求,电力电子控制算法也应该在减少纹波电流和增强鲁棒性的同时,能够快速处理非线性和未知负载。逆变控制有两种基本原理-直接电流控制和间接电流控制。迄今为止,间接电流控制器(例如通过PWM或空间矢量调制)与直接电流调制比较,应用更广泛。然而,直接电流控制器的快速性、鲁棒性能够很好的适应于处理未知甚至是非线性的负载,因而,似乎更适应于未来的需要。但是其中的一个明显不足在于它是用模拟技术来实现的。漂移、温度的影响等非常明显。本文提出了一种新的高速全数字直接电流控制器。该控制器在10M Hz下工作。能够满足未来的需要,并能够处理非线性负载,克服模拟直流控制器的不足。     

A Highly Parameterized and Efficient FPGA-Based Skeleton for Pairwise Biological Sequence Alignment

This paper presents the design and implementation of the most parameterisable field-programmable gate array (FPGA)-based skeleton for pairwise biological sequence alignment reported in the literature. The skeleton is parameterised in terms of the sequence symbol type, i.e., DNA, RNA, or Protein sequences, the sequence lengths, the match score, i.e., the score attributed to a symbol match, mismatch or gap, and the matching task, i.e., the algorithm used to match sequences, which includes global alignment, local alignment, and overlapped matching. Instances of the skeleton implement the Smith–Waterman and the Needleman–Wunsch Algorithms. The skeleton has the advantage of being captured in the Handel-C language, which makes it FPGA platform-independent. Hence, the same code could be ported across a variety of FPGA families. It implements the sequence alignment algorithm in hand using a pipeline of basic processing elements, which are tailored to the algorithm parameters. This paper presents a number of optimizations built into the skeleton and applied at compile-time depending on the user-supplied parameters. These result in high performance FPGA implementations tailored to the algorithm in hand. For instance, actual hardware implementations of the Smith–Waterman algorithm for Protein sequence alignment achieve speedups of two orders of magnitude compared to equivalent standard desktop software implementations.      

Frequency Response Analysis of Current Controllers for Selective Harmonic Compensation in Active Power Filters

This paper compares four current control structures for selective harmonic compensation in active power filters. All controllers under scrutiny perform the harmonic compensation by using arrays of resonant controllers, one for the fundamental and one for each harmonic of interest, in order to achieve zero phase shift and unity gain in the closed-loop transfer function for selected harmonics. The complete current controller is the superposition of all individual harmonic controllers and may be implemented in various reference frames. The analysis is focused on the comparison of harmonic and total closed-loop transfer functions for each controller. Analytical similarities and differences between schemes in terms of frequency response characteristics are emphasized. It is concluded that three of them have identical harmonic behavior despite the fact that their implementation is significantly different. It emerges that the fourth one has superior behavior and robustness and can stably work at higher frequencies than the others. Theoretical findings and analysis are supported by comparative experimental results on a 7-kVA laboratory setup. The highest harmonic frequency that can be stably compensated with each control method has been determined, indicating significant differences in the control performance.      

Novel Approach for Alternating Current (AC)‐Driven Organic Light‐Emitting Devices

A novel approach for alternating current (AC)‐driven organic light‐emitting devices is reported, which uses the concept of molecular doping in organic semiconductors. Doped organic charge‐transport layers are used to generate charge carriers within the device, hence eliminating the need for injecting charge carriers from external electrodes. Bright luminance of up to 1000 cd m^?2 is observed when the device is driven with an AC bias. The luminance observed is attributed to charge‐carrier generation and recombination, leading to the formation of excitons within the device, without injection of charge carriers through external electrodes. A mechanism for internal charge‐carrier generation and the device operation is proposed.     

Study of an Hybrid Current Controller Suitable for DC–DC or DC–AC Applications

In this paper, the modeling and study of a new hybrid current controller is presented. It ensures high dynamic response with a fixed-frequency operation mode, a zero static error, and high robustness properties in regard to system parameters variations. To model the proposed nonlinear current controller, different tools are developed. In a first step, a high-frequency average model is proposed. It allows studying the average dynamic properties (bandwidth, time response, and overflow). To investigate the behavior of the current ripple due to the switching effect, a second model, based on the construction of a 3D bifurcation diagram and the definition of a form function, is established. This model allows studying the nature of the cycle described by the state trajectory and proving that the system operates with a fixed switching frequency. Design rules of the control parameters of this controller are explained and its robustness properties are tested by numerical simulations and validated by experimental tests.     

适用于VRM数字控制芯片的新结构ADC

提出了一种适用于主板电压调整模块(VRM)数字控制芯片的新结构ADC--延迟环ADC的设计和实现方法.运用延时环(或称环路压控振荡器)的电压-频率转换原理实现对电压信号的模数转换,提高了线性度,减小了工艺偏差;设计差分脉冲计数式鉴频器,降低了延迟环ADC功耗.在标准0.35μm CMOS工艺环境下流片实现,测试结果表明延迟环ADC的微分线性误差和积分线性误差分别为0.92LSB和1.2LSB,最大增益误差为±3.85%,当VRM工作于稳定状态,延迟环ADC在采样频率为500kHz下工作的平均功耗为2.56mW.延迟环ADC满足VRM数字控制芯片应用要求.     

感应电机自适应电流解耦逆控制

通过对感应电机状态方程的转换,将电机dq轴电流方程解耦,利用自适应逆控制思想,采用LMS(最小均方)算法,实现了对MIMO、多参量、强耦合感应电机的电流控制,电机长期运行会导致某些参数发生漂移,仿真验证了该算法对参数变化的鲁棒性.