20 GHz Wavelet Generator Using a Gated Tunnel Diode

We demonstrate the use of a GaAs-AlGaAs gated tunnel diode (GTD) in an ultra-wideband (UWB) wavelet generator. An inductor is integrated to form an oscillator circuit, which is driven by the negative differential conductance property of a GTD. It is demonstrated that as the gate tunes the magnitude of the output conductance, the oscillator may be switched on and off, creating short RF pulses. The shortest pulses generated are 500 ps long, the highest output power for the free running oscillator is $-$4.1 dBm, and the highest oscillation frequency is 22 GHz. Analytical expressions based on the van der Pol equation describing the pulse length and amplitude are presented. This technique is applicable for high frequency impulse radio UWB implementations.      

New design of 3.2–4.8 GHz generator for multi-bands architecture of UWB communication

In this paper a new design of Ultra-Wide Band (UWB) generator is presented. This circuit is the most important block in multi-bands transmitter architecture of UWB communication system. The proposed UWB generator is composed of multi-bands voltage controlled oscillator (VCO), mixer and rectangular pulse generator which consist of ring oscillator, time delay and AND gate function. The UWB generator is based on multiplying the rectangular pulse envelope to a continuous sinusoidal wave in order to generate the UWB signal. This UWB generator circuit produces an output signal which is characterized by the bandwidth of 1600 MHz divided into three sub-bands of 528 MHz, centered at frequencies of 3.432, 3.96, 4.488 GHz and the limited Power Spectral Density (PSD) is −41.44 dBm/MHz. The maximum amplitude of UWB signal is 214 mV, the pulse is during of 3 ns and the pulse repetition period (PRP) is 32 ns. The power consumption is approximately equal to 26 mW at a voltage supply of 2.5 V. This topology is designed in CMOS 0.35 μm AMS process technology.     

A 3–5 GHz low-power high-speed radiated power tuning UWB transmitter

To satisfy the different radiated power requirements for the ultra-wideband (UWB) data transmitting in the implantable electronic devices or the wireless component interconnections, a novel low-power high-speed UWB transmitter with radiated power tuning was proposed. The tunable radiated power is achieved by a UWB RF buffer with a peak value controller. The designed low-complex narrow pulse generator and digital ring on–off VCO ensure a high speed transmitting. The low power is realized by using a subtractor to eliminate the base-band component from the output of the VCO and making the UWB RF buffer and the VCO operating in standby mode. The design was fabricated by a standard 0.18 μm CMOS technology. The test results show that the design can achieve maximum data-rate of 250 Mbps, frequency bandwidth from 3 to 5 GHz, radiated power tuning from −40 dBm to −60 dBm, low-power of 8 pJ/bit, and small circuit area of 0.18 mm².     

Ultra-wide-band transmitter for low-power wireless body area networks: design and evaluation

The successful realization of a wireless body area network (WBAN) requires innovative solutions to meet the energy consumption budget of the autonomous sensor nodes. The radio interface is a major challenge, since its power consumption must be reduced below 100 /spl mu/W (energy scavenging limit). The emerging ultra-wide-band (UWB) technology shows strong advantages in reaching this target. First, most of the complexity of an UWB system is in the receiver, which is a perfect scenario in the WBAN context. Second, the very little hardware complexity of a UWB transmitter offers the potential for low-cost and highly integrated solutions. Finally, in a pulse-based UWB scheme, the transmitter can be duty-cycled at the pulse rate, thereby reducing the baseline power consumption. We present a low-power UWB transmitter that can be fully integrated in standard CMOS technology. Measured performances of a fully integrated pulse generator are provided, showing the potential of UWB for low power and low cost implementations. Finally, using a WBAN channel model, we present a comparison between our UWB solution and state-of-the-art low-power narrow-band implementations. This paper shows that UWB performs better in the short range due to a reduced baseline power consumption.     

A 18-pJ/Pulse OOK CMOS Transmitter for Multiband UWB Impulse Radio

This letter presents a new transmitter for multiband impulse radio ultra-wideband (IR-UWB) systems. The ultra low-power, low-complexity UWB transmitter operates over three 528-MHz subbands in 3-5 GHz band. It consists of an on-off keying (OOK) modulator and a pulse generator which is based on the ON/OFF switching operation of an LC oscillator. Measurements show a pulse duration of 3.5 ns and a spectrum that fully complies with the FCC spectral mask with more than 20 dB of sidelobe rejection. Implemented in 0.18-mum CMOS technology, the transmitter operates in burst mode and dissipates only 18 pJ of energy consumption per pulse. The transmitter is best suited for energy detection receivers.     

The design and analysis of a Miller-divider-based clock generator for MBOA-UWB application

A Miller-divider-based clock generator is proposed for Multi-Band OFDM Alliance (MBOA) ultrawideband (UWB) application. Employing closed-loop operation, the clock generator can produce three different carrier frequencies with negligible in-band spurs. The settling time of the proposed clock generator is analyzed based on a linear feedback system. A transistor sizing optimization technique for active inductors with a current-reusing technique is used to achieve low-power operation and area saving. Fabricated in a 0.18-/spl mu/m technology, the clock generator achieves less than 9.5-ns settling time while dissipating less than 47 mW from a 1.8-V power supply.     

A CMOS UWB Pulse Generator for 6–10 GHz Applications

A CMOS ultra wideband (UWB) pulse generator with low energy dissipation and high peak amplitude is presented for 6–10 GHz applications. The pulse generator complies with the FCC spectral mask for indoor UWB systems. It consists of a glitch generator, a pulsed oscillator, and a pulse shaping filter. The pulsed oscillator is switched on by the glitch signal only for a short duration, so as to make a UWB pulse. For sub-nanosecond pulse generation, a pulsed oscillator with fast transient response is proposed. A pulse shaping filter makes the oscillator output fall into the FCC spectral mask. The pulse generator is fabricated using a 0.18 $mu$ m CMOS process. The core chip has a size of 0.11 mm $^{2}$. It shows pulse duration of about 500 ps with ${-}10$ dB bandwidth of 4.5 GHz from 5.9 to 10.4 GHz. The energy consumption is 27.6 pJ per pulse with a peak-to-peak amplitude of 673 mV on a 50 $Omega$ output load. The generated pulses are very coherent with 1.8 ps RMS jitter.      

Analysis and Design of Two Low-Power Ultra-Wideband CMOS Low-Noise Amplifiers With Out-Band Rejection

Two 3–5-GHz low-power ultra-wideband (UWB) low-noise amplifiers (LNAs) with out-band rejection function using 0.18- $mu{hbox{m}}$ CMOS technology are presented. Due to the Federal Communications Commission's stringent power-emission limitation at the transmitter, the received signal power in the UWB system is smaller than those of the close narrowband interferers such as the IEEE 802.11 a/b/g wireless local area network, and the 1.8-GHz digital cellular service/global system for mobile communications. Therefore, we proposed a wideband input network with out-band rejection capability to suppress the out-band properties for our first UWB LNA. Moreover, a feedback structure and dual-band notch filter with low-power active inductors will further attenuate the out-band interferers without deteriorating the input matching bandwidth in the second UWB LNA. The 55/48/45 dB maximum rejections at 1.8/2.4/5.2 GHz, a power gain of 15 dB, and 3.5-dB minimum noise figure can be measured while consuming a dc power of only 5 mW.      

A 1 V 2.2 mW 7 GHz CMOS Quadrature VCO Using Current-Reuse and Cross-Coupled Transformer-Feedback Technology

A current-reused quadrature voltage-controlled oscillator (CR-QVCO) is proposed with the cross-coupled transformer-feedback technology for the quadrature signal generation. This CR-QVCO has the advantages of low-voltage/low-power operation with an adequate phase noise performance. A compact differential three-port transformer, in which two half-circle secondary coils are carefully designed to optimize the effective turn ratio and the coupling factor, is newly constructed to satisfy the need of signal coupling and to save the area consumption simultaneously. The quadrature oscillator providing a center frequency of 7.128 GHz for the ultrawideband (UWB) frequency synthesizer use is demonstrated in a 0.18 mum RF CMOS technology. The oscillator core dissipates 2.2 mW from a 1 V supply and occupies an area of 0.48 mm². A tuning range of 330 MHz (with a maximum control voltage of 1.8 V) can be achieved to stand the frequency shift caused by the process variation. The measured phase noise is -111.2 dBc/Hz at 1 MHz offset from the center frequency. The IQ phase error shown is less than 2deg. The calculated figure-of-merit (FOM) is 184.8 dB.     

Distributed Waveform Generator: A New Circuit Technique for Ultra-Wideband Pulse Generation, Shaping and Modulation

A new circuit technique, the distributed waveform generator (DWG), is proposed for low-power ultra-wideband pulse generation, shaping and modulation. It time-interleaves multiple impulse generators, and uses distributed circuit techniques to combine generated wideband impulses. Built-in pulse shaping can be realized by programming the delay and amplitude of each impulse similar to an FIR filter. Pulse modulation schemes such as on-off keying (OOK) and pulse position modulation (PPM) can be easily applied in this architecture. Two DWG circuit prototypes were implemented in a standard 0.18 $muhbox{m}$ digital CMOS technology to demonstrate its advantages. A 10-tap, 10 GSample/s, single-polarity DWG prototype achieves a pulse rate of 1 GHz while consuming 50 mW, and demonstrates OOK modulation using 16 Mb/s PRBS data. A 10-tap, 10 GSample/s, dual-polarity DWG prototype was developed to generate UWB pulses compliant with the transmit power emission mask. Based on the latter DWG design, a reconfigurable impulse radio UWB (IR-UWB) transmitter prototype was implemented. The transmitter's pulse rate can be varied from 16 MHz range up to 2.5 GHz. The bandwidth of generated UWB pulses is also variable, and was measured up to 6 GHz (${- 10} {rm dB}$ bandwidth). Both OOK and PPM modulation schemes are successfully demonstrated using 32 Mb/s PRBS data. The IR-UWB transmitter achieves a measured energy efficiency of 45 pJ/pulse, independent of pulse rate.      

Flexible Chaotic UWB Communication System With Adjustable Channel Bandwidth in CMOS Technology

A flexible chaotic ultra-wideband (UWB) communication system with an adjustable channel spectrum is proposed. Since the chaotic UWB bandwidth (BW) is independent of the data rate, the system band plan can be flexibly organized for various communication environments. The proposed system can overcome the spectral inefficiency and RF power wastage that is typically observed in conventional methods by utilizing adjustable channel allocations. A novel chaotic signal generator is designed with an adjustable frequency range of 3.5-4.5 GHz and BW of 70-620 MHz. The chaotic UWB transceiver system is implemented in CMOS 0.18-mum technology, and it features tunable chaotic signal generation and adaptive detection. The system performance is evaluated for digital data transmission rates of up to 15 Mb/s.     

On the Development of an Integrated CMOS-Based UWB Tunable-Pulse Transmit Module

A novel low-cost low-power fully integrated tunable transmit module composed of a tunable CMOS monocycle pulse generator and compact uniplanar antenna was designed, built, and tested for ultra-wideband (UWB) impulse systems. The CMOS tunable pulse generator integrates a tuning delay circuit, square-wave generator, impulse-forming circuit, and pulse-shaping circuit in a single chip using a standard low-cost 0.25-$muhbox m$CMOS process. It can generate a monocycle pulse and Gaussian-type impulse (without the pulse-shaping circuitry) signals with tunable pulse duration. A compact uniplanar UWB antenna was also developed and integrated directly with the CMOS pulse generator chip to form the complete integrated tunable UWB transmit module. Measured results show that the CMOS tunable pulse generator can produce a 0.3–0.6-V peak-to-peak monocycle pulse with 140–350-ps tunable pulse duration and a 0.5–1.3-V peak-to-peak impulse signal with 100–300-ps tunable pulse-duration, and the uniplanar antenna has less than a 18-dB return loss and is suitable for transmitting/receiving UWB time-domain impulse signals covering the entire UWB bandwidth of 3.1–10.6 GHz. Good agreement between measured and calculated performance is also achieved. The UWB transmit module was experimentally characterized and its performance is verified. This UWB module finds applications in various time-domain UWB systems including wireless communications and radar.     

Ultra wideband, low-power, 3-5.6 GHz, CMOS voltage-controlled oscillator

In this paper, a low-power inductorless ultra wideband (UWB) CMOS voltage-controlled oscillator is designed in TSMC 0.18 μm CMOS technology as a part of a ultra wideband FM (UWBFM) transmitter. The VCO includes a current-controlled oscillator (CCO) which generates output frequencies between 1.5 and 2.8 GHz and a voltage-to-current (V-to-I) converter. A low-power frequency doubler based on a Gilbert cell, which operates in weak inversion, doubles the VCO tuning range achieving oscillation frequencies between 3 and 5.6 GHz. Thus, the well-known proportionality between the oscillation frequency and the bias tuning current in CCOs is avoided for the entire achieved tuning range, resulting in a lower power design. The employed architecture provides high suppression, over 45 dB, of the 1st and 3rd harmonics, while enabling high-frequency operation and conversion gain due to the unbalanced structure and the single-ended output. The current consumption is 5 mA at a supply voltage of 1.8 V. The VCO exhibits a phase noise of −80.56 dBc/Hz at 1 MHz frequency offset from the carrier and a very high ratio of tuning range (60.4%) over power consumption equal to 8.26 dB which is essential for a UWBFM transmitter.     

Self-calibrated quadrature generator for WLAN multistandard frequency synthesizer

A self-calibrated quadrature generator capable of generating local oscillator (LO) outputs for IEEE 802.11a-b is presented. The quadrature generator is embedded in a frequency synthesizer that generates reference frequencies at 2.4 and 5GHz. A new sequential calibration scheme maintains the quadrature at the 5-GHz output within a maximum phase error of 2/spl deg/, while a divide-by-two flip-flop generates the quadrature output at 2.4 GHz. The circuit is fabricated in a 0.25-/spl mu/m SiGe BiCMOS technology and occupies a silicon area of 2 mm/sup 2/; the quadrature generator consumes a current of 5 mA from a 2.5-V supply.     

一种有载频超宽带脉冲源设计

针对无载频脉冲低频分量大、辐射效率低、频带可调性差等问题,设计了一种以阶跃恢复二极管、D触发器及超宽带调制器为主的宽频带、高重复频率、低振铃水平的有载频超宽带脉冲源。该脉冲源电路由驱动电路、高速开关电路、整形电路、超宽带调制器及振荡器电路组成。实测结果表明,脉冲源输出脉冲信号重复频率可达125 MHz,脉冲宽度600 ps（底宽）,脉冲振铃水平低于10%,峰-峰值为5.4 V,-10 dB带宽可达4.2 GHz。脉冲信号中心频率与载频相同,可在6.6~8.5 GHz之间灵活设置。利用所设计的脉冲源进行时域测量,其结果与矢量网络分析仪频域测量结果相比幅频特性均方根误差小于0.21 dB。该脉冲源可应用于超宽带时域测量、短距离高速无线通信、高精度室内定位等应用。     

Ultra-Wideband, Low-Power, Inductorless, 3.1�C4.8?GHz, CMOS VCO

A low-power, inductorless, UWB CMOS voltage controlled oscillator is designed in 0.18 μm CMOS technology targeting to a UWBFM transmitter application. The VCO is a Double-Cross-Coupled Multivibrator and generates output frequencies ranging from 1.55 GHz to 2.4 GHz. A low-power frequency doubler based on a Gilbert cell, which operates in weak inversion, doubles the VCO tuning range from 3.1 GHz to 4.8 GHz. The proportionality between the oscillation frequency and the bias current is avoided in this case for the entire achieved tuning range resulting in a low-power design. The selected architecture provides high suppression, over 45 dB, for the 1^st and 3^rd harmonics, while enabling high-frequency operation and conversion gain due to the unbalanced structure and the single-ended output. The proposed VCO draws 4 mA from a 1.8 V supply, it has a phase noise of −76.7 dBc/Hz at 1 MHz offset from the center frequency, while it exhibits a very high ratio of tuning range (43%) over power consumption equal to 7.76 dB.     

On the use of a digital computer as a two-phase variable-amplitudevariable-frequency oscillator

A feasibility study on the use of a digital computer as a variable-amplitude variable-frequency oscillator which generates two-phase sinusoidal excitation control signals for a dual-excited synchronous generator is described. The oscillator uses two input signals. One input signal is used to control the frequency of the oscillator outputs, and the other is used to control their amplitudes. By a single variable, the software can be configured to vary the oscillator frequency range and to greatly reduce (almost eliminate) the harmonic distortion of the output signals. The harmonic distortion is constant and independent of the output frequency for each possible oscillator frequency range. The software-based oscillator design is flexible and can be used to generate different types of multiphase signal waveforms     

3–5 GHz FSK-OOK ultra wideband transmitter based on memristive ring oscillator

The compatibility of a memristor with CMOS technology has attracted the attention of many researchers to explore its application further. In this work, an ultra low-power and low-complexity ultra wideband (UWB) chirp transmitter based on memristive ring oscillator (RO) is designed in 0.18 µm TSMC CMOS technology. The Chirp waveform was chosen because of its low side-lobes and large time-bandwidth product, which allows for more spectrum use. OOK and FSK modulation are supported by the proposed UWB chirp transmitter. The chirp frequency is controlled linearly with time across the pulse duration using memristors. The binary data "1" and "0" are encoded using distinct chirp frequencies in FSK TX. The simulation results show a maximum TX output pulse of 457 mV _Vpp with a pulse width of 21 ns. The overall DC power consumption for a pulse repetition frequency (PRF) of 20 MHz is 0.328 mW, equivalent to an energy consumption of 16.4 pJ/pulse. The simulated output amplitude for OOK TX is 453 mV Vpp with a pulse width of 48 ns and a PSD of ? 10 dB over a frequency range of 3.2 to 4.8 GHz. The overall power consumption at 10 MHz PRF is 0.136 mW, which corresponds to an energy consumption of 13.6 pJ/pulse.

     

A semi-digital delay-locked loop using an analog-based finite state machine

This brief describes a low-power full-rate semi-digital delay-locked loop (DLL) architecture using an analog-based finite state machine (AFSM) and a polyphase filter. The AFSM architecture uses low-power analog blocks to map high-frequency loop feedback information to low frequency, thus reducing the total power required for digital signal processing and for the macro as a whole. The polyphase filter generates full-rate multiphase outputs for a phase rotator, hence a reference clock of the semi-digital DLL can be generated by any reference source including a phase-locked loop with an LC voltage-controlled oscillator. The prototype semi-digital DLL in 0.12-/spl mu/m CMOS exhibits less than 10/sup -12/ bit error rate at 3.2 Gb/s consuming 60 mW.     

A monolithic digital clock-generator for on-chip clocking of customDSP's

This paper shows a robust and easily implemented clock generator for custom designs. It is a fully digital design suitable for both high-speed clocking and low-voltage applications. This clocking method is digital, and it avoids analog methods like phase locked loops or delay line loops. Instead, the clock generator is based on a ring counter which stops a ring oscillator after the correct number of cycles. Both a 385 MHz clock and a 15 MHz custom DSP application using the on-chip clocking strategy are described. The prototypes have been fabricated in a 0.8 μm standard CMOS process. The major advantages with this clocking method are robustness, small size, low-power consumption, and that it can operate at a very low supply voltage