Quantum mechanical compact modeling of symmetric double-gate MOSFETs using variational approach

A physics-based analytical model for symmetrically biased double-gate (DG) MOSFETs considering quantum mechanical effects is proposed. Schrödinger's and Poisson's equations are solved simultaneously using a variational approach. Solving the Poisson and Schrödinger equations simultaneously reveals quantum mechanical effects (QME) that influence the performance of DG MOSFETs. The inversion charge and electrical potential distributions perpendicular to the channel are expressed in closed forms. We systematically evaluated and analyzed the potentials and inversion charges, taking QME into consideration, in Si based double gate devices. The effect of silicon thickness variation in inversion-layer charge and potentials are quantitatively defined. The analytical solutions provide good physical insight into the quantization caused by quantum confinement under various gate biases.     

Analytical analysis of nanoscale multiple gate MOSFETs including effects of hot-carrier induced interface charges

As the channel length rapidly shrinks down to the nanoscale regime, the multiple gate MOSFETs structures have been considered as potential candidates for a CMOS device scaling due to its good short-channel-effects (SCEs) immunity. Therefore, in this work we investigate the scaling capability of Double Gate (DG) and Gate All Around (GAA) MOSFETs using an analytical analysis of the two dimensional Poisson equation in which the hot-carrier induced interface charge effects have been considered. Basing on this analysis, we have found that the degradation becomes more important when the channel length gets shorter, and the minimum surface potential position is affected by the hot-carrier induced localized interface charge density. Using this analysis, we have studied the scaling limits of DG and GAA MOSFETs and compared their performances including the hot-carrier effects. Our obtained results showed that the analytical analysis is in close agreement with the 2-D numerical simulation over a wide range of devices parameters. The proposed analytical approach may provide a theoretical basis and physical insights for multiple gate MOSFETs design including the hot-carrier degradation effects.     

ANFIS-based approach to studying subthreshold behavior including the traps effect for nanoscale thin-film DG MOSFETs

A fuzzy framework based on an adaptive network fuzzy inference system(ANFIS) is proposed to evaluate the relative degradation of the basic subthreshold parameters due to hot-carrier effects for nanoscale thin-film double-gate(DG) MOSFETs.The effect of the channel length and thickness on the resulting degradation is addressed, and 2-D numerical simulations are used for the elaboration of the training database.Several membership function shapes are developed,and the best one in terms of accuracy is selected.The predicted results agree well with the 2-D numerical simulations and can be efficiently used to investigate the impact of the interface fixed charges and quantum confinement on nanoscale DG MOSFET subthreshold behavior.Therefore,the proposed ANFIS-based approach offers a simple and accurate technique to study nanoscale devices,including the hot-carrier and quantum effects.     

The effects of fixed bulk charge on the characteristics of metal-oxide-semiconductor transistors

The theory of the characteristics of the MOS transistors is developed based on a model in which both the bulk charge due to the ionized impurity in the semiconductor substrate and the difference between the electrostatic potential and the voltage drop in the channel are included. A detailed comparison of the theory is made with experimental data of gate capacitance, drain current voltage characteristics, and transconductance characteristics on both N-channel and P-channel silicon devices with thin (2000 A) and thick (6200 and 8400 A) oxides under the gate electrode. The correlation is good using the surface mobility as the adjustable parameter. Mobility reduction in the saturation transconductance characteristics is predicted in the theory and demonstrated in the experimental data. It arises entirely from the bulk charge, which modifies the device characteristics, and is not associated with some basic surface scattering phenomena, which further reduce the mobility. It is also demonstrated experimentally that to evaluate a physically meaningful surface mobility from the conductance of the channel, the interface surface state charge Qsscannot be assumed constant in the devices used in this study.     

Performance analysis of long Ge channel double gate (DG) p MOSFETs with high-k gate dielectrics based on carrier concentration formulation

In this paper, electrical behavior of symmetric double gate Ge channel MOSFETs with high-k dielectrics is reported on the basis of carrier concentration formalism. The model relies on the solution of Poisson-Boltzmann equations subject to suitable boundary conditions taking into account the effect of interface trap charge density (D_it) and the Pao-Sah’s current formulation considering field dependent hole mobility. It is continuous as it holds good for sub-threshold, weak and strong inversion regions of device operation. The proposed model has been employed to calculate the drain current of DG MOSFETs for different values of gate voltage and drain voltage along with various important device parameters such as transconductance, output conductance, and transconductance per unit drain current for a wide range of interface trap charge density, equivalent oxide thickness (EOT) and bias conditions. Moreover, most of the important device parameters are compared with their corresponding Si counter parts. Accuracy of the model has been verified by comparing analytical results with the numerical simulation data. A notable improvement of the drive current and transconductance for Ge devices is observed with reference to Si devices, particularly when D_it is small.     

Two-dimensional analytical model of double-gate tunnel FETs with interface trapped charges including effects of channel mobile charge carriers

A two-dimensional analytical model of double-gate(DG) tunneling field-effect transistors(TFETs) with interface trapped charges is proposed in this paper. The influence of the channel mobile charges on the potential profile is also taken into account in order to improve the accuracy of the models. On the basis of potential profile, the electric field is derived and the expression for the drain current is obtained by integrating the BTBT generation rate. The model can be used to study the impact of interface trapped charges on the surface potential, the shortest tunneling length, the drain current and the threshold voltage for varying interface trapped charge densities, length of damaged region as well as the structural parameters of the DG TFET and can also be utilized to design the charge trapped memory devices based on TFET. The biggest advantage of this model is that it is more accurate, and in its expression there are no fitting parameters with small calculating amount. Very good agreements for both the potential, drain current and threshold voltage are observed between the model calculations and the simulated results.     

The quantitative effects of interface states on the performance of charge-coupled devices

The several effects of interface states in limiting the performance of surface channel charge-coupled devices (CCD's) are described and evaluated. The limitations on transfer efficiency may be minimized by using a background charge in the device at all times. Experimental measurements of transfer inefficiency on three-phase devices and a two-phase device are presented and correlated with the predicted values, although measurements of the density and capture cross sections of interface states after device fabrication are required for accurate quantitative predictions of transfer inefficiencies. It is concluded that trapping effects are a limitation on the transfer efficiencies obtainable in surface channel charge-coupled devices, particularly, for example, at frequencies less than 1 MHz for devices having 10-µm-long transfer electrodes, but are not a direct limitation on the high-frequency performance. The effect of interface states in adding transfer noise onto the charge packets is also described, and is shown to be small, although in some devices it may reduce the signal-to-noise ratios that might otherwise be possible.     

An analytical threshold voltage model of NMOSFETs with hot-carrier induced interface charge effect

An analytical threshold voltage model of NMOSFETs including the effect of hot-carrier-induced interface charges is presented. A step function describing the interface charge distribution along the channel is used to account for the hot carrier induced damage, and a pseudo-2D method is applied to derive the surface potential. The threshold voltage model is then developed by solving the gate-to-source voltage at the onset of surface inversion where the minimum surface potential equals the channel potential. Both the drain-induced barrier lowering (DIBL) and body effects are included in the present model as well. The present threshold voltage model is validated for both fresh and damaged devices. The results show that the threshold voltage shifts upward and approaches a maximum value with negative interface charges and shifts downward and reaches a minimum value with positive interface charges as the interface charge region length is increased from zero to the channel length. Model is successfully verified using simulation data obtained from TCAD (technology-based computer-aided design).     

The effects of bulk traps on the performance of bulk channel charge-coupled devices

The effects of bulk traps on the transfer effciency and transfer noise in bulk channel charge-coupled devices (BCCD's) are calculated for different charge packet sizes and operating frequencies. These predictions are compared with experimental results and the distribution and density of bulk states in actual devices are thereby measured. The measured low transfer inefficiency of 10^-4per transfer with no intentionally introduced background charge and low transfer noise are shown to be due to a low bulk state density of 2 × 10¹¹/cm³. A detailed comparison of estimated noise in both surface and bulk channel versions of an image sensor and an analog delay line show that BCCD's are very attractive for low-light level imaging but not as attractive for analog signal processing.     

A compact charge-based model to study the nanoscale undoped double gate MOSFETs for nanoelectronic circuit design using genetic algorithms

The analytical modeling of nanoscale devices is an important area of computer-aided design for fast and accurate nanoelectronic design and optimization.In the present paper,a new approach for modeling semiconductor devices,nanoscale double gate DG MOSFETs,by use of the gradual channel approximation(GC) approach and genetic algorithm optimization technique(GA) is presented.The proposed approach combines the universal optimization and fitting capability of GA and the cost-effective optimization concept of quantum correction,to achieve reliable,accurate and simple compact models for nanoelectronic circuit simulations.Our compact models give good predictions of the quantum capacitance,threshold voltage shift,quantum inversion charge density and drain current.These models have been verified with 2D self-consistent results from numerical calculations of the coupled Poisson-Schrodinger equations.The developed models can also be incorporated into nanoelectronic circuit simulators to study the nanoscale CMOS-based devices without impact on the computational time and data storage.     

Impact of device physics on DG and SOI MOSFET linearity

The influence of different physical mechanisms on MOSFET linearity is analyzed using 2D TCAD device simulations. In particular, the RF linearity performance of 50 nm gate length SOI and DG-MOSFETs are investigated and compared with traditional bulk MOSFETs. We employ the hydrodynamic (HD) transport model to account for non-equilibrium carrier dynamics and the density gradient approximation for quantum mechanical effects. Impact ionization of channel carriers and self-heating effect (SHE) are also accounted for in the thin-body devices. Our results disclose the relationship between various aspects of device physics and linearity. We show that linearity performance is particularly sensitive to non-local effects and are lowered due to SHE. Quantum mechanical effects appear to have a small positive impact on linearity. Drift-diffusion approximation is found to be unreliable for linearity analysis of DG MOSFETs due to large overestimation from this model. We also observe that linearity has an anomalous monotonous dependence on the ambient temperature.     

Quantum effects in Si n-MOS inversion layer at high substrate concentration

The charge distribution at the semiconductgor-insulator interface is calculated for electrons by solving Schrödinger's and Poisson's equations self-consistently for particles obeying Fermi-Dirac statistics at 300 K. The results are applied to carriers in the channel of a crystalline MOSFET with the (100) axis perpendicular to the gate oxide. The inversion charge density calculated quantum mechanically is smaller than that calculated classically. This affects the shift of the subthreshold curves. The shift is larger at higher substrate impurity concentrations, and is especially pronounced at more than 10¹⁷ cm⁻³, which is the concentration used in recent MOS devices. The shift is as large as 0.18 V when the substrate impurity concentration is 8.5 × 10¹⁷ cm⁻³. Comparisons with measurement are also shown and it agrees well with quantum mechanical calculations. The inversion layer depth is compared, and a new efficient method is derived by transferring the quantum mechanical effect into the classical calculation. The results of this new method agree well with the quantum mechanical calculations and with the measurements.     

Charge density at the contacts of symmetric and asymmetric organic diodes

The organic diode, or metal-organic-metal (MOM) structure, is constituent key building block of organic-devices. The physical understanding and performance evaluation of these devices usually require proper modeling and simulation of the metal-organic structure. A topic of major concern in the simulation of the MOM structure, although frequently mishandled, is the selection of proper boundary conditions at the metal-organic interface. In this work, we determine the boundary conditions for the charge density at the metal-organic contact. Symmetric and asymmetric organic diodes with unipolar and bipolar conduction are analyzed. Using experimental current-voltage curves, an analytical method to determine the value of the charge density at the contacts is proposed. In single-carrier diodes, we observe that the charge concentration at the interface due to injection follows a power-law function of the current in metal-organic contacts in drift-dominated transport. This boundary condition is the way to introduce the contact effects in models. The contact affects the other regions (e.g., the bulk) as a boundary condition. This boundary condition for the charge density keeps information about the limited recombination velocity at the contacts and the contribution from space charge limited conduction (SCLC) in the bulk. In diffusion-dominated transport, at low bias close to the diode’s built-in voltage, the charge density at the contact is almost constant with the current. The complete relation between charge and current for injecting electrodes, extracted from the analysis of single-carrier diodes, can be used as boundary condition in bipolar devices.     

Theoretical Investigation of Dielectric Materials for Two‐Dimensional Field‐Effect Transistors

Two‐dimensional dielectric materials that can inhibit electronic leakage are vital for developing next‐generation all‐2D electronic devices. However, few comprehensive studies of the atomistic nature of 2D insulating dielectrics currently exist. In this work, computational design strategies based on density functional theory and quantum dynamics simulations are used to assess the charge permeability through dielectric materials. Promising 2D dielectrics are considered, including monolayer SiC, hBN, and BeO, which possess promising properties and a honeycomb structure compatible with that of MoS₂, currently the most commonly used channel material in all‐2D transistors. A useful protocol for discovering promising dielectrics is described. The atomic structures of the interfaces are determined and their stabilities are evaluated by studying the interface formation energies and the presence of stress/strain at the interfaces. The interface electronic structures are characterized by studying the band structures, band offsets, and charge transfer at the interface. These important quantities reveal that all three materials chosen are good dielectric materials, but SiC is the poorest among them, BeO has the best insulting properties as a monolayer and hBN prevents the most charge leakage at the interface. It is shown how this protocol can also consider the effects of external potentials and temperatures.     

Determination of the spatial variation of interface trapped charge using short-channel MOSFET's

Previous measurements of interface trapped charge (ITC) by charge pumping used long-channel metal gate transistors. In this paper charge pumping is extended to short-channel Self-aligned polysilicon gate transistors and used to determine the spatial variation of ITC on wafers. Only the MOSFET gate area and a pulse frequency are required to calculate ITC density from the charge pumping current. In previous work, with long-channel devices, it appears that some investigators used the design dimension of metal gate devices and others used the metallurgical channel length of the transistors to calculate gate area. Two-dimensional simulation of the charge pumping measurement showed that, for a sufficient applied pulse height voltage, the correct area is obtained if the polysilicon gate length and width asmeasured are used. When the process-induced variation of the polysilicon gate length is included in the measurement analysis, no systematic variation of ITC is observed across 5 cm wafers. The charge pumping measurement technique on short-channel MOSFET's can be used to resolve the spatial variation of ITC if the area variations are correctly handled. The measurement of ITC is linear with frequency from 1 kHz to 1 MHz, indicating that the emission time constant of the fast states measured using this method is ≤10^-6s. A variation of ITC with channel lengths is also observed. This variation could not be detected using large area devices such as capacitors, but will have important consequences for short-channel MOSFET's.     

Experimental Evaluation of Circuit-Based Modeling of the NBTI Effects in Double-Gate FinFETs

In this work, an example of practical implementation of the auxiliary sub-circuit (ASC) for modeling of the NBTI effects in DG FinFETs is described. A good agreement between the simulated and measured electrical characteristics of p-type DG FinFETs fabricated in SOI technology has been obtained using the industry-standard BSIM-CMG model with ASC. The oxide and interface trap densities are extracted in Spice simulations by tuning the ASC trapped charge parameters to fit the NBTI experimental data. The increase of oxide and interface trapped charge in p-type DG FinFET device is found to follow the logarithmic dependence with NBTI stress time.     

Simulation of quantum effects along the channel of ultrascaledSi-based MOSFETs

Quantum transport simulations, including phase-breaking scattering, are used to observe the transition from classical to quantum transport in ultrascaled Si and SiGe heterostructure MOSFETs in order to gauge the potential effectiveness of semiclassical and pure phase-coherent quantum transport models as this transition is approached. It is shown that semiclassical models of transport along the length of the channel (as opposed to normal to the channel, where the importance of quantum mechanical effects has long been recognized) may remain reliable for channel lengths down to roughly 10 nm and perhaps beyond, and likely more reliable at this point than phase-coherent quantum transport simulations even when much of the transport is coherent/ballistic. As coherent transport effects within the channel eventually do become significant for ballistic carriers, the phase-breaking scattering rate, itself, also becomes a nonlocal function of the carrier's kinetic energy placing further demands on simulation. Simulations also reaffirm that for injection into the channel, the modeling of quantum transport effects such as tunneling, particularly in Si-SiGe heterostructure MOSFET's, will be important in much longer devices. However, even for this purpose it may not be possible to neglect the effects of inelastic scattering that can provide additional tunneling "paths."     

Bulk charge effects in VLSI MOSFET's

An analysis of the relative magnitudes of the bulk charge for three MOSFET structures suitable for VLSI devices, such as NMOS (normal), VMOS (V slot) and UMOS (U slot), is carried out. It is shown that even for the same channel design (i.e. channel length, doping, source/drain junction depth, and oxide thickness), the amount of bulk charge and hence the threshold voltage can be significantly different for the three structures. This effect becomes more important with decreasing channel length, and increasing source to substrate bias. Further, for a given channel length, the bulk charge and hence the threshold voltage of an NMOS decreases with increasing source/drain junction depth. However, for the VMOS and UMOS structures, the bulk charge as well as the threshold voltage do not depend on the junction depth of the source/drain diffusion. An expression is also derived for the bulk charge of UMOS transistors valid for both short and long channels.     

A physically based compact model of partially depleted SOI MOSFETsfor analog circuit simulation

In this paper, the Southampton Thermal AnaloGue (STAG) compact model for partially depleted (PD) silicon-on-insulator (SOI) MOSFETs is presented. The model uses a single expression to model the channel current, thereby ensuring continuous transition between all operating regions. Furthermore, care has been taken to ensure that this expression is also infinitely differentiable, resulting in smooth and continuous conductances and capacitances as well as higher order derivatives. Floating-body effects, which are particular to PD SOI and which are of concern to analog circuit designers in this technology, are well modeled. Small geometry effects such as channel length modulation (CLM), drain-induced barrier lowering (DIBL), charge sharing, and high field mobility effects have also been included. Self-heating (SH) effects are much more apparent in SOI devices than in equivalent bulk devices. These have been modeled in a consistent manner, and the implementation in SPICE3f5 gives the user an additional thermal node which allows internal device temperature rises to be monitored and also accommodates the modeling of coupled heating between separate devices. The model has been successfully used to simulate a variety of circuits which commonly cause problems with convergence. Due to its inherent robustness, the model can normally achieve convergence without recourse to the setting of initial nodal voltage estimates     

Circuit Techniques Utilizing Independent Gate Control in Double-Gate Technologies

Independent gate control in double-gate (DG) devices enhances circuit performance and robustness while substantially reducing leakage and chip area. In this paper, we describe circuit techniques which take advantage of the independent biasing properties of symmetrical and asymmetrical DG devices in design. DG circuits at the 25-nm node are analyzed via mixed-mode numerical simulations using Taurus MEDICI. In dynamic circuits, we give examples of conditional keepers, charge sharing prevention scheme, and static keepers. A conditional keeper can dynamically achieve the optimal strength ratio between keeper and evaluation devices by utilizing the front- and backchannel currents in DG devices. A charge sharing mitigation scheme utilizing the back-gate of a logic transistor is then described. Static data retention scheme in dynamic circuits is proposed. A case study for analog applications using a voltage controlled oscillator (VCO) illustrates the specific advantages of DG devices.