共查询到19条相似文献,搜索用时 187 毫秒
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本文介绍了利用点对点(哪)数字通信系统模型,推导卷积编码和Viterbi译码的非线性传输函数的方法以及对Viterbi译码软判决和硬判决的性能分析。通过Matlab中的Simulink仿真模块,对系统模型进行了建模,其仿真结果表明。增大卷积编码和Viterbi译码的约束长度可以提高误码性能。最后,得到了Viterbi译码在软判决和硬判决条件下的误码曲线。 相似文献
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本文分析了高阶调制通信系统中将解调和卷积码的译码联合的解码方法,并与传统的Viterbi软判决译码和Viterbi硬判决译码算法进行了比较.仿真结果表明,在不增加复杂度和保持相同的误码率的条件下系统所需信噪比比Viterbi软判决译码降低0.2-0.3dB.本文给出的方法也可推广到更高阶调制通信系统中. 相似文献
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针对通信系统中传统维特比(Viterbi)译码器结构复杂、译码延时大、资源消耗大的问题,提出了一种新的基于FPGA的Viterbi译码器设计。结合(2,1,7)卷积编码器和Viterbi译码器的工作原理,设计出译码器的核心组成模块,具体采用3比特软判决译码,用曼哈顿距离计算分支度量,32个碟型加比选子单元并行运算,完成幸存路径和幸存信息的计算。幸存路径管理模块采用Viterbi截短译码算法,回溯操作分成写数据、回溯读和译码读,以改进的流水线进行并行译码操作,译码延时和储存空间分别降低至和。 相似文献
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软判决译码中软信息的提取 总被引:1,自引:0,他引:1
本文基于单载波和多载波传输的等效基带模型的衰落信道,采用比特交织的编码调制(BICM)系统,研究了软判决译码所需的软信息的提取。通过仿真说明,反馈信道噪声信息的结合解调与译码的迭代译码方法具有一定的鲁棒性。 相似文献
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一种新的π/4DQPSK解调译码方案 总被引:1,自引:0,他引:1
本文提出了一种新的π/4DQPSK解调译码方案.该方案利用非冗余纠错差分解调的硬判决信息对Viterbi软判决译码时的量度加权,从而改变了传统的差分解调结合软判决译码的量度值,使差分解调软输出的信噪比得到改善,提高了Viterbi软判决译码的性能.计算机仿真表明,相对于传统的差分解调结合软判决译码,该算法在误比特率BER为10-5时在AWGN信道中有1.4dB的性能改善,在Rician信道中同样有显著的性能改善.这使得在普遍采用差分解调软判决译码的卫星通信系统中系统容量和通信质量都得到显著改善. 相似文献
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在对DVB-T系统信道内码解码方案的MATLAB和定点C仿真的基础上,介绍了DVB-T系统接收端的解星座映射、解频率交织、解比特交织、解删余以及维特比译码,并采用FPGA技术实现. 相似文献
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利用现场可编程门阵列(FPGA,Field Programmable Gate Array)实现了一种基于深空通信的级联码结构。该级联码包括内码和外码,内码是基于全并行的软判决Viterbi译码器结构,用来纠正随机错误,结合帧同步技术完成解交织,然后进行外码里德-所罗门码(RS codes,Reed-solomon codes)译码,纠正突发错误,实现级联码译码。通过实际硬件测试,在满足系统误码率要求的前提下,使用该级联码译码器能够降低发射功率或减少天线尺寸,对降低系统成本及提高系统性能具有非常重要的作用。 相似文献
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卷积码维特比译码算法最佳反馈深度研究 总被引:1,自引:2,他引:1
卷积码可以用维特比算法作为译码算法,由于维特比译码器复杂度随着反馈深度的增长成指数倍增长,因而译码反馈深度对译码器的复杂度影响很大甚至可能无法实用,目前有些文献中仅给出了反馈深度的大致范围,但在硬件实现和性能仿真时无法确定一个具体的数值。通过在OFDM系统中运用卷积编码和维特比译码仿真分析发现,维特比译码器反馈深度为卷积码编码器存贮长度的5倍时,既可达到性能和硬件复杂度的良好折衷,又便于实际应用。 相似文献
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Viterbi译码算法广泛应用于无线数字通信系统,一般采用比特对数似然信息(LLR)作为译码器的输入。针对M-FSK信号,该文提出一种采用信号解调得到的M维能量信息,直接作为译码器分支度量值,并给出了相应的Viterbi译码算法。在加性高斯白噪声(AWGN)和瑞利(Rayleigh)衰落信道下对所提算法的BER性能进行了理论推导,得到了闭合表达式。通过仿真验证了理论推导的正确性,与常规Viterbi算法相比,所提算法避免了比特LLR和分支度量值的计算,降低了算法复杂度和减少了信息损失,提高了M-FSK信号软解调Viterbi译码算法的BER性能,是一种更适用于工程实现的M-FSK信号的Viterbi译码算法。 相似文献
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Turbo均衡是一种通过反复均衡和信道译码来提高接收性能的迭代接收机算法。通常的Turbo均衡算法采用均衡与软输出译码的迭代运算,由于均衡和译码的重复计算,使得复杂度大大提高。文中提出了2种降低复杂度的Turbo均衡器:第一种采用软判决维特比译码,第二种采用软输入硬输出的维特比译码。通过仿真表明,这2种算法在几乎没有损失接收性能的情况下,大大降低了计算复杂度,并且第二种的性能要好于第一种。 相似文献
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This paper introduces an efficient iterative decoding method for high‐dimensional block turbo codes. To improve the decoding performance, we modified the soft decision Viterbi decoding algorithm, which is a trellis‐based method. The iteration number can be significantly reduced in the soft output decoding process by applying multiple usage of extrinsic reliability information from all available axes and appropriately normalizing them. Our simulation results reveal that the proposed decoding process needs only about 30% of the iterations required to obtain the same performance with the conventional method at a bit error rate range of 10?5 to 10?6. 相似文献
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In this paper, an adaptive decoding algorithm for convolutional codes, which is a modification of the Viterbi algorithm (VA) is presented. For a given code, the proposed algorithm yields nearly the same error performance as the VA while requiring a substantially smaller average number of computations. Unlike most of the other suboptimum algorithms, this algorithm is self-synchronizing. If the transmitted path is discarded, the adaptive Viterbi algorithm (AVA) can recover the state corresponding to the transmitted path after a few trellis depths. Using computer simulations over hard and soft 3-bit quantized additive white Gaussian noise channels, it is shown that codes with a constraint length K up to 11 can be used to improve the bit-error performance over the VA with K=7 while maintaining a similar average number of computations. Although a small variability of the computational effort is present with our algorithm, this variability is exponentially distributed, leading to a modest size of the input buffer and, hence, a small probability of overflow 相似文献
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Viterbi decoding is widely used in many radio systems. Because of the large computation complexity, it is usually implemented with ASIC chips, FPGA chips, or optimized hardware accelerators. With the rapid development of the multicore technology, multicore platforms become a reasonable choice for software radio (SR) systems. The Cell Broadband Engine processor is a state-of-art multi-core processor designed by Sony, Toshiba, and IBM. In this paper, we present a 64-state soft input Viterbi decoder for WiMAX SR Baseband system based on the Cell processor. With one Synergistic Processor Element (SPE) of a Cell Processor running at 3.2GHz, our Viterbi decoder can achieve the throughput up to 30Mb/s to decode the tail-biting convolutional code. The performance demonstrates that the proposed Viterbi decoding implementation is very efficient. Moreover, the Viterbi decoder can be easily integrated to the SR system and can provide a highly integrated SR solution. The optimization methodology in this module design can be extended to other modules on Cell platform. 相似文献
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A modified Viterbi (1971) algorithm for convolutional codes is described that provides for signal-to-noise ratio (SNR) adaptive computational effort. The algorithm has three levels of prioritized effort. Movement from one level to the next is controlled by parameters that can be selected according to desired output bit error rate performance. For 3-bit soft decision detected signals, a coding gain within 0.06 dB of Viterbi at a 3-dB SNR is achieved for the same constraint-length code with modest parameter values and computational effort. At values of SNR above 6 dB, the algorithm decodes with very low computational effort. Effort levels are controlled by spanning the decoding trellis in steps that are one constraint-length long 相似文献