Fault detection in combinational circuits using Gunn effect logic devices

It is shown that certain realisations of combinational switching functions using Gunn effect logic gates can be tested for single or multiple stuck-type faults by using two tests only. This result is achieved by exploiting the fact that the function of Gunn effect logic gates is sensitive to bias voltage     

Statistical timing analysis of combinational logic circuits

Efficient methods for computing an exact probability distribution of the delay of a combinational circuit, given probability distributions for the gate and wire delays, are developed. The derived distribution can give the probability that a combinational circuit will achieve a certain performance, across the possible range. This information can then be used to predict the expected performance of the entire circuit. The techniques presented target fast analysis as well as reduced memory requirements. The notion of a correct approximation, based on convex inequality, which never overestimates the percentage of circuits that will achieve any given performance is defined. It is shown that given the assumption that all the topologically longest paths are responsible for the delay, the computation technique provides a correct probabilistic measure in the sense given above. Methods are given to identify and to ignore false paths in the probabilistic analysis, so as to obtain correct and less pessimistic answers to the performance prediction question. Some practical results are given for a number of benchmark combinational circuits     

Exact reliability analysis of combinational logic circuits

A novel method is presented for the exact reliability analysis of combinational logic circuits. A model is developed that allows the logic circuit to be presented by a circuit equivalent graph (CEG). The reliability is analyzed by a systematic searching of certain subgraphs from the CEG. A computer algorithm and an example are given. The method gives the exact solution to the combinational logic circuit reliability-analysis problem. This is achieved by proper gate/circuit modeling, which allows the enumeration of all redundant fault vectors in a given circuit. Due to the concept of dominance among fault vectors, the number of necessary enumerations is appreciably reduced, and thus circuits with a few tens of gates can be efficiently analyzed     

Improving path delay testability of sequential circuits

We analyze the causes of low path delay fault coverage in synchronous sequential circuits and propose a method to improve testability. The three main reasons for low path delay fault coverage are found to be: (A) combinationally false (nonactivatable) paths; (B) sequentially nonactivatable paths; and (C) unobservable fault effects. Accordingly, we classify undetected faults in Groups A, B, and C. Combinationally false paths ran be made testable by modifying the circuit or resynthesizing the combinational logic as discussed by other researchers. A majority of the untestable faults are, however found in Group B, where a signal transition cannot be functionally propagated through a combinational path. A test requires two successive states necessary to create a signal transition and propagate it through the target path embedded in the sequential circuit. We study a partial scan technique in which flip-flops are scanned to break cycles and shun that a substantial increase in the coverage of path delay faults is possible     

Soft error generation analysis in combinational logic circuits

Reliability is expected to become a big concern in future deep sub-micron integrated circuits design.Soft error rate(SER) of combinational logic is considered to be a great reliability problem.Previous SER analysis and models indicated that glitch width has a great impact on electrical masking and latch window masking effects,but they failed to achieve enough insights.In this paper,an analytical glitch generation model is proposed.This model shows that after an inflexion point the collected charge has an...     

组合逻辑电路中的软错误（Soft Error）生成模型的分析

在深亚微米集成电路设计领域,电路可靠性问题日益严重。这个问题的一个重要方面是组合逻辑电路的软错误。现有的关于软错误率的分析和模型表明电压脉冲宽度对电气掩蔽（Electrical Masking）以及锁存窗掩蔽（Latch Window Masking）两种效应都有很大的影响。电压脉冲的宽度通过影响这两种效应进而决定了电路的软错误率。但是这些分析和模型在这个问题上不够深入。在这篇文章中,我们首次提出一个脉冲生成的解析模型。这个模型表明,越过一个拐点后,电路中由射线粒子注入的电荷量同电压脉冲宽度之间存在指数关系。这个模型的平均误差约为2.6%。这个模型还揭示了逻辑门延时与软错误率之间的折中关系。这个关系是最近的一篇有关组合逻辑电路软错误率降低方法的论文的基础[19]。     

BILCO: built in testing method for combinational logic circuits

The testing of digital logic circuits has become quite complex owing to miniaturisation and its associated increase in circuit function per unit area. Methods have been devised for testing ASIC products and, latterly, board level products. A new method (BILCO) is presented for probing asynchronous combinational logic circuits using a novel development of scan path principles     

Fast test generation and partial testing for combinational logic circuits

A simple, yet effective fast test generation algorithm by using the real value boolean difference is given for combinational logic circuits along with a short review of several fast test generation algorithms. Because no recursive operation is involved, it can be carried out as a parallel algorithm. In the second part of this paper, the concept of the partial testing is discussed. A new partial testing method, weighted point testing, is presented in this paper. Every line or node in the combinational logic circuit has a weight assigned to it. The weight at a point is determined by several factors, such as the fault occurrence found by experience or prior-knowledges, the number of fan-in or fan-out at that point, and the depth of the point in the circuit. Only those points with relatively high weights are considered in the test generation and testing. Because testing is more effectively done and directed to the point, the test coverage is higher.     

A new fault independent test generation algorithm for combinational logic circuits

In order to improve the performance of fault independent test generation algorithms, two strategies are proposed: a critical lines maximization strategy (CLM) and a critical primary inputs flipping strategy (CPF). CLM is used to maximize the number of detected faults while generating a test pattern. CPF is used to derive new test pattern(s) from a generated test pattern with little additional effort. A new fault independent test generation algorithm (MAX) based on these strategies is introduced and illustrated.     

Modeling and simulation of combinational CMOS logic circuits by ANFIS

In this paper, application of adaptive neuro-fuzzy inference system (ANFIS) in modeling of CMOS logic gates as a tool in designing and simulation of CMOS logic circuits is presented. Structures of the ANFIS are developed and trained in MATLAB 7.0.4 program. We have used real hardware data for training the ANFIS network. A hybrid learning algorithm consists of back-propagation and least-squares estimation is used for training. Influence of the structure of the proposed ANFIS model on accuracy and network performance has been analyzed through some combinational circuits. For the comparison of the ANFIS simulation results, we have simulated the circuits in HSPICE environment with 0.35 μm process nominal parameters. The comparison between ANFIS, HSPICE, and real hardware shows the feasibility and accuracy of the proposed ANFIS modeling procedure. The results show the proposed ANFIS simulation has much higher speed and accuracy in comparison with HSPICE simulation and it can be simply used in software tools for designing and simulation of complex CMOS logic circuits.     

Systematic synthesis of combinational circuits using multiplexers

An algorithmic procedure has been developed, suited to computer solution, for a switching function of n variables that can be synthesised by one multiplexer MUX(p, q), (n?q > l) without the necessity of referring to all the possible Ashenhurst's decomposition charts DCn(?q|?n?q).     

A method for automatic design error location and correction in combinational logic circuits

We present a new diagnostic algorithm, based on backward-propagation, for localising design errors in combinational logic circuits. Three hypotheses are considered, that cover all single gate replacement and insertion errors. Diagnosis-oriented test patterns are generated in order to rapidly reduce the suspected area where the error lies. The originality of our method is the use of patterns which do not detect the error, in addition to detecting patterns. A theorem shows that, in favourable cases, only two patterns suffice to get a correction. We have implemented the test generation and diagnosis algorithms. Results obtained on benchmarks show that the error is always found, after the application of a small number of test patterns, with an execution time proportional to the circuit size. This work is partially supported by EUREKA “JESSI-AC3” project and the ESPRIT Basic Research Action CHARME Working Group #6018.     

Constant testability of combinational cellular tree structures

This paper presents various approaches for testing cellular tree structures with a constant number of test vectors, that is, independent of the number of cells (size of the tree). The necessary and sufficient conditions which must be satisfied in the state table of a basic combinational cell for achieving C-testability and one-step C-testability in a homogeneous tree, are proved. The design modifications required to accomplish this objective in arbitrary cells, are discussed. It is proved that three additional rows and three additional columns are needed in the state table of a cell; the characteristics of the additional states are also analyzed. The complexity of the proposed testing process is quadratic with respect to the number of entries in the state table of a cell. Illustrative examples are also given.This research supported in part by grants from NATO and NSF.     

基于交通故障报警系统的组合逻辑电路的设计

用数字信号完成对数字量进行算术运算和逻辑运算的电路称为数字电路,可以分为组合逻辑电路和时序逻辑电路两大类.其中,组合逻辑电路是由最基本的逻辑门电路组合而成.文章以交通故障报警系统为例介绍了三种设计方案,以便学生熟悉常见组合逻辑电路的特点及应用.     

Diagnosis of logic circuits using compressed deterministic data and on-chip response comparison

While manufacturing test helps to isolate faulty devices from the good ones, diagnosis is enabling a faster transition from the yield learning to the volume production phase of a new process technology. Given the escalating design complexity, new methods such as embedded deterministic test have been proposed in recent years to deal with the cost of manufacturing test. This paper discusses diagnosis of logic blocks by leveraging the existing embedded deterministic test hardware. The proposed method is based on new techniques for on-chip decompression and comparison of incompletely specified test patterns and test responses. Using experimental data, the tradeoffs between the number of tester channels, on-chip area, and scan time are discussed.     

Exact probabilistic testability measures for multi-output circuits

The computation of probabilistic testability measures has become increasingly important and some methods have been proposed, although the exact solution of the problem is NP-hard. An exact analytical method for singleoutput combinational circuits is extended to deal with multi-output circuits. Such circuits are reduced to singleoutput ones by introducing a dummy gate, the X-gate, and applying to the resulting graph the analysis based on supergates.     

ATPG for combinational circuits on configurable hardware

In this paper, a new approach for generating test vectors that detects faults in combinational circuits is introduced. The approach is based on automatically designing a circuit which implements the D-algorithm, an automatic test pattern generation (ATPG) algorithm, specialized for the combinational circuit. Our approach exploits fine-grain parallelism by performing the following in three clock cycles: direct backward/forward implications, conflict checking, selecting next gate to propagate fault or to justify a line, decisions on gate inputs, and loading the state of the circuit after backup. In this paper, we show the feasibility of this approach in terms of hardware cost and speed and how it compares with software-based techniques     

Self-checking CMOS circuits using pass-transistor logic

This article presents a new approach to implementing self-checking circuits in CMOS technology. Implementations are made self-checking with respect to a single line stuck-at 0/1 fault. It is assumed that stuck faults at a common gate of neighboring PMOS and NMOS are not independent and the contact between a PMOS (NMOS) source and a power (ground) line is fault free. Self-checking error checkers for parity, two-rail code, and m-out-of-n code are designed using pass-transistor logic and then verified by fault simulation.     

Efficient reliability evaluation methodologies for combinational circuits

Reliability evaluation methodologies have become important in circuit design. In this paper, we focus on the probabilistic transfer matrix (PTM), which has proven to be a gate-level approach for accurately assess the reliability of a combinational circuit with penalty in simulation runtime and memory usage. In order to improve its efficiency, several methodologies based on traditional PTM are proposed. A general tool is developed to calculate the reliability of a circuit with efficient computation methods based on an optimized PTM (denoted as ECPTM), which achieves runtime and memory usage improvement. Experiments demonstrate how the proposed simulation framework, combined with traditional PTM method, can provide significant reduction in computation runtime and memory usage with different benchmark circuits.