SoC芯片STA的时钟约束问题研究

随着集成电路的飞速发展,芯片能否进行全面成功的静态时序分析已成为其保证是否能正常工作的关键.该文结合一款面向个人信息处理终端的SoC芯片探讨了静态时序分析（STA）流程中时钟约束的关键技术问题,对未来基于静态时序分析进行SoC芯片的优化设计有重要的参考价值.     

1.5Gbps高速串行数据恢复电路的标准单元实现

在高速串行接口芯片的设计中,高速串行数据恢复电路是设计中的一个难点,由于其高达千兆的传输频率,大多采用模拟电路方式实现·然而同数字电路相比,模拟电路在噪声影响、面积、功耗、工艺敏感度和可测性方面都存在较大的劣势·提出了一个应用于SATA1·0中1·5Gbps高速串行接口的高速串行数据恢复电路,它没有用PLL或DLL等模拟电路的方法,它采用完全数字电路的设计,并用标准单元实现·与用模拟电路实现的串行数据恢复电路相比,此电路设计更加简单易实现,数据恢复快速,而且面积小功耗低·电路被应用在PATA/SATA桥接芯片的设计中,并在标准0·18CMOS工艺下投片生产·     

基于静态代码分析的自动化对象行为协议提取工具

对象行为协议对于理解对象接口、正确实现模块集成以及类代码的复用都有着重要的意义.在前期工作中,提出了一种基于静态源代码分析的对象行为协议自动提取方法.该方法通过源代码分析获取对象(类)内部各接口方法之间直接和间接的依赖关系,然后在对象(类)内部依赖关系的基础上构建接口的状态机图.在此基础上,进一步介绍相应的支持工具,包括主要模块、各部分的主要实现技术等.     

Interactive design of 3D models with geometric constraints

In this paper, an interactive graphical approach for the design of parameterized part-hierarchies is presented. Primitive solids can be grouped into compound objects, and multiple instances of a compound object can be used in further designs. Geometric relations between primitives and instances are specified by geometric constraints between their local coordinate systems. The user can specify and edit a model by direct manipulation on a perspective or parallel projection with a mouse, whereas a procedural model representations is automatically generated via visual programming. The obtained twoview approach offers two concurrent interface styles to the end-user and enables the combination of an intuitive direct manipulation interface with the expressiveness of a procedural modeling language.     

时间限制协议一致性测试新模型研究

原有的时间限制协议一致性测试模型TCFSM不适合实时协议的一致性测试。在TCFSM的基础上,引入新变量重新定义时间限制而得到新模型TCFSM-N,通过把进程中的消息处理时间与消息在信道中的传送时间分离开来,并使进程改变状态的时间可由进程明确测量,以及使时钟与定时器达到完全同步等一系列改进措施,使得新模型TCFSM-N完全适合于实时协议的一致性测试。     

Low power DCVSL circuits employing AC power supply

In view of changing the type of energy conversion in CMOS circuits, this paper investigates low power CMOS circuit design, which adopts a gradually changing power clock. First, we discuss the algebraic expressions and the corresponding properties of clocked power signals. Then the design procedure is summed up for converting complementary CMOS logic gates employing DC power to the power-clocked CMOS gates employing AC power. On this basis, the design of differential cas-code voltage switch logic (DCVSL) circuits employing AC power clocks is proposed. The PSPICE simulations using a sinusoidal power-clock demonstrate that the designed power-clocked DCVSL circuit has a correct logic function and low power characteristics. Finally, an interface circuit to convert clocked signals into the standard logic levels of a CMOS circuit is proposed, and its validity is verified by computer simulations.     

多FPGA设计的时钟同步

在多FPGA设计中,时钟信号的传输延时造成了FPGA间的大时钟偏差,进而制约系统性能。为减少时钟偏差,该文提出一种多数字延迟锁相环(DLL)电路。该电路将时钟的传输电路放入DLL的反馈环路。利用DLL的延迟锁定特性,对FPGA间的时钟传输延时进行补偿,减少FPGA间的时钟偏差,解决多FPGA的时钟同步问题。     

应用于片上系统中低功耗IP核设计的自适应门控时钟技术

门控时钟技术一直以来是降低芯片动态功耗的有效方法.文章结合片上系统(SoC)的结构特性和设计特点,分析已有的各种门控时钟技术的优缺点,指出这些缺点是SoC设计中的严重障碍,随后抽象出IP核工作模型,提出了仅用非常简单的逻辑就可以方便应用于IP核的自适应门控时钟技术.这种技术在不影响性能的前提下,可以根据IP核的应用状况自动开关时钟,不但可以降低动态功耗,还可以结合门控电源技术降低漏电功耗.对一款真实SoC中浮点IP核的改造实验表明,在不降低性能的前提下,可以平均降低62.2%的动态功耗,同时理论上平均降低70.9%的漏电功耗.     

异步FIFO的模型检验方法

跨时钟域(Clock Domain Crossing,CDC)设计和验证是SOC系统芯片设计的关键问题。讨论了异步FIFO的模型检验方法,利用模型检验工具SMV,建立了异步FIFO的有限状态机模型,使用时序逻辑LTL对该模型和属性进行了描述和验证。实验结果达到要求,同时表明该方法是行之有效的。与传统的模拟和仿真等验证方法相比较,模型检验具有能够自动进行、验证速度快、不用书写测试激励等优点。     

Optically injected logic circuits for remote-powered systems on a chip

This paper reviews the concept of optically injected logic circuits and investigates their implementation in nanometer CMOS technologies. Optically injected circuits are powered via an optical beam, i.e. they do not require a local power supply and distribution network. A complete set of digital cells has been designed and simulated, and key building blocks of the logic family have been fabricated and tested in a standard 180 nm CMOS technology. The paper also discusses the design and implementation of optically injected circuits for clock distribution, input/output, analog-to-digital and digital-to-analog conversion. All these circuits are immediately applicable in wireless biomedical implants or contactless smart cards. They can also be used in other systems-on-chip (SoC), in which very low power operation can be replaced by remote-powered operation.     

ScanBist: a multifrequency scan-based BIST method

The authors present ScanBist, a low-overhead, scan-based built-in self-test method, along with its performance in several designs. A novel clock synchronization scheme allows at-speed testing of circuits. This design allows the testing of circuits operating at more than one frequency while retaining the combinational character of the circuit to be analyzed. We can therefore apply scan patterns that will exercise the circuit under test at the system speed, potentially providing a better coverage of delay faults when compared to other self-test methods. Modifications to an existing transition fault simulator account for cases where inputs originating from scan registers clocked at different frequencies drive a gate. We claim to detect transition faults only if the transition originates from the inputs driven by the highest frequency clock. ScanBist is useful at all levels of system packaging assuming that a standard TAP provides the control and boundary scan isolates the circuit from primary inputs and outputs during BIST mode     

Performance Evaluation of Elastic GALS Interfaces and Network Fabric

This paper reports on the design of a test chip built to test a) a new latency insensitive network fabric protocol and circuits, b) a new synchronizer design, and c) how efficiently one can synchronize into a clocked domain when elastic interfaces are utilized. Simulations show that the latency insensitive network allows excellent characterization of network performance in terms of the cost of routing, amount of blocking due to congestion, and message buffering. The network routers show that peak performance near 100% link utilization is achieved under congestion and combining. This enables accurate high-level modeling of the behavior of the network fabric so that optimized network design, including placement and routing, can occur through high-level network synthesis tools. The chip also shows that when elastic interfaces are used at the boundary of clock synchronization points then efficient domain crossings can occur. Buffering at the synchronization points are required to allow for variability in clocking frequencies and correct data transmission. The asynchronous buffering and synchronization scheme is shown to perform over four times faster than the clocked interface.     

基于层次平台的安全SoC设计技术

在基于层次平台的SoC设计方法学基础上,文中提出了安全SoC设计关键技术,主要包括基于可信计算体系结构的安全SoC层次化设计平台、在安全SoC设计中引入独立的安全约束及安全约束映射技术以及安全验证技术。从软件攻击、旁路攻击和物理攻击等角度,定义安全约束并验证防护技术的有效性。文中给出的安全SoC设计技术不仅可以充分重用已有的设计资源,也可充分利用现有的层次平台设计技术及相关辅助设计工具。     

Secure and self-stabilizing clock synchronization in sensor networks

In sensor networks, correct clocks have arbitrary starting offsets and nondeterministic fluctuating skews. We consider an adversary that aims at tampering with the clock synchronization by intercepting messages, replaying intercepted messages (after the adversary’s choice of delay), and capturing nodes (i.e., revealing their secret keys and impersonating them). We present an efficient clock sampling algorithm which tolerates attacks by this adversary, collisions, a bounded amount of losses due to ambient noise, and a bounded number of captured nodes that can jam, intercept, and send fake messages. The algorithm is self-stabilizing, so if these bounds are temporarily violated, the system can efficiently stabilize back to a correct state. Using this clock sampling algorithm, we construct the first self-stabilizing algorithm for secure clock synchronization in sensor networks that is resilient to the aforementioned adversarial attacks.     

延迟优化的片上网络低功耗映射*

片上网络（NoC）是解决传统基于总线的片上系统（SoC）所面临的功耗、延迟、同步和信号完整性等挑战的有效解决方案。功耗和延迟是NoC设计中的重要约束和性能指标,在设计的各个阶段都存在着优化空间。基于蚁群优化算法,通过通信链路上并发通信事件的均匀分布来降低NoC映射阶段的功耗和延迟。仿真实验表明,与链路通信量负载均衡的方法相比,该方案能进一步在拓扑映射阶段优化功耗和延迟。     

A Survey and Taxonomy of GALS Design Styles

Single-clocked digital systems are largely a thing of the past. Although most digital circuits remain synchronous, many designs feature multiple clock domains, often running at different frequencies. Using an asynchronous interconnect decouples the timing issues for the separate blocks. Systems employing such schemes are called globally asynchronous, locally synchronous (GALS). To minimize time to market, large SoC designs must integrate many functional blocks with minimal design effort. These blocks are usually designed using standard synchronous methods and often have different clocking requirements. A GALS approach can facilitate fast block reuse by providing wrapper circuits to handle interblock communication across clock domain boundaries. SoCs may also achieve power savings by clocking different blocks at their minimum speeds. For example, Scott et al. describe the advantages of GALS design for an embedded-processor peripheral bus.     

基于对象的分布式实时系统调度模型研究

为了解决分布式实时系统有关分配和调度等问题，给出并用形式化方法描述了一种基于对象分布式实时系统调度的通用模型。该模型包括表示时限的绝对时间约束，表示周期属性的周期约束，表示各种前趋关系和同步要求的相对时间约束以及保证资源使用一致性的一致性约束，此外该模型克服了以往模型不能在应用系统的逻辑和功能部件上描述系统实时的约束的不足，允许从方法和活动上描述所需的约束，降低了单一约束描述的繁杂程度，为了能够使用现有调度算法进行任务调度，讨论了约束转换的问题，给出了高层约束到底层约束的转换规则和相应的转换算法。     

Reconciling fault-tolerant distributed computing and systems-on-chip

Classic distributed computing abstractions do not match well the reality of digital logic gates, which are the elementary building blocks of Systems-on-Chip (SoCs) and other Very Large Scale Integrated (VLSI) circuits: Massively concurrent, continuous computations undermine the concept of sequential processes executing sequences of atomic zero-time computing steps, and very limited computational resources at gate-level make even simple operations prohibitively costly. In this paper, we introduce a modeling and analysis framework based on continuous computations and zero-bit message channels, and employ this framework for the correctness & performance analysis of a distributed fault-tolerant clocking approach for Systems-on-Chip (SoCs). Starting out from a “classic” distributed Byzantine fault-tolerant tick generation algorithm, we show how to adapt it for direct implementation in clockless digital logic, and rigorously prove its correctness and derive analytic expressions for worst case performance metrics like synchronization precision and clock frequency. Rather than on absolute delay values, both the algorithm’s correctness and the achievable synchronization precision depend solely on the ratio of certain path delays. Since these ratios can be mapped directly to placement & routing constraints, there is typically no need for changing the algorithm when migrating to a faster implementation technology and/or when using a slightly different layout in an SoC.     

Verification of clock synchronization algorithms: experiments on a combination of deductive tools

We report on an experiment in combining the theorem prover Isabelle with automatic first-order arithmetic provers to increase automation on the verification of distributed protocols. As a case study for the experiment we verify several averaging clock synchronization algorithms. We present a formalization of Schneider’s generalized clock synchronization protocol [Sch87] in Isabelle/HOL. Then, we verify that the convergence functions used in two clock synchronization algorithms, namely, the Interactive Convergence Algorithm (ICA) of Lamport and Melliar-Smith [LMS85] and the Fault-tolerant Midpoint algorithm of Lundelius–Lynch [LL84], satisfy Schneider’s general conditions for correctness. The proofs are completely formalized in Isabelle/HOL. We identify parts of the proofs which are not fully automatically proven by Isabelle built-in tactics and show that these proofs can be handled by automatic first-order provers with support for arithmetics.