A 5.25-GHz image rejection RF front-End Receiver With Polyphase filters

A 5.25-GHz image rejection (IR) radio frequency (RF) front-end receiver is proposed, which is implemented in 0.18-/spl mu/m CMOS technology. The proposed receiver adopts both a high-intermediate frequency (IF) and the double quadrature architecture to achieve high IR at 5-GHz frequency. The measured results show a power gain of 14 dB, a minimum noise figure of 7.9dB, and IIP3 of -8dBm. The measured maximum image rejection ratio is 45dBc. The receiver consumes a total of 32mA from a 1.8-V supply.     

Design of an L1 band low noise single-chip GPS receiver in 0.18 μm CMOS technology

This article presents an L1 band low noise integrated global positioning system(GPS)receiver chip using 0.18 μm CMOS technology.Dual-conversion with a low-IF architecture was used for this GPS receiver.The receiver is composed of low noise amplifier(LNA),down-conversion mixers,band pass filter,received signal strength indicator,variable gain amplifier,programmable gain amplifier,ADC,PLL frequency synthesizer and other key blocks.The receiver achieves a maximum gain of 105 dB and noise figure less than 6 dB.The variable gain amplifier(VGA)and programmable gain amplifier(PGA)provide gain control dynamic range over 50 dB.The receiver consumes less than 160 mW from a 1.8 V supply while occupying a 2.9 mm2chip area including the ESD I/O pads.     

A low-power 2.4-GHz transmitter/receiver CMOS IC

A 2.4-GHz CMOS receiver/transmitter incorporates circuit stacking and noninvasive baseband filtering to achieve a high sensitivity with low power dissipation. Using a single 1.6-GHz local oscillator, the transceiver employs two upconversion and downconversion stages while providing on-chip image rejection filtering. Realized in a 0.25-/spl mu/m digital CMOS technology, the receiver exhibits a noise figure of 6 dB and consumes 17.5 mW from a 2.5-V supply, and the transmitter delivers an output power of 0 dBm with a power consumption of 16 mW.     

L波段数字声广播接收机CMOS集成模拟前端

本文设计了使用CMOS工艺,单片集成的L波段数字声广播(DAB)接收机模拟前端.接收机前端应用了三种方法来提高镜像抑制度:低中频双正交weaver结构比一般的同相/正交(I/Q)两路下变频结构具有更高的镜像抑制能力;镜像抑制低噪声放大器(LNA)提供了额外的镜像信号抑制;具有相位和幅度校正功能的本振驱动器提供了更精确的正交本振信号.仿真显示接收机前端对镜像信号的抑制超过65dB,其级联噪声指数为4dB,输出三阶交调指数为22dBm.接收机前端使用TSMC 0.25μm CMOS工艺制作,版图核心面积为9mm²,目前正在测试中.     

0.5-V 5.6-GHz CMOS Receiver Subsystem

The building blocks of a 0.5-V receiver, including a receiver front-end and a low-pass filter (LPF), are fabricated using 0.18- $mu{hbox{m}}$ CMOS technology. At 5.6 GHz, the receiver front-end achieves a voltage gain of 17.1 dB and a noise figure of 8.7 dB, while dissipating at 19.4 mW. The fifth-order low-pass Chebyshev filter achieves a corner frequency of 2.6 MHz and an input-referred noise of 28.5 nV/sqrt (Hz) at 6.8 mW. The receiver front-end is further integrated with the LPFs to form a highly integrated receiver subsystem at ultra-low voltage.      

A 19-mW 2.6-mm/sup 2/ L1/L2 dual-band CMOS GPS receiver

This paper presents the design and implementation of an L1/L2 dual-band global positioning system (GPS) receiver. Dual-conversion with a low-IF architecture was used for dual-band operation. The receiver is composed of an RF preamplifier, down-conversion mixers, a variable-gain channel filter, a 2-bit analog-to-digital converter, and the full phase-locked-loop synthesizer including an on-chip voltage controlled oscillator. Fabricated in a 0.18-/spl mu/m CMOS technology, the receiver exhibits maximum gain of 95 dB and noise figures of 8.5 and 7.5 dB for L1 and L2, respectively. An on-chip variable-gain channel filter provides IF image rejection of 20 dB and gain control range over 60 dB. The receiver consumes 19 mW from a 1.8-V supply while occupying a 2.6-mm/sup 2/ die area including the ESD I/O pads.     

A fully integrated 900-MHz CMOS wireless receiver with on-chip RF and IF filters and 79-dB image rejection

A monolithic 900-MHz CMOS wireless receiver with on-chip RF and IF filters and a fully integrated fractional-N synthesizer is presented. Implemented in a standard 0.5-/spl mu/m CMOS process and without any off-chip component, the complete receiver has a measured image rejection of 79 dB, a sensitivity of -90 dBm, an IIP3 of -24 dBm, and a noise figure of 22 dB with a power of 227 mW and a chip area of 5.7 mm/sup 2/. The synthesizer achieves a phase noise of -118 dBc/Hz at 600 kHz offset and a settling time of less than 150 /spl mu/s.     

S波段雷达接收机前端低噪声放大器

采用0.35μm SiGe BiCMOS工艺设计了用于S波段雷达接收机前端电路的低噪声放大器。对于现代无线接收机来说,其动态范围和灵敏度很大程度上都取决于低噪声放大器的噪声性能和线性度。相对于CMOS工艺来说,SiGe BiCMOS工艺具有更高的截止频率、更好的噪声性能和更高的电流增益,非常适合微波集成电路的设计。该低噪声放大器采用三级放大器级联的结构以满足高达30dB的增益要求。在5V的电源电压下,满足绝对稳定条件,在3GHz-3.5GHz频段内,功率增益为34.5dB,噪声系数为1.5dB,输出1dB功率压缩点为11dBm。     

Dual-band RF receiver for GPS-L1 and compass-B1 in a 55-nm CMOS

A fully integrated dual-band RF receiver with a low-IF architecture is designed and implemented for GPS-L 1 and Compass-Bl in a 55-nm CMOS process. The receiver incorporates two independent IF channels with 2 or 4 MHz bandwidth to receive dual-band signals around 1.57 GHz respectively. By implementing a flexible frequency plan, the RF front-end and frequency synthesizer are shared for the dual-band operation to save power consumption and chip area, as well as avoiding LO crosstalk. A digital automatic gain control （AGC） loop is utilized to improve the receiver＇s robustness by optimizing the conversion gain of the analog-to-digital converter （ADC）. While drawing about 20 mA per channel from a 1.2 V supply, this RF receiver achieves a minimum noise figure （NF） of about 1.8 dB, an image rejection （IMR） of more than 35 dB, a maximum voltage gain of about 122 dB, a gain dynamic range of 82 dB, and an maximum input-referred 1 dB compression point of about -36.5 dBm with an active die area of 1.5 × 1.4 mm2 for the whole chip.     

A New Transceiver Architecture for the 60-GHz Band

A new “half-RF” architecture incorporates a polyphase filter in the signal path to allow the use of a local oscillator frequency equal to half the input frequency. The receiver performs 90 $^{circ}$ phase shift and two downconversion steps to produce quadrature baseband outputs. The transmitter upconverts the quadrature baseband signals in two steps, applies the results to a polyphase filter, and sums its outputs. Each path employs a dedicated 30-GHz oscillator and is fabricated in 90-nm CMOS technology. The receiver achieves a noise figure of 5.7–7.1 dB and gain/phase mismatch of 1.1 dB/2.1$^{circ}$ while consuming 36 mW. The transmitter produces a maximum output level of $-$7.2 dBm and an image rejection of 20 dB while drawing 78 mW.      

A 900-MHz dual-conversion low-IF GSM receiver in 0.35-μm CMOS

A low-power fully integrated GSM receiver is developed in 0.35-μm CMOS. This receiver uses dual conversion with a low IF of 140 kHz. This arrangement lessens the impact of the flicker noise. The first IF of 190 MHz best tolerates blocking signals. The receiver includes all of the circuits for analog channel selection, image rejection, and more than 100-dB controllable gain. The receiver alone consumes 22 mA from a 2.5-V supply, to give a noise figure of 5 dB, and input IP3 of -16 dBm. A single frequency synthesizer generates both LO frequencies. The integrated VCO with on-chip resonator and buffers consume another 8 mA, and meets GSM phase-noise specifications     

一种用于卫星导航接收机的低噪声放大器设计

设计了一种可用于多模式卫星导航接收机的射频前端低噪声放大器,设计电路可在1.13～1.95 GHz工作,兼容了GPS,北斗及GLONOSS导航系统的工作频段。电路采用0.18 μm CMOS工艺实现。仿真结果表明,频带内S11和S22均在-10 dB以下,功率增益＞10 dB,带内最小噪声系数可达到2.2 dB,输出1 dB压缩点为-5.585 dBm,在1.8 V电源电压下,主体电路消耗12 mA电流。因此,该低频噪声放大器模块可满足当前各种导航系统的工作要求。     

A crystal-tolerant fully integrated CMOS low-IF dual-band GPS receiver

This paper presents the design of a dual-band L1/L2 GPS receiver, that can be easily integrated in portable devices (mainly GSM mobile phones). For the ease of integration with GSM wireless systems the receiver can tolerate most of the common GSM crystals, besides the GPS crystals, this will eliminate the need to use another crystal on board. A new frequency plan is presented to satisfy this requirement. A low-IF receiver architecture is used for dual-band operation with analog on-chip image rejection. The receiver is composed of a narrow-band LNA for each band, dual down-conversion mixers, a variable-gain channel filter, a 2-bit analog-to-digital converter, and a fully integrated frequency synthesizer including an on-chip VCO and loop filter. The complex filter can accept IF frequency variation of 10% around 4.092 MHz which allows the use of the commonly used 10/13/26 MHz GSM crystals and all the GPS crystals. The synthesizer generates the LO signals for both L1/L2 bands with an average phase noise of −95 dBc/Hz. The receiver exhibits maximum gain of 112 and 115 dB, noise figures of 4 and 3.6 dB, and input compression points of −76 and −79 dBm for L1 and L2, respectively. An on-chip variable-gain channel filter provides IF image rejection greater than 25 dB and gain control range over 80 dB. The receiver is designed in 0.13 μm CMOS technology and consumes 18 mW from a 1.2-V supply.     

A monolithic, standard CMOS, fully differential optical receiver with an integrated MSM photodetector

This paper presents a realization of a silicon-based standard CMOS, fully differential optoelectronic inte grated receiver based on a metal-semiconductor-metal light detector (MSM photodetector). In the optical receiver, two MSM photodetectors are integrated to convert the incident light signal into a pair of fully differential photo generated currents. The optoelectronic integrated receiver was designed and implemented in a chartered 0.35 μm, 3.3 V standard CMOS process. For 850 nm wavelength, it achieves a 1 GHz 3 dB bandwidth due to the MSM pho todetector's low capacitance and high intrinsic bandwidth. In addition, it has a transimpedance gain of 98.75 dBΩ, and an equivalent input integrated referred noise current of 283 nA from 1 Hz up to -3 dB frequency.     

A low power 3-5 GHz CMOS UWB receiver front-end

A novel low power RF receiver front-end for 3-5 GHz UWB is presented. Designed in the 0.13μm CMOS process, the direct conversion receiver features a wideband balun-coupled noise cancelling transconductance input stage, followed by quadrature passive mixers and transimpedance loading amplifiers. Measurement results show that the receiver achieves an input return loss below-8.5 dB across the 3.1-4.7 GHz frequency range, max-imum voltage conversion gain of 27 dB, minimum noise figure of 4 dB, IIP3 of-11.5 dBm, and IIP2 of 33 dBm. Working under 1.2 V supply voltage, the receiver consumes total current of 18 mA including 10 mA by on-chip quadrature LO signal generation and buffer circuits. The chip area with pads is 1.1 × 1.5 mm2.     

A 1.9-GHz silicon receiver with monolithic image filtering

A 1.9-GHz fully monolithic silicon superheterodyne receiver front-end is presented; it consists of a low noise amplifier (LNA), a tunable image reject filter, and a Gilbert cell mixer integrated in one die. The receiver was designed to operate with a 1.9-GHz RF and a 2.2-GHz local oscillator (LO) for a 300-MHz IF. Two chip versions were fabricated on two different fabrication runs using a 0.5-μm bipolar technology with 25 GHz transit frequency (f_T). Measured performance for the receiver front-end version 1, packaged and without input matching, was: conversion gain 33.5 dB, noise figure 4.9 dB, input IP3 -28 dBm, image rejection 53 dB (tuned to reject a 2.5-GHz image frequency), and 15.9 mA current consumption at +3 V. The image rejection was tunable from 2.4-2.63 GHz by means of an on-chip varactor. Version 2 had increased mixer degeneration for improved linearity. Its measured performance for the packaged receiver with its input matched to 50 Ω was: conversion gain 24 dB, noise figure 4.8 dB, input IP3 -19 dBm, and 65 dB image rejection for a 2.5-GHz image with an image tuning range from 2.34-2.55 GHz     

用于IEEE802．11b／g WLAN直接下变频接收机的射频前端设计

介绍了一种应用于IEEE802．11b／g无线局域网接收机射频前端的设计。基于直接下变频的系统架构。接收机集成了低噪声放大器、I／Q下变频器、去直流偏移滤波器、基带放大器和信道选择滤波器。电路采用TSMC0．18μm CMOS工艺设计,工作在2．4GHz ISM（工业、科学和医疗）频段,实现的低噪声放大器噪声系数为0．84dB,增益为16dB,S11低于-15dB,功耗为13mW;I／Q下变频器电压增益为2dB,输入1dB压缩点为-1 dBm,噪声系数为13dB,功耗低于10mw。整个接收机射频前端仿真得到的噪声系数为3．5dB,IIP3为-8dBm,IP2大于30dBm,电压增益为31dB,功耗为32mW。     

3-D Integration of 10-GHz Filter and CMOS Receiver Front-End

A 10-GHz filter/receiver module is implemented in a novel 3-D integration technique suitable for RF and microwave circuits. The receiver designed and fabricated in a commercial 0.18-mum CMOS process is integrated with embedded passive components fabricated on a high-resistivity Si substrate using a recently developed self-aligned wafer-level integration technology. Integration with the filter is achieved through bonding a high-Q evanescent-mode cavity filter onto the silicon wafer using screen printable conductive epoxy. With adjustment of the input matching of the receiver integrated circuit by the embedded passives fabricated on the Si substrate, the return loss, conversion gain, and noise figure of the front-end receiver are improved. At RF frequency of 10.3 GHz and with an IF frequency of 50 MHz, the integrated front-end system achieves a conversion gain of 19 dB, and an overall noise figure of 10 dB. A fully integrated filter/receiver on an Si substrate that operates at microwave frequencies is demonstrated.     

A Millimeter-Wave CMOS Heterodyne Receiver With On-Chip LO and Divider

A heterodyne receiver performs frequency down-conversion in two steps to relax oscillator and divider speed requirements. The receiver incorporates new concepts such as a current-domain quadrature separation method, a broadband Miller divider based on a passive mixer, and an inductor nesting technique that significantly reduces the length of high-frequency interconnects. Fabricated in 90-nm CMOS technology, the circuit achieves a noise figure of 6.9 to 8.3 dB from 49 GHz to 53 GHz with a gain of 26 to 31.5 dB and I/Q mismatch of 1.6 dB/6.5deg.     

低功耗IR-UWB接收机和LNA设计研究

在分析各种超宽带(UWB)接收机系统结构的基础上,提出了一种低功耗IR-UWB接收机结构.该结构基于非相干通信机制,使用自混频技术和脉冲宽度调制方式(PPM).在该结构中,低噪声放大器(LNA)的低功耗优化是系统低功耗实现的关键.综合分析各种宽带LNA结构,提出了一种低功耗LNA设计.该LNA采用65 nmCMOS标准...