Schottky-barrier source/drain MOSFETs on ultrathin SOI body with a tungsten metallic midgap gate

This letter presents a simple low-temperature process to fabricate Schottky-barrier (SB) MOSFETs that integrates a midgap metallic gate (tungsten). The device architecture is based on a thin (10 nm) and lowly doped silicon-on-insulator film that provides a threshold voltage of -0.3 V independent on the depletion charge and therefore not sensitive to variations in film thickness and doping. A gate encapsulation technique using an SiO/sub 2/-like hydrogen silsesquioxane capping layer features 15-nm-wide spacers and ensures the compatibility with the PtSi self-aligned silicide process. Long-channel devices present an ideal subthreshold swing of 60 mV/dec, over six decades of I/sub on//I/sub off/ without any sign of sublinear upward bending of the I/sub DS/--V/sub DS/ curves at low drain voltage.     

Design of enhanced Schottky-barrier AlGaAs/GaAs MODFET's using highly doped p+surface layers

The design and performance of enhanced Schottky-barrier height modulation-doped AlGaAs/GaAs field-effect transistors (ESMODFET's) is discussed. Results are presented showing that the addition of a thin highly doped p⁺layer under the gate can increase the forward biased gate turn-on voltage from 0.8 V (conventional MODFET) to as high as 1.6 V. A mathematical model is presented that predicts the thickness and doping of the heterostructure layers required to obtain a given threshold voltage and effective Schottky-barrier height. It is predicted that this enhanced Schottky barrier will allow increased gate-voltage swings and thus significantly improve the noise margin of enhancement-mode MODFET circuits.     

Low temperature processed mosfet's using laser recrystallized polycrystalline silicon films

An n-channel MOS transistor was fabricated on a laser recrystallized polycrystalline silicon film at temperatures below 630°C. The gate oxide was sputter deposited at 200°C. Lasers were used for substrate recrystallization, implantation damage annealing and dopant drive-in. An electron field effect mobility higher than 100 cm²/V · sec. was observed on the finished transistors. With 10 V applied to the gate of the transistors for 2 hr, less than a 20 mV shift in threshold voltage was observed.     

Minimum-size effects in asymmetric tilt-angle-implantedLDD-WNx-GaAs MESFET's

Asymmetric tilt-angle-implanted lightly doped drain (LDD)-WN_x -GaAs MESFETs with an optimized transconductance performance are discussed. A tilt-angle implantation is used to reduce the parasitic source resistance below the gate sidewall without increasing short- and narrow-channel effects. This leads to a transconductance increase of nearly 25% for submicrometer FETs while the gate-source capacitance increase is almost negligible. The influence of the implantation angle on the threshold voltage transconductance, and Schottky-barrier characteristics is reported     

High-speed Schottky-barrier pMOSFET with f/sub T/=280 GHz

High-speed results on sub-30-nm gate length pMOSFETs with platinum silicide Schottky-barrier source and drain are reported. With inherently low series resistance and high drive current, these deeply scaled transistors are promising for high-speed analog applications. The fabrication process simplicity is compelling with no implants required. A sub-30-nm gate length pMOSFET exhibited a cutoff frequency of 280 GHz, which is the highest reported to date for a silicon MOS transistor. Off-state leakage current can be easily controlled by augmenting the Schottky barrier height with an optional blanket As implant. Using this approach, good digital performance was also demonstrated.     

Dual-polycide gate technology using regrowth amorphous-Si tosuppress lateral dopant diffusion

Process techniques for dual-polycide gate CMOS have been developed. The origin of lateral dopant diffusion is analyzed, and an enlarged-grain dual-polycide gate technology using regrowth amorphous-Si (a-Si) is proposed. Reduction of the dopant absorption into the silicide layer has been observed in the regrowth of a-Si polycide gate structure. Lateral dopant diffusion has been suppressed to less than 0.1 μm, and, as a result, 0.2 μm n-MOS/p-MOS spacing has been realized under an 850°C furnace annealing process. This technology can also achieve current drivability improvement by suppressing the gate depletion simultaneously. Suppression of boron penetration through the gate oxide to the channel region from the p⁺ gate has been realized by gate doping ion implantation into the a-Si, and no threshold voltage lowering with small standard deviation has been confirmed. It has been recognized that the above techniques are a possible solution for the dual-polycide gate CMOS structure     

NBTI and hot carrier effect of Schottky-barrier p-MOSFETs

The experimental investigation of NBTI and hot carrier induced device degradation in Pt-silicided Schottky-barrier p-MOSFETs has been performed. The investigations on the threshold voltage shifts, the degradation of inverse subthreshold slope, and the decrease of I_ON/I_OFF ratio have been carried out using the modulation of Schottky-barrier height and width. After NBTI and hot carrier stress, the decrease of I_ON could be explained by the lower hole tunneling current through the more increased Schottky-barrier height and the increased I_OFF could be explained by the increase of the amount of electron thermal emission and tunneling through thinner Schottky-barrier into the near drain. After hot carrier stress, it is observed that the threshold voltage shifts to more negative values for all stress gate voltages and the drain current is decreased. The device degradation is more significant as the stress gate voltage decreases.     

Effect of arsenic implantation on electrical characteristics ofLPCVD WSi2/n-Si Schottky contacts

Electrical characteristics of As-implanted low-pressure chemical vapor deposition (LPCVD) WSi₂/n-Si Schottky barriers are reported. It is shown that As implantation results in a significant Schottky-barrier lowering and an increase in the diode ideality factor n. Silicide annealing prior to As implantation is more effective in reducing Schottky-barrier height. Nearly ohmic characteristics were obtained for As-implanted LPCVD WSi₂ Schottky barriers. Arsenic implanted into high-temperature annealed silicide films was more effective in reducing the effective Schottky-barrier height. Detailed SIMS analysis indicated higher As concentration at the silicide/silicon interface when implanted into high-temperature-annealed silicide films     

标准氟离子注入实现增强型GaN基功率器件

介绍了一种直接利用离子注入机对AlGaN/GaN高电子迁移率晶体管(HEMT)器件的栅下进行氟(F)离子注入的方法,成功实现了增强型HEMT器件,阈值电压从耗尽型器件的-2.6V移动到增强型器件的+1.9V.研究了注入剂量对器件性能的影响,研究发现随着注入剂量的不断增加,阈值电压不断地正向移动,但由于存在高能F离子的注入损伤,器件的正向栅极漏电随着注入剂量的增加而不断上升,阈值电压正向移动也趋于饱和.因此,提出采用在AlGaN/GaN异质结表面沉积栅介质充当能量吸收层,降低离子注入过程中的损伤,成功实现了阈值电压为+3.3 V,饱和电流密度约为200 mA/mm,同时具有一个较高的开关比109的增强型金属-绝缘层-半导体HEMT (MIS-HEMT)器件.     

Threshold voltage adjustable process for self-aligned gate GaAs JFET

A self-aligned GaAs JFET process, allowing threshold voltage adjustment after gate metallisation, has been developed. Zn-doped tungsten silicide was used as the gate metallisation, which also acts as the source of Zn diffusion for the p-junction gate. The threshold voltage was adjusted by repeated short thermal pulses in a lamp annealer at 550°C. The process has the potential to solve the most difficult task of threshold voltage control necessary for achieving high yield in LSI fabrication.     

A possible scaling limit for enhancement-mode GaAs MESFETs in DCFLcircuits

A possible scaling limit for ion-implanted GaAs MESFETs with buried p-layer LDD structure has been numerically investigated. A Schottky-contact model with a thin interfacial layer and interface states was used to simulate the Schottky-barrier height of a scaled-down MESFETs. When enhancement-mode MESFETs in direct-coupled FET logic (DCFL) circuits are scaled down, the gate length can be reduced to 0.21 μm at an interface-state density of 6.6×10¹² cm^-2·eV^-1, when the barrier height is greater than 0.6 V, the threshold voltage is less than 0.1 V, and the channel aspect ratio is 8     

Improvement of electron emission efficiency and stability bysurface application of molybdenum silicide onto gated poly-Si fieldemitters

As an approach to improve electron field emission and its stability, molybdenum (Mo) silicide formation on n⁺ polycrystalline silicon (poly-Si) emitters has been investigated. Mo silicide was produced by direct metallurgical reaction, namely, deposition of Mo and subsequent rapid thermal annealing. The surface morphologies and emission properties of Mo-silicided poly-Si (Mo-polycide) emitters have been examined and compared with those of poly-Si emitters. While anode current of 0.1 μA per tip could be obtained at the gate voltage of 82 V from poly-Si emitters, the same current level was measured at 72 V from Mo-polycide emitters. In addition, the application of Mo silicide onto poly-Si emitters reduced the emission current fluctuation considerably. These results show that the polycide emitters can have potential applications in vacuum microelectronics to obtain superior electron emission efficiency and stability     

Short-channel metal-gate TFTs with modified Schottky-barrier source/drain

A thin active layer, a fully silicided source/drain (S/D), a modified Schottky-barrier, a high dielectric constant (high-/spl kappa/) gate dielectric, and a metal gate are integrated to realize high-performance thin-film transistors (TFTs). Devices with 0.1-/spl mu/m gate length were fabricated successfully. Low threshold voltage, low subthreshold swing, high transconductance, low S/D resistance, high on/off current ratio, and negligible threshold voltage rolloff are demonstrated. It is thus suggested for the first time that the short-channel modified Schottky-barrier TFT is a solution to carrier out three-dimension integrated circuits and system-on-panel.     

在薄二氧化硅层上纯多晶硅化镍膜的研究

本文研究了在薄二氧化硅层上快速热退火（RTA）形成的多晶硅化镍膜的电特性，对于在薄二氧化硅上的纯硅化镍膜，测试了其到衬底的泄漏电流，发现二氧化硅性质仍类似于多晶硅膜或纯铝膜下二氧化硅性质，采用准静态C－V方法研究了多晶硅栅和纯硅化镍栅的多晶栅耗尽效应（PDE），并探讨了硅化镍栅掺杂浓度和栅氧化层厚度对PDE的影响，结果表明，即使在未被掺杂的纯硅化镍栅膜，也未曾观察到PDE。     

On the performance of single-gated ultrathin-body SOI Schottky-barrier MOSFETs

The authors study the dependence of the performance of silicon-on-insulator (SOI) Schottky-barrier (SB) MOSFETs on the SOI body thickness and show a performance improvement for decreasing SOI thickness. The inverse subthreshold slopes S extracted from the experiments are compared with simulations and an analytical approximation. Excellent agreement between experiment, simulation, and analytical approximation is found, which shows that S scales approximately as the square root of the gate oxide and the SOI thickness. In addition, the authors study the impact of the SOI thickness on the variation of the threshold voltage V/sub th/ of SOI SB-MOSFETs and find a nonmonotonic behavior of V/sub th/. The results show that to avoid large threshold voltage variations and achieve high-performance devices, the gate oxide thickness should be as small as possible, and the SOI thickness should be /spl sim/ 3 nm.     

A 630-mS/mm GaAs MESFET with Au/WSiN refractory metal gate

GaAs MESFET's with a gate length as low as 0.2 μm have been successfully fabricated with Au/WSiN refractory metal gate n⁺-self-aligned ion-implantation technology. A very thin channel layer with high carrier concentration was realized with 10-keV ion implantation of Si and rapid thermal annealing. Low-energy implantation of the n⁺-contact regions was examined to reduce substrate leakage current. The 0.2-μm gate-length devices exhibited a maximum transconductance of 630 mS/mm and an intrinsic transconductance of 920 mS/mm at a threshold voltage of -0.14 V     

用于200V电平位移电路的薄层SOI高压LDMOS

文章基于1.5μm厚顶层硅SOI材料,设计了用于200 V电平位移电路的高压LDMOS,包括薄栅氧nLDMOS和厚栅氧pLDMOS。薄栅氧nLDMOS和厚栅氧pLDMOS都采用多阶场板以提高器件耐压,厚栅氧pLDMOS采用场注技术形成源端补充注入,避免了器件发生背栅穿通。文中分析了漂移区长度、注入剂量和场板对器件耐压的影响。实验表明,薄栅氧nLDMOS和厚栅氧pLDMOS耐压分别达到344 V和340 V。采用文中设计的高压器件,成功研制出200 V高压电平位移电路。     

A novel self-aligned polycrystalline silicon thin-film transistorusing silicide layers

A novel self-aligned polycrystalline silicon (poly-Si) thin-film transistor (TFT) was fabricated using the three layers of poly-Si, silicon-nitride, and thin amorphous silicon. Gate and source/drain silicide formation was carried out simultaneously following silicon nitride and amorphous silicon patterning, enabling the use of only two mask steps for the TFT. The fabricated poly-Si TFT using laser annealed poly-Si exhibited a field-effect mobility of 30.6 cm²/Vs, threshold voltage of 0.5 V, subthreshold slope of 1.9 V/dec., on/off current ratio of ~10⁶, and off-state leakage current of 7.88×10^-12 A/μm at the drain voltage of 5 V and gate voltage of -10 V     

IrSi Schottky-barrier infrared detectors with 10-μm cutoffwavelength

IrSi Schottky-barrier detectors were fabricated with ~40-Å-thick silicide electrodes formed on p-type Si substrates by in situ processing in a conventional electron-beam evaporator. High-resolution transmission electron microscopy shows that these detectors have clean, abrupt silicide-Si interfaces. For operation at a reverse-bias voltage of 2 V, the cutoff wavelength is ~10 μm, as determined by quantum efficiency measurements     

Schottky-barrier S/D MOSFETs with high-k gate dielectrics and metal-gate electrode

This letter presents a low-temperature process to fabricate Schottky-barrier silicide source/drain transistors (SSDTs) with high-/spl kappa/ gate dielectric and metal gate. For p-channel SSDTs (P-SSDT) using PtSi sourece/drain (S/D) , excellent electrical performance of I/sub on//I/sub off//spl sim/10/sup 7/-10/sup 8/ and subthreshold slope of 66 mV/dec have been achieved. For n-channel SSDTs (N-SSDTs) using DySi/sub 2-x/ S/D , I/sub on//I/sub off/ can reach /spl sim/10/sup 5/ at V/sub ds/ of 0.2 V with two subthreshold slopes of 80 and 340 mV/dec. The low-temperature process relaxes the thermal budget of high-/spl kappa/ dielectric and metal-gate materials to be used in the future generation CMOS technology.