Mobility degradation effects in CMOS differential pair transconductors

The influence of the mobility reduction factor on the dominant third-harmonic distortion and effective transconductance in CMOS differential pair transconductors is examined. Analytical expressions are developed which are suitable for hand calculation and generate realistic estimates for distortion and transconductance. The results produced have been tested against SPICE simulations over a wide range of parameter values and show excellent agreement. The analysis highlights the importance of mobility degradation and reveals that the linearity of the source-coupled differential pair is actually improved as the mobility reduction factor increases. This surprising finding suggests that where 0.15, for example, acceptably low distortion levels (<60 dB for V _i =1 V _pp ) should be achievable with the basic long-tailed pair and that complex linearization schemes may be unnecessary.This work is supported by a grant of the Science and Engineering Research Council.     

Integral expressions for the numerical evaluation of product form expressions over irregular multidimensional integer state spaces

We consider stochastic systems defined over irregular, multidimensional, integer spaces that have a product form steady state distribution. Examples of such systems include closed and BCMP type of queuing networks, polymerization and genetic models. In these models the system state is a vector of integers, n=[n ₁,...,n _M ] and the steady state solution has product form of the type (n)= _i=1 ^M f _i (n _i ). To obtain useful statistics from such product form solutions, (n) has to be summed over some subset of the space over which it is defined. We consider situations when these subsets are defined by a set of equalities and inequalities with integer coefficients, as is most often the case and provide integral expressions to obtain these sums. Typically, a brute force technique to obtain the sum is computationally very expensive. Algorithmic solutions are available for only specific forms of f _i (n _i ) and shapes of the state space. In this paper we derive general integral expressions for arbitrary state spaces and arbitrary f _i (n _i ). The expressions that we derive here become especially useful if the generating functions f _i (n _i ) can be expressed as a ratio of polynomials in which case, exact closed form expressions can be obtained for the sums. We demonstrate the wide applicability of the integral expressions that we derive here through three examples in which we model finite highway cellular systems, copy networks in multicast packet switches and a BCMP queuing network modeling a multiuser computer system.     

H ∞ and Robust Control of 2-D Systems in FM Second Model

This paper deals with output feedback stabilization and H control problems for two-dimensional (2-D) discrete linear systems without or with parameter uncertainty. The class of systems under investigation is described by the 2-D local state space Fornasini-Marchesini second model. We aim at designing a dynamical output feedback controller to achieve asymptotic stability and H performance for the 2-D system. It is shown that the design of output feedback controller can be recast into a convex optimization problem characterized by linear matrix inequalities (LMIs). The LMI solution is further extended to solve the robust stabilization problem for 2-D systems subject to norm-bounded uncertainty. The solutions for the H control and robust stabilization are applied to two application examples: thermal process control and robust stabilization of processes in Darboux equation.     

The significance of finite buffer edge effects in histogram measurements of queues

The empirically oberved fractal or self-similar nature of packet traffic implies heavy tailed queue processes for such traffic. However, based on our simulation analysis using real network data as well as standard models, we have found that the actual losses sustained are remarkably lower than those suggested by the heavy tail distribution. This can be explained by an effect observed in the tail of the histogram of a finite buffer queue process, which we call tail-raising, which contains information pertinent to performance estimation. This effect is also responsible for a significant reduction in packet losses for finite buffer systems, than would be otherwise predicted by the buffer overflow probability for heavy-tailed queues. We define a new parameter X _B on the histogram of a queue process for a finite buffer system, to calculate the tail of the queue process based on the information available in the histogram on the finite buffer. We propose an estimator that approximates X _B , namely, X _min, which is measurable because of the tail-raising effect and has a robust measurement method. The proposed estimator shows promise as a good predictor for performance metrics of queueing systems. We propose an innovative packet loss ratio estimation technique which uses histogram measurements combined with a virtual buffer scheme to find and extrapolate the objective packet loss rate using a binning strategy for histogram measurement, namely, Symmetric Logarithmic Binning (SLB).     

Design considerations for CMOS and GaAs OTAs: Frequency response,linearity, tuning,and common-mode feedback

High-performance operational transconductance amplifiers (OTAs) are important in the design of high-frequency analog transconductance-C (g _m -C) filters. Critical design considerations for OTAs are frequency response, linearity, tuning, output impedance, power supply rejection (PSR), and common-mode rejection (CMR). In CMOS technology, satisfactory OTA design techniques are available, except that the linear input range often is relatively small and the frequency response of the OTA is limited by the intrinsic speed of transistors. In this paper, a new approach is developed to increase the linear input range, and a trade-off between linearity and input range is discussed. A CMOS OTA with less than ±0.4% linearity error over a very large input range is given as a design example. To achieve a very high frequency response, 1m depletion-mode GaAs MESFETs with high intrinsic speed are used to replace MOSFETs. Simple ac compensation, a new technique for output impedance enhancement, and a new tuning method for OTAs with all N-channel devices are used to design a GaAs OTA with very small parasitics and f _–3dB=7 GHz. To improve PSR and CMR, fully balanced structures are used for the OTAs. Design considerations for the interaction of the operation of common-mode feedback (CMF) and tuning are discussed, and improved CMF circuits are proposed. Using the GaAs OTA and considering the frequency limitations imposed by parasitics, the design of a high order ladder filter with 300MHz cutoff frequency is presented as an application.     

A multiprocess performance analysis chart based on the incapability index Cpp: an application to the chip resistors

Statistical process control charts, such as the , R, S², S, and MR charts, have been widely used in the manufacturing industry for controlling/monitoring process performance, which are essential tools for any quality improvement activities. Those charts are easy to understand, which effectively communicate critical process information without using words and formula. In this paper, we introduce a new control chart, called the C_pp multiple process performance analysis chart (MPPAC), using the incapability index C_pp. The C_pp MPPAC displays multiple processes with the departure, and process variability relative to the specification tolerances, on one single chart. We demonstrate the use of the C_pp MPPAC by presenting a case study on some resistor component manufacturing processes, to evaluate the factory performance.     

A high performance pMOSFET with two-step recessed SiGe-S/D structure for 32 nm node and beyond

A novel SiGe-S/D structure for high performance pMOSFET called two-step recessed SiGe-source/drain (S/D) is developed with careful optimization of recessed SiGe-S/D structure. With this method, hole mobility, short channel effect and S/D resistance in pMOSFET are improved compared with conventional recessed SiGe-S/D structure. To enhance device performance such as drain current drivability, SiGe region has to be closer to channel region. Then, conventional deep SiGe-S/D region with carefully optimized shallow SiGe SDE region showed additional device performance improvement without SCE degradation. As a result, high performance 24 nm gate length pMOSFET was demonstrated with drive current of 451 μA/μm at V_dd of 0.9 V and I_off of 100 nA/μm (552 μA/μm at V_dd of 1.0 V). Furthermore, by combining with V_dd scaling, we indicate the extendability of two-step recessed SiGe-S/D structure down to 15 nm node generation.     

Power Microwave FETs Using Epitaxial AlGaAs/GaAs Structures

MBE layers of high-purity Al _x Ga_{1 – x} As solid solutions are produced with 0 x 0.38. Using this material, heterostructure FETs are fabricated for high-power microwave applications. They are demonstrated to deliver up to 1.2 W/mm at 18 GHz under saturation.     

Low-Power Log-Domain CMOS Filter Bank for 2-D Sound Source Localization

This paper proposes the design of a novel current-mode front-end for the extraction of localization spectral cues from two audio signals, together with test results. The front-end consists of two parallel filter banks, envelope extraction and comparison circuitry, together with an AGC loop. The extracted cues are intended to be further processed in order to determine the source azimuth and elevation. A current-mode log-domain implementation using subthreshold MOS operation is used for micropower operation while still achieving a good bandwidth and linearity. A current-mode solution is also preferred because of the ease of implementation of certain mathematical operations. The front-end splits the input signals into different frequency bands and computes monaural and interaural spectral cues from the resulting signal envelopes for each band. The front-end has been optimized to operate at a supply voltage of 1.8 V and most blocks have been designed using a differential architecture. To our knowledge, this is the first log-domain implementation of a front-end for 2-D localization cues extraction. The design has been carried out using a standard double-poly double-metal 0.8 m CMOS process with V _T = 0.8 V. The bandpass filters which form the main core of the chip exhibit a measured dynamic range of 62 dB corresponding to 1.9% THD, while the total power dissipation is 890 W.     

Novel Ion-Lens Configurations: A Further Step to 2-nm Ion-Beam Lithography

Composite axially symmetric immersion ion lenses are considered that consist of an electrostatic and a magnetic lens. For the first time, their performance is evaluated over the entire range of operating conditions: from the case of a zero magnetic field to the case of a zero ion energy on the target. Operating conditions are characterized in terms of = W _t/W ₀, where W ₀ is the energy of an ion at the boundary of the region in which the trajectories are parallel to the axis and W _t is that on the target. For the first time, simple analytical approximations are derived for C _c/r, C _s/r, f/r, and NI, where C _c is the chromatic-aberration coefficient, C _s is the third-order spherical-aberration coefficient, f is the focal distance, NI is the magnetomotive force of the coil, and r is the outer radius of the coil. The behavior of the four quantities is explored as a function of . The following conclusions are drawn: (i) The aberrations are maximum for a zero magnetic field. (ii) The aberration coefficients decrease monotonically with increasing NIand decreasing , the lens changing from an accelerating to a decelerating one. (iii) If , then C _s/r – ^1/4, C _c/r – ^1/6, f/r– ^1/3, and NI – ^–1/2. (iv) The lenses are suitable for resistless heavy-ion projection lithography and can provide 20 × 10¹¹ pixels of area 2 × 2 nm² for an exposed area of 3 × 3 mm². (v) Used in heavy-ion microprobe systems, the lenses could enable resistless lithography over much larger areas than existing equipment.     

A VLSI structure forX(modm) operation

High-computing speed and modularity have made RNS-based arithmetic processors attractive for a long time, especially in signal processing, where additions and multiplications are very frequent. The VLSI technology renewed this interest because RNS-based circuits are becoming more feasible; however, intermodular operations degradate their performance and a great effort results on this topic. In this paper, we deal with the problem of performing the basic operationX(modm), that is the remainder of the integer divisionX/m, for large values of the integerX, following an approximating and correcting approach, which guarantees the correctness of the result.We also define a structure to computeX(modm) by means of few fast VLSI binary multipliers, which is exemplified for 32-bit long numbers, obtaining a total response time lower than 200 nsec. Furthermore, such a structure is evaluated in terms of VLSI complexity and area and time figuresA=(n ² T _m ² ) andT=(T _M ) for the parameterT _M in are derived. A simple positional-to-residue converter is finally presented, based on this structure; it improves some complexity results previously obtained by authors.This work has been supported by the National Program on Solid-State Electronics and Devices of the Italian National Research Council.     

A Distributed Algorithm for Dynamic Channel Allocation

Recent demand for mobile telephone service has been growing rapidly while the electro-magnetic spectrum of frequencies allocated for this purpose remains limited. Any solution to the channel assignment problem is subject to this limitation, as well as the interference constraint between adjacent channels in the spectrum. Channel allocation schemes provide a flexible and efficient access to bandwidth in wireless and mobile communication systems. In this paper, we present an efficient distributed algorithm for dynamic channel allocation based upon mutual exclusion model, where the channels are grouped by the number of cells in a cluster and each group of channels cannot be shared concurrently within the cluster. We discuss the algorithm and prove its correctness. We also show that the algorithm requires at most (worst case) O(N _gN _n logN _n) messages, where N _g is the number of groups and N _n is the number of neighbors. This is compared to Choy's algorithm which requires O(N _g ²N _n), where N _g is the number of groups and N _n is the number of neighboring cells in the system. We report our algorithm's performance with several channel systems using different types of call arrival patterns. Our results indicate that significant low denial rate, low message complexity and low acquisition time can be obtained using our algorithm.     

A canonical form for discrete-time systems defined overZ + *

It is shown that for each memberG of a large class of causal time invariant nonlinear input-output maps, with inputs and outputs defined on the nonnegative integers, there is a functionalA on the input set such that (Gs)(k) has the representationA(F _k s) for allk and each inputs, in whichF _k is a simple linear map that does not depend onG. More specifically, this holds—with anA that is unique in a certain important sense—for anyG that has approximately finite memory and meets a certain often-satisfied additional condition. Similar results are given for a corresponding continuous-time case in which inputs and outputs are defined on ₊. An example shows that the members of a large family of feedback systems have these A-map representations.     

Design and implementation of a new four-quadrant MOS analog multiplier

A four-quadrant MOS analog multiplier is proposed using the quarter-square technique, which is based on the quadratic characteristics of an MOS transistor operating in the saturation region and the difference operation of four identical sourced-coupled differential amplifiers. The multiplier has a simple configuration and a large dynamic range over a wide frequency range, since each input signal passes only one transistor to reach the output. The operation of the multiplier was analyzed in detail, and the second-order effects were also analyzed. The proposed circuit was fabricated in 12-V p-well CMOS process with a 5-m minimum feature. The measured results show that linearity error is less than 1% for 5-V_p-p input at ±5 V supply voltage, and the-3 db bandwidth is 30 MHz.     

Novel Voltage-Tunable, Low-Voltage Linear CMOS Transconductor

A novel voltage-tunable, low-voltage linear CMOS transconductor design is described. The design is based on the improvement of the cross-coupled pairs. SPICE simulation results show that using BSIM models, MOSIS 2-m n-well process parameters and a power supply of ±2.5 V, the linearity error is less than 0.4% over a differential input voltage range of ±1.2 V. The THD for a differential input voltage of 1V _pp at 1 kHz is 1.3%.     

Stability of nonlinear systems with three time scales

We study the asymptotic stability of a singularly perturbed nonlinear time-invariant systemS _v , which has three vastly different time scales. The systemS _v is approximated by three simpler systems over different time intervals. We give a straightforward proof of the fact that the asymptotic stability ofS _v is guaranteed when the equilibrium points of the three simpler systems are exponentially stable and when the parameters and are sufficiently small.Research sponsored by the Joint Services Electronics Program, Contract Number F4962084-C-0057, and NASA, Grant NAG2-243.     

Generating nonorthogonal bases for signal representation

The representation of functions in a basis function expansionz(t)= k=1/=,a _k> x _k (t) is straightforward when the basis functionsx _k (t) are orthogonal. There has been very little work up to this time in determining how to use nonorthogonal bases in signal representation. On the other hand, applications in data compression and signal synthesis often require using specific tailor-made bases. Presented here is a method for constructing very general nonorthogonal bases.Orthogonality has often been used to show that a basis spans the set of functions of interest and to calculate the coefficients of the representation. In this paper, both of these fundamental aspects are addressed for nonorthogonal bases. A new basis {y _k (t)} is obtained by performing a linear transformation on a known existing basis {x _k (t)}. This transformation is constructed such that the coefficients of signal representation on the new basis are readily found. Then, a useful and sufficient condition is placed upon the new basis such that representations converge.The fundamental methods are applied to the standard examples of signal representation. The complex sinusoids, the Rademacher functions, the orthogonal polynomials, and the decaying exponentials are used as the original basis {x _k (t)} from which a new basis {y _k (t)} is generated. Two examples are given to illustrate general applications: one in signal synthesis and one in signal analysis.     

A 10-bit 100 MSamples/s BiCMOS D/A Converter

This paper presents a 10-bit Digital-to-Analogue Converter (DAC) based on the current steering principle. The DAC is processed in a 0.8µm BiCMOS process and is designed to operate at a sampling rate of 100MSamples/s. The DAC is intended for applications using direct digital synthesis, and focus has been set on reducing dynamic nonlinearities to achieve a high spurious free dynamic range (SFDR) at high generated frequencies. The main part of the DAC consists of a matrix of current cells. Each current cell contains an emitter-coupled logic (ECL) flip-flop, clocked by a global ECL clock to ensure accurate clocking. A bipolar differential pair, with a cascode CMOS current sink, steered by the differential output of the ECL flip-flop, is used in each current cell to steer the current. The DAC operates at 5V, and has a power consumption of approximately 650mW. The area of the chip-core is 2.2mm × 2.2mm. The measured integral nonlinearity (INL) and differential nonlinearity (DNL) are both approximately 2 LSB. At a generated frequency of f _g0.1 f _s(f _s = 100MSamples/s) the measured SFDR is 50dB, and at f _g0.3 f _s the measured SFDR is as high as 43dB. The DAC is operating up to a sampling frequency of approximately 140MSamples/s. The DAC uses the hierarchical switching scheme and therefore the dynamic performance is not described well using the conventional glitch energy. A new energy measure that replaces the conventional glitch energy is therefore proposed. This energy measure is especially useful during the design phase.     

Pentacene organic field-effect transistors with polymeric dielectric interfaces: Performance and stability

Low-voltage pentacene organic field-effect transistors (OFETs) with different gate dielectric interfaces are studied and their performance in terms of electrical properties and operational stability is compared. Overall high electrical performance is demonstrated at low voltage by using a 100 nm-thick high-κ gate dielectric layer of aluminum oxide (Al₂O₃) fabricated by atomic layer deposition (ALD) and modified with hydroxyl-free low-κ polymers like polystyrene (PS), divinyltetramethyldisiloxane-bis(benzocyclobutene) (BCB) (Cyclotene™, Dow Chemicals), and as well as with the widely used octadecyl-trichlorosilane (OTS). Devices with PS and BCB dielectric surfaces exhibit almost similar electrical performance with high field-effect mobilities, low subthreshold voltages, and high on/off current ratios. The higher mobility in pentacene transistors with PS can be correlated to the better structural ordering of pentacene films, as demonstrated by atomic force microscopy (AFM) images and X-ray diffraction (XRD). The devices with PS show good electrical stability under bias stress conditions (V_GS = V_DS = −10 V for 1 h), resulting in a negligible drop (2%) in saturation current (I_DS) in comparison to that in devices with OTS (12%), and to a very high decay (30%) for the devices with BCB.