Monolithic AGC loop for a 160 Mb/s transimpedance amplifier

A new BiCMOS monolithic automatic gain control (AGC) amplifier with wide dynamic range is described. The forward gain path has 120 kΩ transimpedance, 140 MHz bandwidth, input noise current spectral density of 1.17 pA/√Hz and input signal current handling capability of 4 mA. An on-chip peak detector incorporating a 25 pA current source yields AGC hold times in the millisecond range     

单通道角跟踪系统接收机AGC控制环路设计

单通道角跟踪系统中角误差信息通常以调幅的形式调制在接收信号包络上,接收机AGC电路必须能够补偿由于传输距离变化引起信号电平起伏,而不引入角误差信息失真。文中采用拉普拉斯变换方式对采用两阶环路滤波器的AGC电路进行分析,得到了电路输出信号以及其失真与输入信号和环路参数的关系。进一步研究表明根据信号传输电平变化最大变化率,合理的设计单脉冲调制速率和环路滤波器的参数,AGC电路能够准确补偿信号传输引起的信号电平变化而几乎不会引入角误差信息失真。     

一种新的噪声系数测量方法

测量含有自动增益控制(AGC)电路的射频模块噪声系数时,使用Y因子法将改变模块的功率增益,进而无法测定.本文提出了一种新的噪声系数测量方法.该方法在信噪比较小的条件下用误码率推算前端的载噪比,避免了用仪器标定载噪比受信道滤波器通带平坦性影响较大的问题;测量过程中,AGC输入端信号和噪声的总功率几乎不变,能够保证AGC功率增益不变,从而可准确测量含有AGC电路的射频模块噪声系数.通过理论推导和数值模拟分析了随机误差、系统误差、实验温度以及测量次数对噪声系数估计的影响,验证了方法的有效性.本文成果已用于我国"北斗一号"卫星导航定位用户机的射频模块测量.     

Power Amplification of Microwave FM Communication Signals Using a Phase-Locked Voltage-Tuned Oscillator

An analog phase-locked oscillator is used as a power amplifier for FM communications signals. Intended service is for FDM telephone message service or television relay. The output power is generated in a varactor-tuned oscillator, which is synchronized with a weak input signal using a phase-lock loop. This involves a phase detector and a wide-band direct-coupled video amplifier whose output is applied to the tuning varactor. The paper is largely theoretical, relating the parameters of the feedback loop to the performance of the overall device. Explicit expressions are derived for the noise figure, the frequency response of the modulation characteristic, AM-PM conversion, and nonlinearity effects in terms of differential gain and intermodulation. In addition, two experimental models are described, together with certain measured data. The phase-lock method differs in many ways from multistage reflection amplifiers and appears to offer advantages for many applications. The device has adequate bandwidth and linearity for a single FDM-FM signal with 1800 or more channels, but must be tuned to the intended frequeucy. Tuning procedures are simple. High gain of 25-35 dB is obtainable in a single microwave "stage." Most of this gain may be associated with the functions of phase detection, video amplification, and VCO tuning. Of major importance, with respect to noise, is that the device is functionally equivalent to a high-gain low-noise microwave preamplifier followed by a low-gain power amplifier stage in which the preamplifier has the noise figure of the phase detector combined with the video amplifier, and the power stage has a noise figure appropriate to the class of power diode used. FM noise generation is substantially lower than in a high-gain reflection amplifier using the same class of microwave power diode throughout.     

IC signal-processing circuit for TV receivers

An IC signal-processing circuit that can be applied in both black-and-white and color receivers is described. The integrated circuit combines the following functions: video preamplifier; keyed AGC detector, operating on top sync level; AGC amplifier for IF and tuner control; noise canceling circuits for AGC and sync circuits; sync separator; automatic horizontal sync; and vertical sync pulse separator. Due to the noise-canceling circuit a stable synchronization is obtained when impulse noise is received. Since the values of the capacitors in the AGC circuit can be rather low without difficulties with instabilities, the performance during fast input signal fluctuations (airplane flutter) is very good.     

Performance Analysis of Digital Tanlock Loop

In this paper, a nonuniform-sampling digital phaselocked loop (DPLL) called the digital tanlock loop (DTL), which uses a new type of phase error detector with linear phase characteristic, is studied. The main feature of the DTL is that the phase error detector, using thetan^{-1}(.)function with in-phase and quadrature samples of the incoming signal, has a linear characteristic with a period of 2π. Accordingly, the DTL can be characterized by a linear difference equation, thereby making it possible to analyze the loop easily, without approximation of nonlinearity as is usually done in analysis of a conventional DPLL with sinusoidal phase characteristic. The performances of the first- and second-order DTL's in the absence and presence of noise have been investigated by analysis and computer simulation. It is shown that the linear phase characteristic results in many attractive features in comparison to the conventional DPLL with the sinusoidal phase characteristic. These include insensitivity of the locking conditions to variation of input signal power, more noise immunity, wider lock range and less steady-state phase error of the first-order loop for an input with frequency offset, and much less sensitivity to initial phase errors in convergence of the second-order loop.     

导引头多源信息AGC系统设计

针对雷达导引头AGC控制处理中传统低通滤波法在输入信号饱和时无法正常工作以及不能直接反映信号幅度的缺陷,通过分析信号幅度与饱和度及功率检波的相互关系,分别提出了基于饱和度的幅度估计方法和平方和功率检波的幅度估计方法,利用这两种方法的特点结合弹载处理机应用,设计了导引头多源信息自动增益控制算法,并给出了实现流程.利用Matlab仿真引入算例,证明其具有响应时间短、控制精度高、系统性能稳定的特点.     

A high-performance monolithic IF amplifier incorporating electronic gain control

A direct-coupled monolithic IF amplifier that incorporates an active gain control stage and exhibits a power gain of 50 dB and an AGC range of 60 dB at 50 MHz is described. This circuit has negligible change in either input or output admittance, and has excellent signal linearity over the full range of gain control. Experimental and theoretical analyses are made of the large signal response, stability, available gain, and noise behavior of the circuit. An application to color television is discussed in which the functions of the 45-MHz IF amplifier and the dc-AGC circuitry are fabricated on a single die.     

Noise Output and Noise Figure of Biased Millimeter-Wave Detector Diodes

The behavior of a dc biased millimeter-wave detector diode was investigated by theoretical analysis and experimental measurement. The results indicate that because of the nonlinearity of the diode, shot noise appearing across the diode increases with dc biasing. For the same reason conversion gain of the detector increases with bias. The increase in gain is faster than the increase in noise for a certain range of bias current. Thus the noise figure of the diode detector and its minimum detectable signal are decreased.     

An Integrated IF Amplifier and Detector for an A.M. Upconversion Radio

This paper presents a monolithically integrated IF amplifier and envelope detector for an AM upconversion car-radio receiver. This receiver is intended for the reception of the long-wave and medium-wave frequency bands and uses an intermediate frequency of 10.7 MHz. Specific requirements resulting from the upconversion concept will be illustrated and the basic considerations for maximization of the signal-to-noise ratio as a function of the input signal level will be given. Furthermore, a new method will be presented for fixing the signal levels and the AGC speed in the amplifier. The amplifier uses two emitter-driven variable-gain pairs alternated by negative-feedback current amplifiers. It has an AGC range of 90 dB and a gain of 66 dB. The audio output level is constant within 0.2 dB over the full controll range. A cross-quad compensated envelope detector is driven at a level as low as 30 mV and shows less than 3-percent distortion at a modulation depth of 80 percent.     

A fast configurable AGC for front-end of digital hearing aids

This paper presents a fast configurable automatic gain control (AGC) with strong focus on fast acting control and low power consumption. This AGC includes two paths, main amplification path and gain adjusting path. Using the gain adjusting path through an extra amplifier provides a way for tracking and comparing the input signal with four adjusted thresholds to be judged for selecting the appropriate gain value for main amplification path. This mechanism of gain control is done by reorganization of input level and changing the resistance of feedback in main amplification path to generate smooth variation gain, without any interruption or delay in signal flow through the variable gain amplifier. Moreover, in order to protect the user from intense transients in variations of the input signal level, output level of variable gain amplifier is directly monitored using optimum threshold to reduce the overall gain using feedback control mechanism. The minimum power is consumed by gain adjusting path has almost no considerable on power consumption, it greatly improves hearing quality. Meanwhile, using a large size PMOS differential pair at the input improved the noise performance. Proposed AGC designed and simulated in TSMC 130-nm CMOS process. The post layout simulation results the maximal SNR is 84.6 dB in 100 Hz–19.6 kHz band-width and the total consumption power of this AGC is 78 μW at 1 V supply voltage. In addition, its gain is varied smoothly between 20 to 57 dB. Achieved results demonstrate that designed AGC meet the requirement of analog front end of hearing aids.

     

An adaptive detector for deterministic signals in noise of unknownspectra using the Rao test

An adaptive detector for a known deterministic signal of unknown amplitude in Gaussian noise of unknown spectra is described. The detector is based on the Rao test, which is asymptotically equivalent to the generalized likelihood ratio. The detector achieves constant false alarm probability in the presence of large changes in input noise bandwidth and variance while providing optimum detection performance. The results are supported by simulation     

Decision-Directed Automatic Gain Control for MAPSK Systems

An automatic gain control (AGC) loop is presented for use withM-ary amplitude- and phase-shift keying (MAPSK) systems. The gain control amplifier is regulated by an error signal formed by the difference between the estimated amplitude level and the received amplitude level. The AGC performance is thus independent of the short-term average received signal energy. AGC loop analysis and simulation is presented forM-ary amplitude-shift keying (MASK) and quadrature amplitude-shift keying (QASK). The AGC is shown to have a negligible degradation on the symbol probability of error for most practical cases. A generalized AGC for an arbitrary MAPSK system is also presented.     

一种变时间常数自动增益控制环路与算法设计

针对时间常数恒定的自动增益控制环路的不足,设计了一种时间常数可变的自动增益控制结构,实现了环路响应时间能够自适应地随着输入信号的增大而减小,在一定程度上克服了恒定时间常数自动增益控制环路的不足。给出了其核心算法并进行了详细推导,在理论上证明了该结构的稳定性以及算法的有效性。最后,对提出的结构以及算法进行了仿真。仿真结果表明,本文所设计的结构与提出的算法既能对大电平信号迅速响应,又能保证足够小的反调制失真。     

一种新的数字接收机AGC电路

该文提出一种新的数字接收机自动增益控制(AGC)电路。该电路将传统的两级级连负反馈AGC电路中后级AGC电路的反馈控制改为前馈控制,前后两级AGC电路共用一套功率检波器和环路滤波器,前级AGC电路的增益控制误差能够在后级AGC电路中得到修正,故新的AGC电路的总增益控制误差仅取决于后级AGC电路的增益控制误差。计算机仿真和硬件电路测试结果均表明,与传统的AGC电路相比,该文提出的新AGC电路能够提高增益控制精度,降低AGC响应时间。     

A 7.5-GHz super regenerative detector

In this paper, simulated and measured results are presented for a microwave-integrated-circuit super regenerative detector operating at 7.5 GHz and brief comparisons made to a monolithic-microwave integrated-circuit super regenerative detector operating at 34 GHz. The sensitivity of the 7.5-GHz detector was measured at -83-dBm (AM, 1 kHz, 100 % mod) RF signal for 12 dB (signal + noise + distortion)/(noise + distortion). Simulation results show that, to produce a sensitive super regenerative detector, a high rate of change in loop gain of the oscillator circuit with respect to the gate bias (quenching) voltage and a high maximum loop gain at the point of detection is required. It has also been shown, by simulation and measurement, that the detection frequency of the super regenerative detector is lower than the normal free-running oscillation frequency     

3G系统中AGC的FPGA设计实现

详细介绍了数字AGC的基本原理,3G接收机需要采用AGC电路处理输入的无线信号,从而给无线环路中的可变增益放大器或数控衰减器提供外部控制信号,使得无线链路输出基本恒定且与输入信号电平无关的信号给基带部分处理,同时在很宽的范围内保持线性。RF输入电压经IF放大后,检波器检测出该电压的包络。该包络电压经AGC处理后,产生增益可变器件的控制电压,从而减小IF的输入和增益。     

Optical Phase Locking by Local Oscillator Phase Dithering

A new type of optical phase-locked loop (OPLL), called the dither loop, is mathematically analyzed. The dither loop extracts a phase-error signal by applying a small phase disturbance to the local oscillator laser, and synchronously demodulating the resulting power fluctuation in the output signal of the receiver. The dither loop is superior to other OPLL designs, because it does not need the transmission of a residual carrier, it employs a 180deg/3-dB hybrid, an ac-coupled front end, and it accepts a large variety of input signals. Furthermore, in a dither loop, the amount of power which is fed to the phase-locking branch can be adaptively controlled within the receiver. The analysis first focuses on an expression for the phase detector gain in a dither loop. Using a linearized model, the phase-error variance due to phase dithering, white frequency noise induced phase noise and shot noise is evaluated. A simplified expression for the power penalty generated by the phase dither signal is presented. In a more complex calculation, the overall power penalty due to phase dithering and the residual phase error is found. This allows us to synthesize a design rule for dither loops with optimum performance measures. The design rule determines all relevant system parameters, based on specified values of the system bit rate, the laser linewidth, the photodiode responsivity and the required bit-error rate     

一种带有外部噪声识别功能的AGC电路的设计

基于红外遥控接收芯片中自动增益控制电路的功能需求及其应用环境,设计了一种能够有效抑制外部环境光干扰、线性度高的自动增益控制电路。该电路在传统自动增益控制电路的设计理念基础上引入外部噪声识别功能,设计的核心子电路包括具有线性增益特性的可变增益放大器、比较器以及利用空闲时间识别外部噪声的信号检测与增益控制电路。电路基于0.25μm标准CMOS工艺设计,使用Hspice软件进行仿真验证。仿真结果表明:电源电压为3~5 V,温度为0~85℃时,可变增益放大器的可控增益范围至少可达-69.5~27.6 dB,且至少具有42 dB的线性增益控制范围。     

自动增益控制环路方程的一种简化处理方法及环路稳定时间分析

基于一种典型的自动增益控制(AGC)环路的模型，采用对数表示方式，简化了AGC环路的静态微动方程和动态运动方程。用数学模型动态表示出AGC环路输出信号和增益控制信号的变化过程，定量定性分析了AGC环路的稳定时间。仿真结果及实际应用验证了本文方法的有效性。