High performance poly-crystalline silicon thin film transistorsfabricated using remote plasma chemical vapor deposition of SiO2

A remote plasma chemical vapor deposition (RPCVD) of SiO₂ was investigated for forming an interface of SiO₂/Si at a low temperature below 300°C. A good SiO₂/Si interface was formed on Si substrates through decomposition and reaction of SiH₄ gas with oxygen radical by confining plasma using mesh plates. The density of interface traps (D_it) was as low as 3.4×10¹⁰ cm^-2eV^-1. N- and p-channel Al-gate poly-Si TFTs were fabricated at 270°C with SiO₂ films as a gate oxide formed by RPCVD and laser crystallized poly-crystalline films formed by a pulsed XeCl excimer laser. They showed good characteristics of a low threshold voltage of 1.5 V (n-channel) and -1.5 V (p-channel), and a high carrier mobility of 400 cm²/Vs     

High quality SiO2/Si interfaces of poly-crystallinesilicon thin film transistors by annealing in wet atmosphere

A new post-metallization annealing technique was developed to improve the quality of metal-oxide-semiconductor (MOS) devices using SiO ₂ films formed by a parallel-plate remote plasma chemical vapor deposition as gate insulators. The quality of the interface between SiO₂ and crystalline Si was investigated by capacitance-voltage (C-V) measurements. An H₂O vapor annealing at 270°C for 30 min efficiently decreased the interface trap density to 2.0×10¹⁰ cm^-2 eV^-1, and the effective oxide charge density from 1×10 ¹² to 5×10⁹ cm^-2. This annealing process was also applied to the fabrication of Al-gate polycrystalline silicon thin film transistors (poly-Si TFT's) at 270°C. In p-channel poly-Si TFT's, the carrier mobility increased from 60-400 cm² V^-1 s^-1 and the threshold voltage decreased from -5.5 to -1.7 V     

Yttrium oxide/silicon dioxide: a new dielectric structure forVLSI/ULSI circuits

Electrical characteristics of Al/yttrium oxide (~260 Å)/silicon dioxide (~40 Å)/Si and Al/yttrium oxide (~260 Å)/Si structures are described. The Al/Y₂O₃/SiO₂/Si (MYOS) and Al/Y₂ O₃/Si (MYS) capacitors show very well-behaved I-V characteristics with leakage current density <10^-10 A/cm² at 5 V. High-frequency C- V and quasistatic C-V characteristics show very little hysteresis for bias ramp rate ranging from 10 to 100 mV/s. The average interface charge density (Q_f+Q _it) is ~6×10¹¹/cm² and interface state density D_it is ~10¹¹ cm^-2-eV^-1 near the middle of the bandgap of silicon. The accumulation capacitance of this dielectric does not show an appreciable frequency dependence for frequencies varying from 10 kHz to 10 MHz. These electrical characteristics and dielectric constant of ~17-20 for yttrium oxide on SiO₂/Si make it a variable dielectric for DRAM storage capacitors and for decoupling capacitors for on-chip and off-chip applications     

不同退火氛围对TiN/HfO2/SiO2/Si结构电荷分布的影响

热退火技术是集成电路制造过程中用来改善材料性能的重要手段。系统分析了两种不同的退火条件(氨气氛围和氧气氛围)对TiN/HfO₂/SiO₂/Si结构中电荷分布的影响,给出了不同退火条件下SiO₂/Si和HfO₂/SiO₂界面的界面电荷密度、HfO₂的体电荷密度以及HfO₂/SiO₂界面的界面偶极子的数值。研究结果表明,在氨气和氧气氛围中退火会使HfO₂/SiO₂界面的界面电荷密度减小、界面偶极子增加,而SiO₂/Si界面的界面电荷密度几乎不受退火影响。最后研究了不同退火氛围对电容平带电压的影响,发现两种不同的退火条件都会导致TiN/HfO₂/SiO₂/Si电容结构平带电压的正向漂移,基于退火对其电荷分布的影响研究,此正向漂移主要来源于退火导致的HfO₂/SiO₂界面的界面偶极子的增加。     

Suppression of the boron penetration induced Si/SiO2interface degradation by using a stacked-amorphous-silicon film as thegate structure for pMOSFET

The authors report that the boron penetration through the thin gate oxide into the Si substrate does not only cause a large threshold voltage shift but also induces a large degradation in the Si/SiO₂ interface. An atomically flat Si/SiO₂ interface can be easily obtained by using a stacked-amorphous-silicon (SAS) film as the gate structure for p⁺ poly-Si gate MOS devices even with the annealing temperature as high as 1000°C     

Metal–Oxide–High-$kappa$ Dielectric–Oxide–Semiconductor (MOHOS) Capacitors and Field-Effect Transistors for Memory Applications

Metal-oxide-high-kappa dielectric-oxide-silicon capacitors and transistors are fabricated using HfO₂ and Dy₂O₃ high-kappa dielectrics as the charge storage layer. The programming speed of Al/SiO₂/Dy₂O₃/ SiO₂/Si transistor is characterized by a DeltaV _th shift of 1.0 V with a programming voltage of 12 V applied for 10 ms. As for retention properties, the Al/SiO₂/Dy₂O₃/ SiO₂/Si transistors can keep a DeltaV _th window of 0.5 V for 2 times10⁸ s. The corresponding numbers for Al/ SiO₂/HfO₂/SiO₂/Si transistors are 100 ms and 2 times10⁴ s, respectively. The better performance of the Al/SiO₂/Dy₂O₃/ SiO₂/Si transistors is attributed to the larger conduction band offset at the Dy₂O₃/SiO₂ interface.     

The effects of NH3 plasma passivation on polysiliconthin-film transistors

The NH₃ plasma passivation has been performed for the first time on the polycrystalline silicon (poly-Si) thin-film transistors (TFT's). It is found that the TFT's after the NH₃ plasma passivation achieve better device performances, including the off-current below 0.1 pA/μm and the on/off current ratio higher than 10⁸, and also better hot-carrier reliability as well as thermal stability than the H₂-plasma devices. These improvements were attributed to not only the hydrogen passivation of the grain-boundary dangling bonds, but also the nitrogen pile-up at SiO₂/poly-Si interface and the strong Si-N bond formation to terminate the dangling bonds at the grain boundaries of the polysilicon films     

Promising storage capacitor structures with thin Ta2O5 film for low-power high-density DRAMs

To ensure the required capacitance for low-power DRAMs (dynamic RAMs) beyond 4 Mb, three kinds of capacitor structures are proposed: (a) poly-Si/SiO₂/Ta₂O₅/SiO₂ /poly-Si or poly-Si/Si₃N₄/Ta₂O ₅/SiO₂/poly-Si (SIS), (b) W/Ta₂O₅ /SiO₂/poly-Si (MIS), and (c) W/Ta₂O₅ W (MIM). The investigation of time-dependent dielectric breakdown and leakage current characteristics indicates that capacitor dielectrics that have equivalent SiO₂ thicknesses of 5, 4, and 3 nm can be applied to 3.3-V operated 16-Mb DRAMs having stacked capacitor cells (STCs) by using SIS, MIS, and MIM structures, respectively, and that 3 and 1.5 nm can be applied to 1.5-V operated 64-Mb DRAMs having STCs by using MIS and MIM structures, respectively. This can be accomplished while maintaining a low enough leakage current for favorable refresh characteristics. In addition, all these capacitors show good heat endurance at 950°C for 30 min. Therefore, these capacitors allow the fabrication of low-power high-density DRAMs beyond 4 Mb using conventional fabrication processes at temperatures up to 950°C. Use of the SIS structure confirms the compatability of the fabrication process of a storage capacitor using Ta₂O₅ film and the conventional DRAM fabrication processes by successful application to the fabrication process of an experimental memory array with 1.5-μm×3.6-μm stacked-capacitor DRAM cells     

Optimization of gate oxide N2O anneal for CMOSFET's atroom and cryogenic temperatures

This paper presents a study of the impact of gate-oxide N₂ O anneal on CMOSFET's characteristics, device reliability and inverter speed at 300 K and 85 K. Two oxide thicknesses (60 and 110 Å) and five N₂O anneal conditions (900~950°C, 5~40 min) plus nonnitrided process and channel lengths from 0.2 to 2 μm were studied to establish the correlation between the nitrogen concentration at Si/SiO₂ interface and the relative merits of the resultant devices. We concluded that one simple post-oxidation N₂O anneal step can increase CMOSFET's lifetime by 4~10 times, effectively suppress boron penetration from the P⁺ poly-Si gate of P-MOSFET's without sacrificing CMOS inverter speed. We also found that the benefits in terms of the improved interface hardness and charge trapping characteristic still exist at cryogenic temperature. All these improvements are found to be closely correlated to the nitrogen concentration incorporated at the Si/SiO₂ interface. The optimal N₂O anneal occurs somewhere at around 2% of nitrogen incorporation at Si/SiO₂ interface which can be realized by annealing 60~110 Å oxides at 950°C for 5 min or 900°C for 20 min     

Low-Frequency Noise Assessment of Silicon Passivated Ge pMOSFETs With TiN/TaN/ HfO2 Gate Stack

The low-frequency noise of pMOSFETs fabricated in epitaxial germanium-on-silicon substrates is studied. The gate stack consists of a TiN/TaN metal gate on top of a 1.3-nm equivalent oxide thickness HfO₂/SiO₂ gate dielectric bilayer. The latter is grown by chemical oxidation of a thin epitaxial silicon film deposited to passivate the germanium surface. It is shown that the spectrum is of the 1/f^gamma type, which obeys number fluctuations for intermediate gate voltage overdrives. A correlation between the low-field mobility and the oxide trap density derived from the 1/f noise magnitude and the interface trap density obtained from charge pumping is reported and explained by considering remote Coulomb scattering     

TiN/TaN 厚度变化对nMOSCAP栅叠层有效功函数的影响

We evaluated the TiN/TaN/TiA1 triple-layer to modulate the effective work function （EWF） of a metal gate stack for the n-type metal-oxide-semiconductor （NMOS） devices application by varying the TiN/TaN thickness. In this paper, the effective work function of EWF ranges from 4.22 to 4.56 eV with different thicknesses of TiN and TaN. The thinner TiN and/or thinner in situ TaN capping, the closer to conduction band of silicon the EWF is, which is appropriate for 2-D planar NMOS. Mid-gap work function behavior is observed with thicker TiN, thicker in situ TaN capping, indicating a strong potential candidate of metal gate material for replacement gate processed three-dimensional devices such as FIN shaped field effect transistors. The physical understandings of the sensitivity of EWF to TiN and TaN thickness are proposed. The thicker TiN prevents the A1 diffusion then induces the EWF to shift to mid-gap. However, the TaN plays a different role in effective work function tuning from TiN, due to the Ta-O dipoles formed at the interface between the metal gate and the high-k layer.     

1/f noise reduction in PMOSFETs by an additional preoxidationcleaning with an ammonia hydrogen peroxide mixture

1/f noise magnitude in a 15 μm×0.5 μm PMOSFET was remarkably reduced by simply adding a cleaning step using an ammonia hydrogen peroxide mixture (APM) prior to gate oxidation. Gate input-referred noise level for APM-finished PMOSFETs at f=10 Hz was around -128 dBV²/Hz whereas for standard, HF-finished devices, the level was around -114 dBV²/Hz. Flat-band voltages (V_FBs) determined by a capacitance-voltage (C-V) measurement were -0.19 V for an APM-finished PMOS and -0.34 V for a HF-finished PMOS. Based on the V_FB values, interface state densities were determined to be N_it=3.02×10¹¹ cm^-2 for APM-finished PMOS and N_it=6.47×10¹¹ cm^-2 for HF-finished PMOS. Lower interface state density obtained by the APM preoxidation cleaning is consistent with the remarkable reduction in the 1/f noise magnitude     

Development of high-performance polycrystalline silicon thin-filmtransistors (TFTs) using defect control process technologies

High-performance polycrystalline Si (poly-Si) thin-film transistors (TFTs) were successfully fabricated on a glass substrate below 425°C by introducing defect control process technologies. The defects in the laser crystallized poly-Si films were terminated by an oxygen plasma treatment to the film and the defects at the SiO₂ /Si interface were controlled by a gate SiO₂ film formation using electron cyclotron resonance (ECR) plasma enhanced chemical vapor deposition (PECVD). As a result, high n-channel mobility of 309 cm²V^-1s^-1, low threshold voltage of 1.12 V and low subthreshold swing of 250 mV/decade were obtained. In addition, it was demonstrated that the defect control process is quite effective to minimize the variation of TFT characteristics     

Suppression of the boron penetration induced dielectric degradationby using a stacked-amorphous-silicon film as the gate structure forpMOSFET

This work proposes a stacked-amorphous-silicon (SAS) film as the gate structure of the p⁺ poly-Si gate pMOSFET to suppress boron penetration into the thin gate oxide. Due to the stacked structure, a large amount of boron and fluorine piled up at the stacked-Si layer boundaries and at the poly-Si/SiO₂ interface during the annealing process, thus the penetration of boron and fluorine into the thin gate oxide is greatly reduced. Although the grain size of the SAS film is smaller than that of the as deposited polysilicon (ADP) film, the boron penetration can be suppressed even when the annealing temperature is higher than 950°C. In addition, the mobile ion contamination can be significantly reduced by using this SAS gate structure. This results in the SAS gate capacitor having a smaller flat-band voltage shift, a less charge trapping and interface state generation rate, and a larger charge-to-breakdown than the ADP gate capacitor. Also the Si/SiO₂ interface of the p⁺ SAS gate capacitor is much smoother than that of the p⁺ SAS gate capacitor     

High-mobility poly-Si TFTs fabricated on flexible stainless-steelsubstrates

High mobility polycrystalline Si thin-film transistors (poly-Si TFTs) are firstly fabricated on flexible stainless-steel substrates 100 μm thick through low-temperature processes where both active Si and gate SiO₂ films are deposited by glow-discharge sputtering and the Si films are crystallized by KrF excimer laser irradiation. The gate SiO₂ films are sputter-deposited in oxygen atmosphere from the SiO₂ target. Resulting poly-Si TFTs show excellent characteristics of mobility of 106 cm²/V·s and drain current on-off ratio of as high as 1×10⁶. Thus, the poly-Si TFTs are very promising for realizing novel flat panel displays of lightweight and rugged LCDs and LEDs     

A novel self-aligned TiN formation by N2+implantation during two-step annealing Ti-salicidation for submicrometerCMOS technology application

A new technology of self-aligned TiN/TiSi₂ formation using N₂⁺ implantation during two-step annealing Ti-salicidation process has been developed. The formation of TiN was confirmed by RBS analysis. The leakage currents of n⁺/p junction diodes fabricated using this technology were measured to investigate the phenomena of Al spiking into Si-substrate. The measured reverse-bias leakage current of diode per unit junction area with Al/TiN/TiSi₂ contact is 1.2 nA/cm² at -5 V, which is less than all of reported data. Also it can sustain the annealing process for 30 min at 500°C. Thus, TiN formed with this technology process is suggested as a very effective barrier layer between TiSi₂ and Al for submicron CMOS technology applications     

Thermally robust Ta2O5 capacitor for the256-Mbit DRAM

The thermal degradation of the Ta₂ O₅ capacitor during BPSG reflow has been studied. The cause of deterioration of Ta₂O₅ with the TiN top electrode was found to be the oxidation of TiN. By placing a poly-Si layer between TiN and BPSG to suppress oxidation, the low leakage current level was maintained after BPSG reflow at 850°C. The Ta₂O₅ capacitor with the TiN/poly-Si top electrode was integrated into 256-Mbit DRAM cells and excellent leakage current characteristics were obtained     

A Comparative Study of HfTaON/SiO2 and HfON/SiO2 Gate Stacks With TaN Metal Gate for Advanced CMOS Applications

The electrical characteristics of a novel HfTaON/SiO₂ gate stack, which consists of a HfTaON film with a dielectric constant of 23 and a 10-Aring SiO₂ interfacial layer, have been investigated for advanced CMOS applications. The HfTaON/SiO₂ gate stack provided much lower gate leakage current against SiO₂ , good interface properties, excellent transistor characteristics, and superior carrier mobility. Compared to HfON/SiO₂, improved thermal stability was also observed in the HfTaON/SiO₂ gate stack. Moreover, charge-trapping-induced threshold voltage V _th instability was examined for the HfTaON/SiO₂ and HfON/SiO₂ gate stacks. The HfTaON/SiO₂ gate stack exhibited significant suppression of the V_th instability compared to the HfON/SiO₂, in particular, for nMOSFETs. The excellent performances observed in the HfTaON/SiO₂ gate stack indicate that it has the potential to replace conventional SiO₂ or SiON as gate dielectric for advanced CMOS applications     

Low thermal-budget ultrathin NH3-annealedatomic-layer-deposited Si-nitride/SiO2 stack gate dielectricswith excellent reliability

We present novel ultrathin (EOT = 2.1 nm) atomic-layer-deposited (ALD) Si-nitride/SiO₂ stack gate dielectrics annealed in NH ₃ at a moderate temperature of 550°C. MOS capacitors are fabricated using the proposed dielectrics. Excellent performance in electrical stressing experiments is shown by the dielectrics. They also exhibit better interface quality, low bulk-trap density, low trap generation rate, and high long-term reliability in comparison with ALD Si-nitride/SiO₂ stack dielectrics without NH₃-annealing and conventional thermal SiO₂ dielectrics. The proposed stack-gate dielectrics appear to be very promising for ULSI devices     

One transistor ferroelectric memory with Pt/Pb5Ge3O11/Ir/poly-Si/SiO2/Si gate-stack

One transistor ferroelectric nonvolatile memory with gate stack of Pt/Pb₅Ge₃O₁₁/lr/poly-Si/SiO₂ /Si was successfully fabricated. This device features a saturated memory window of 3 V at a programming voltage of higher than 3 V from C-V and I-V measurements. The memory window decays rapidly within 10 seconds after programming, but remains stable at 1 V for up to 100 h. The "on" and "off" state currents are greater than 10 μA/μm and less 0.01 pA/μm, respectively, at a drain voltage of 0.1 V