An investigation into the effects of probing and wire bonding stress on the reliability of BOAC

This work describes two types of low stress bonding over active circuit (BOAC) structures applying a finite element analysis. The advantage of improving the chip area utility of the BOAC design is approximately 150–180 μm for each dimension. A 0.13 μm 2 Mb high-speed SRAM with fluorinated silicate glass (FSG) low-k dielectric was combined with these two BOAC structures as the test vehicles to evaluate the impact of the probing and wire bonding stress on the reliability. Initially, a cantilevered probe card was applied to probe the BOAC pads using the typical and the worse probing conditions. Before and after the circuits probing (CP1 and CP2) the experimental results were compared, including the 2 Mb high-speed SRAM yield and wafer bit map data. The difference between the CP1 and CP2 results were negligible for all probing split cells. Next, the cross-section of the BOAC pad under the probing area was investigated following the worst probing condition. In addition, the BOAC pads evaluate the bondability, including the use of ball shear, wire pull and cratering tests. Moreover, all BOAC packaging samples underwent reliability tests, including HTOL, TCT, TST, and HTST. All the bondability and reliability tests passed the criteria for both proposed BOAC structures. Finally, the immunity level of both proposed BOAC pads, for ESD-HBM (human body mode) and ESD-MM (machine mode), differed slightly from the normal pads. No performance degradation was detected. Accordingly, this work shows that both proposed BOAC structures can be used to improve the active chip area utility or save the chip area.     

Effects of underfill materials on the reliability of low-K flip-chip packaging

The reliability of low-K flip-chip packaging has become a critical issue owing to the low strength and poor adhesion qualities of the low-K dielectric material when compared with that of SiO₂ or fluorinated silicate glass (FSG). The underfill must protect the solder bumps and the low-K chip from cracking and delamination. However, the material properties of underfill are contrary to those required for preventing solder bumps and low-K chip from cracking and delamination. This study describes the systematic methodologies for how to specify the adequate underfill materials for low-K flip-chip packaging. The structure of the test vehicle is seven copper layers with a low-K dielectric constant value of 2.7-2.9, produced by the chemical vapor deposition (CVD) process. Initially, the adhesion and the flow test of the underfill were evaluated, and then the low-K chip and the bumps stress were determined using the finite element method. The preliminary screened underfill candidates were acquired by means of the underfill adhesion and flow test, and balancing the low-K chip and the bumps stress simulation results. Next, the low-K chips were assembled with these preliminary screened underfills. All the flip-chip packaging specimens underwent the reliability test in order to evaluate the material properties of the underfill affecting the flip-chip packaging stress. In addition, the failed samples are subjected to failure analysis to verify the failure mechanism. The results of this study indicate that, of the underfill materials investigated, those with a glass transition temperature (T_g) and a Young’s modulus of approximately 70–80 °C and 8–10 GPa, respectively, are optimum for low-K flip-chip packaging with eutectic solder bumps.     

Oxidation of copper pads and its influence on the quality of Au/Cu bonds during thermosonic wire bonding process

To understand the copper oxide effect on the bondability of gold wire onto a copper pad, thermosonic gold wire bonding to a copper pad was conducted at 90–200 °C under an air atmosphere. The bondability and bonding strength of the Au/Cu bonds were investigated. The bondability and bonding strength were far below the minimum requirements stated in industrial codes. At elevated bonding temperature of 200 °C, the bondability and bonding strength deteriorated mainly due to hydroxide and copper oxide formation on the copper pad. Oxide formation occurred if no appropriate oxide preventive schemes were applied. At lower bonding temperature, 90 °C, poor bondability and low bonding strength were mainly attributed to insufficient thermal energy for atomic inter-diffusion between the gold ball and copper pad.Copper pad oxidation was investigated using an electron spectroscopy for chemical analysis (ESCA) and thermogravimetric analysis (TGA). An activation energy of 35 kJ/mol for copper pad oxidation was obtained from TGA. This implies that different mechanisms govern the oxidation of copper pad and bulk copper. Hydroxide and copper oxide were identified based on the shifted binding energy. Cu(OH)₂ forms mainly on the top surface of copper pads and the underlying layer consists mainly of CuO. The hydroxide concentration increased with increasing the heating temperatures. After heating at 200 °C, the hydroxide concentration on the copper pad surface was approximately six times that at 90 °C. Protective measures such as passivation layer deposition or using shielding gas are critical for thermosonic wire bonding on chips with copper interconnects.     

Direct gold and copper wires bonding on copper

The key to bonding to copper die is to ensure bond pad cleanliness and minimum oxidation during wire bonding process. This has been achieved by applying a organic coating layer to protect the copper bond pad from oxidation. During the wire bonding process, the organic coating layer is removed and a metal to metal weld is formed. This organic layer is a self-assembled monolayer. Both gold and copper wires have been wire-bonded successfully to the copper die even without prior plasma cleaning. The ball diameter for both wires are 60 μm on a 100 μm fine pitch bond pad. The effectiveness of the protection of the organic coating layer starts from the wafer dicing process up to the wire bonding process and is able to protect the bond pad for an extended period after the first round of wire bond process. In this study, oxidization of copper bond pad at different packaging processing stages, dicing and die attach curing, have been explored. The ball shear strength for both gold and copper ball bonds achieved are 5 and 6 g/mil² respectively. When subjected to high temperature storage test at 150 °C, the ball bonds formed by both gold and copper wire bond on the organic coated copper bondpad are thermally stable in ball shear strength up to a period of 1440 h. The encapsulated daisy chain test vehicle with both gold and copper wires bonding have passed 1000 cycles of thermal cycling test (−65 to 150 °C). It has been demonstrated that orientation imaging microscopy technique is able to detect early levels of oxidation on the copper bond pad. This is extremely important in characterization of the bondability of the copper bond pad surface.     

Thermosonic bonding of gold wire onto a copper pad with titanium thin-film deposition

A novel thermosonic (TS) bonding process for gold wire bonded onto chips with copper interconnects was successfully developed by depositing a thin, titanium passivation layer on a copper pad. The copper pad oxidizes easily at elevated temperature during TS wire bonding. The bondability and bonding strength of the Au ball onto copper pads are significantly deteriorated if a copper-oxide film exists. To overcome this intrinsic drawback of the copper pad, a titanium thin film was deposited onto the copper pad to improve the bondability and bonding strength. The thickness of the titanium passivation layer is crucial to bondability and bonding strength. An appropriate, titanium film thickness of 3.7 nm is proposed in this work. One hundred percent bondability and high bonding strength was achieved. A thicker titanium film results in poor bond-ability and lower bonding strength, because the thicker titanium film cannot be removed by an appropriate range of ultrasonic power during TS bonding. The protective mechanism of the titanium passivation layer was interpreted by the results of field-emission Auger electron spectroscopy (FEAES) and electron spectroscopy for chemical analysis (ESCA). Titanium dioxide (TiO₂), formed during the die-saw and die-mount processes, plays an important role in preventing the copper pad from oxidizing. Reliability of the high-temperature storage (HTS) test for a gold ball bonded on the copper pad with a 3.7-nm titanium passivation layer was verified. The bonding strength did not degrade after prolonged storage at elevated temperature. This novel process could be applied to chips with copper interconnect packaging in the TS wire-bonding process.     

Thermosonic bonding of gold wire onto silver bonding layer on the bond pads of chips with copper interconnects

A copper pad oxidizes easily at elevated temperatures during thermosonic wire bonding for chips with copper interconnects. The bondability and bonding strength of a gold wire onto a bare copper pad are seriously degraded by the formation of a copper oxide film. A new bonding approach is proposed to overcome this intrinsic drawback of the copper pad. A silver layer is deposited as a bonding layer on the surface of copper pads. Both the ball-shear force and the wire-pull force of a gold wire bonded onto copper pads with silver bonding layers far exceed the minimum values stated in the JEDEC standard and MIL specifications. The silver bonding layer improves bonding between the gold ball and copper pads. The reliability of gold ball bonds on a bond pad is verified in a high-temperature storage (HTS) test. The bonding strength increases with the storage time and far exceeds that required by the relevant industrial codes. The superior bondability and high strength after the HTS test were interpreted with reference to the results of electron probe x-ray microanalyzer (EPMA) analysis. This use of a silver bonding layer may make the fabrication of copper chips simpler than by other protective schemes.     

Development of a thermosonic wire-bonding process for gold wire bonding to copper pads using argon shielding

To improve the bondability and ensure the reliability of Au/Cu ball bonds of the thermosonic (TS) wire-bonding process, an argon-shielding atmosphere was applied to prevent the copper pad from oxidizing. With argon shielding in the TS wire-bonding process, 100% gold wire attached on a copper pad can be achieved at the bonding temperature of 180°C and above. The ball-shear and wire-pull forces far exceed the minimum requirements specified in the related industrial codes. In a suitable range of bonding parameters, increasing bonding parameters resulted in greater bonding strength. However, if bonding parameters exceed the suitable range, the bonding strength is deteriorated. The reliability of the high-temperature storage (HTS) test for Au/Cu ball bonds was verified in this study. The bonding strength of Au/Cu ball bonds increases slightly with prolonged storage duration because of diffusion between the gold ball and copper pad during the HTS test. As a whole, argon shielding is a successful way to ensure the Au/Cu ball bond in the TS wire-bonding process applied for packaging of chips with copper interconnects.     

Evaluation of reliability and metallurgical integrity of wire bonds and lead free solder joints on flexible printed circuit board sample modules

This paper presents a study of the optimization of the gold plating thickness for the use of both wire bonding and soldered interconnects on a flexible printed circuit board sample module. Wire bondability is typically better, when the gold plating thickness is greater than 30 μin.; however, the risk of problems with solder joint embrittlement becomes a concern with thick gold plating. In order to better understand the effect of the gold plating thickness on wire bondability and solder joint embrittlement, an evaluation was performed on samples with three ranges of gold plating thicknesses (10–20 μin., 20–30 μin., and 30–45 μin.), on flexible printed circuit board (PCB), substrates. Mechanical shear testing and metallurgical analyses were conducted on chip component solder joints in this three thickness gold study. Thermal shock and drop testing were conducted to evaluate the reliability of the sample modules. Drop testing is especially critical for determining the reliability of the sample modules, which are used in portable consumer electronics products. Reliability testing and metallurgical analyses have been performed to characterize the effect of gold embrittlement on the mechanical integrity of the solder joints with a gold content ranging from 1 to 4 wt.%.     

Facing the challenge of designing for Cu/low-k reliability

With the decrease of the feature size to 90 nm and lower new materials are introduced in the waferfabs. Copper replaced aluminium and low-k dielectrics served as a better isolator. But this change has serious consequences for the structural integrity of the IC interconnects after processing and package manufacturing. Due to the fact that the new materials have substantially different thermo-mechanical properties, sufficient reliability performance for the IC package becomes a key factor. This paper presents solutions for the reliability problems faced due to the introduction of Cu/low-k as a consequence of the packaging processes. The packaging processes that significantly endanger the Cu/low-k integrity are probing, wire bonding, and moulding. Examples of the reliability issues are presented; these are deep probe marks, metal peel off, and/or pulled-off IC layers. To solve these issues, packaging process conditions and material properties are tuned to better fit with the Cu/low-k technology. Hopefully, the lessons learned and the newly developed state-of-the-art modelling and experimental techniques will enable the industry to release the lower node technologies such as CMOS065.     

Development of capillaries for wire bonding of low-k ultra-fine-pitch devices

Although wire bonding has been a well-established technology for many years, the bonding tool design becomes more complex and the process is very sensitive for wire bonding of low-k ultra-fine-pitch microelectronics devices. In this study, two different types of external transition profile were considered in order to use lower ultrasonic-generator power for preventing pad damage. The ultrasonic vibration displacements of the capillaries were measured using a laser interferometer. The measurement results revealed that the amplification factor (the ratio of the vibration displacement at the capillary tip to that at the transducer point) of a capillary with a small radius transition between the bottleneck angle and the main taper angle was 37% higher than that of a capillary with a sharp transition, and this led to satisfactory results in terms of ball size, ball height, ball shear and stitch pull. To solve the ball lift problem for wire bonding of low-k ultra-fine-pitch devices, optimization of the capillary internal profile was attempted to improve bondability. Actual bonding responses were tested. Compared to a standard design, a capillary with a smaller chamfer angle, a larger inner chamfer and a larger chamfer diameter could increase the percentage of the intermetallic compound in the bond interface. Metal pad peeling and ball lift failures were not observed after an aging test.     

Design, assembly and reliability of large die and fine-pitch Cu/low-k flip chip package

This paper reports the design, assembly and reliability assessment of 21 × 21 mm² Cu/low-k flip chip (65 nm node) with 150 μm bump pitch and high bump density. To reduce the stress from the solder bump pad to low-k layers, Metal Redistribution Layer (RDL) and Polymer Encapsulated Dicing Lane (PEDL) are applied to the Cu/low-k wafer. Lead-free Sn2.5Ag, high-lead Pb5Sn and Cu-post/Sn37Pb bumps are evaluated as the first-level interconnects. It is found that the flip chip assembly of high-lead bumped test vehicle requires the right choice of flux and good alignment between the high-lead solder bumps and substrate pre-solder alloy to ensure proper solder bump and substrate pre-solder alloy wetting. Joint Electron Device Engineering Council (JEDEC) standard reliability is performed on the test vehicle with different first-level interconnects, underfill materials and PEDL.By integrating PEDL to the Cu/low-k chip, the reliability performance of the flip chip package has been improved by almost two times. This paper has demonstrated Moisture Sensitivity Test-Level 2 (MST-L2) qualified large die and fine-pitch Cu/low-k flip chip package. The presented results are significant for the development of flip chip packaging technologies for future advanced Cu/low-k generations.     

Process windows for low-temperature Au wire bonding

The process windows are presented for low-temperature Au wire bonding on Au/Ni/Cu bond pads of varying Au-layer thicknesses metallized on an organic FR-4 printed circuit board (PCB). Three different plating techniques were used to deposit the Au layers: electrolytic plating, immersion plating, and immersion plating followed by electrolytic plating. Wide ranges of wire bond force, bond power, and bond-pad temperature were used to identify the combination of these processing parameters that can produce good wire bonds, allowing the construction of process windows. The criterion for successful bonds is no peel off for all 20 wires tested. The wire pull strengths and wire deformation ratios are measured to evaluate the bond quality after a successful wire bond. Elemental and surface characterization techniques were used to evaluate the bond-pad surfaces and are correlated to wire bondability and wire pull strength. Based on the process windows along with the pull strength data, the bond-pad metallization and bonding conditions can be further optimized for improved wire bondability and product yields. The wire bondability of the electrolytic bond pad increased with Au-layer thickness. The bond pad with an Au-layer thickness of 0.7 μm displayed the highest bondability for all bonding conditions used. The bondability of immersion bond pads was comparable to electrolytic bond pads with a similar Au thickness. Although a high temperature was beneficial to wire bondability with a wide process window, it did not improve the bond quality as measured by wire pull strength.     

Analysis of Cu/low-k bond pad delamination by using a novel failure index

For the development of state-of-the-art Cu/low-k CMOS technologies, the integration and introduction of new low-k materials is one of the major bottlenecks owing to the bad thermal and mechanical integrity of these materials and the inherited weak interfacial adhesion. Especially the forces resulting from packaging related processes such as dicing, wire bonding, bumping and molding are critical and can easily result in cracking, delamination and chipping of the IC back-end structure if no appropriate measures are taken. This paper presents a methodology for optimizing the thermo-mechanical reliability of bond pads by using a 3D multi-scale finite element approach. An important characteristic of this methodology is the use of a novel energy-based failure index, which allows a fast qualitative comparison of different back-end structures. The usability of the methodology will be illustrated by a case study in which several bond pad structures are analysed.     

Role of process parameters on bondability and pad damage indicators in copper ball bonding

Cu wire bonding is one of the hottest trends in electronic packaging due to the cost and performance advantages of Cu wire over Au wire. However, there are many challenges to Cu wire bonding, one of which is the increased stress transmitted to the bond pad during bonding. This high stress is not desirable as it leads to pad damage or cratering in the Si under the pad. Another issue is pad splash in which the pad material is squeezed outside the bonded area, which in severe cases can cause Al pad thinning and depletion. To study the root cause of the increased stress, ball bonding is performed with Au and Cu wires using the same levels of ultrasound (USG), bonding force (BF), and impact force (IF). The bonding is performed on a bonding test pad with integrated piezoresistive microsensors and the in situ pad stress is measured in real time. The ultrasonic pad stress did not show any significant difference between the Au and the Cu ball bonding processes. This indicates that the cause of increased stress cannot be attributed to material properties such as hardness alone, and that the differences in bondability and bonding parameters required for the Cu process might be more influential. To achieve optimal bonding results in terms of shear force per unit area, the Cu process requires higher BF and USG settings, which are the main causes of pad damage. To understand the effect of bonding parameters IF, BF, and USG on pad stress, a detailed DOE is conducted with Cu wire. In addition to conventional bonding parameters, the effect of a non-zero USG level applied during the impact portion of the bonding (pre-bleed USG) is investigated. One of the findings is the reduction of pad damage when higher pre-bleed USG levels are used.     

铝键合丝弧高、跨度与可靠性的研究

铝丝键合作为一项半导体产品的封装工艺,被广泛用于连接半导体器件内具有铝焊盘4的芯片与其它元件。然而,如果产品内铝丝连接设计或者键合工艺参数超出铝丝材料承受能力,会降低产品的可靠性。本文以铝丝键合失效案例为起始,设计铝丝键合工艺研究试验,对铝丝所能承受的最高弧度和最大跨度进行了讨论和总结,并提出修改意见。通过对比调整前后产品内铝键合丝拉断力和拉断力标准差,证明修改后该产品可靠性明显得到了提升,也论证本文更改建议的正确性。     

Effect of the direct current on microstructure,tensile property and bonding strength of pure silver wires

In the microelectronics assembly and packaging industry, the wire bonding has become an important process to connect lead frames and pads. In the past, gold and copper were the main materials of wire bonding. However, the cost of gold wires is getting higher nowadays and yet wire bonding cannot be wholly replaced by copper wire; thus silver wires become a novel bonding material in recent years. The reliability test of wires was a static method; this study leads electrical current into the wires to estimate the structural changing and interface properties of Al pads (positive and negative pad). After leading 90% critical fusing current density (CFCD) into a 23 μm silver wire, some grains of silver wire had grown up and formed into equal-diameter grains (EDG). After the current test, the fracture position of bonded wires moved from heat affect zone (HAZ) of electric flame-off (EFO) to the neck of HAZ. Otherwise, the current test would reduce the tensile strength of wire. The bonding strength of the positive pad was lower than that of the negative pad. The intermetallic compound (IMC) of bonding interface was AgAl₂.     

表面特性对PBGA软金丝键合点可焊性的影响

一级封装中最流行的互连技术仍为丝焊。引线键合的效率主要依赖于受表面特性影响的键合点的可焊性。在最近的研究中,我们调查了表面特性对金-金超声压焊系统的影响。表面特性包括金层厚度,表面硬度和粗糙度、有机物杂质及金属杂质。对两个样本间的不同特性进行比较。确定金表面特性的粗糙度依赖于镍层的外形结构。焊料掩膜逸出气体对可焊性具有负面影响,等离子清洗能够有效地去除有机物杂质。金层中的杂质将导致不良的可焊性。     

Effects of bonding temperature on the properties and reliabilities of anisotropic conductive films (ACFs) for flip chip on organic substrate application

The effects of bonding temperatures on the composite properties and reliability performances of anisotropic conductive films (ACFs) for flip chip on organic substrates assemblies were studied. As the bonding temperature decreased, the composite properties of ACF, such as water absorption, glass transition temperature (T_g), elastic modulus (E′) and coefficient of thermal expansion (α), were improved. These results were due to the difference in network structures of cured ACFs which were fully cured at different temperatures. From small angle X-ray scattering (SAXS) test result, ACFs cured at lower temperature, had denser network structures. The reliability performances of flip chip on organic substrate assemblies using ACFs were also investigated as a function of bonding temperatures. The results in thermal cycling test (−55 °C/+150 °C, 1000 cycles) and PCT (121 °C, 100% RH, 96 h) showed that the lower bonding temperature resulted in better reliability of the flip chip interconnects using ACFs. Therefore, the composite properties of cured ACF and reliability of flip chip on organic substrate assemblies using ACFs were strongly affected by the bonding temperature.     

The development of Cu bonding wire with oxidation-resistant metal coating

Although Cu bonding wire excels over Au bonding wire in some respects such as production costs, it has not been widely used because of its poor bondability at second bonds due to surface oxidation. We conceived an idea of electroplating oxidation-resistant metal on the Cu bonding wire to prevent the surface oxidation. The electroplating of Au, Ag, Pd, and Ni over Cu bonding wire all increased bond strengths as expected, but it caused problematic ball shapes except Pd-plated Cu bonding wire. The wire could produce the same ball shape as that of Au bonding wire. It was also proved to have excellent bondability sufficient to replace Au bonding wire. That is, it excelled in bond strengths, defective bonding ratio, and wideness of "Parameter Windows". It also showed the same stability as Au bonding wire in reliability tests, while bonds of Cu bonding wire were deteriorated in a few of the tests. In short, the Pd-plated Cu bonding wire can realize excellent bonding similar to Au bonding wire, while having much lower production costs.     

Efficient damage sensitivity analysis of advanced Cu/low-k bond pad structures by means of the area release energy criterion

For integrated circuit (IC) wafer back-end development, state-of-the-art CMOS-technologies have to be developed and robust bond pad structures have to be designed in order to guarantee both functionality and reliability during waferfab processes, packaging, qualification tests, and, of course, usage. It is now well established that for future CMOS-technologies (CMOS065 and beyond), low-k dielectric materials will be integrated in the back-end structures. However, bad thermal and mechanical integrity as well as weak interfacial adhesion result in major thermo-mechanical reliability issues. Especially the forces resulting from packaging related processes such as dicing, wire bonding, bumping and molding are critical and can easily induce cracking, delamination and chipping of the IC back-end structure when no appropriate precautions are taken. This paper presents an efficient method to describe the damage sensitivity of three-dimensional multi-layered structures. The index that characterizes this failure sensitivity is an energy measure called the Area Release Energy, which predicts the amount of energy that is released upon crack initiation at an arbitrary position along an interface. The benefits of the method are: (1) the criterion can be used as damage sensitivity indicator for complex three-dimensional structures; (2) the criterion is energy-based, thus more accurate than stress-based criteria; (3) unlike recent fracture mechanics approaches, no initial defect size and location has to be assumed a priori. A mesh objectivity condition is formulated resulting from numerical experiments. The method is applied to advanced IC back-end structures, revealing not only the most critical back-end design but also the critical interfaces in the bond pad structures at which delamination might occur. In order to bridge the length scale difference between the wafer level and the back-end structures, a multi-scale method has been implemented in the finite element code MSC.Marc. In this way, effects of e.g., packaging and wire bond loading at the global level can be studied while taking into account the possibility of occurring failure phenomena at the local, back-end level. The validity and applicability of the method will be demonstrated by considering several Cu/low-k back-end structures. The obtained results are in good agreement with experimental observations.