NMOS Compatible Work Function of TaN Metal Gate With Erbium-Oxide-Doped Hafnium Oxide Gate Dielectric

This letter demonstrates reduction in effective work function of tantalum-nitride (TaN) metal gate with erbium-oxide-doped hafnium oxide. We report that TaN effective metal-gate work function can be tuned from Si midgap to the conduction band to meet the work-function requirement of NMOSFETs by incorporating ErO in HfO₂ with an equivalent oxide thickness as low as 1.15 nm. Several other lanthanide-oxide doped hafnium oxides show similar characteristics.     

硫化锌衬底上氧化铪保护膜制备及性能研究

采用磁控溅射法在硫化锌衬底上制备了氧化铪薄膜,并对氧化铪薄膜的结构和性能进行了分析和测试.结果表明,制备的氧化铪薄膜结构为单斜相,膜层致密,在8～12 μm波段对硫化锌衬底的透过率没有明显影响,硬度显著高于衬底的硬度,且与衬底结合良好,适合用作硫化锌的红外保护膜.     

Characterization of Ultrathin Dielectric Films With the Prism-Coupler Method

We demonstrate a technique of applying the prism-coupler method to the characterization of dielectric films that are too thin to support enough guided modes in air for the normal application of the method. The technique is based on applying suitable index-matching liquids on the surface of the thin film to increase the number of effective indexes available for the determination of the refractive index and the thickness of the film. With this technique, even thin films that do not support any guided modes in air can be characterized. We apply the technique to the characterization of polymer thin films as thin as 100-200 nm and discuss its performance and limitation     

不同厚度超薄栅氧化物MOSFET的应力诱导漏电流

研究了不同厚度的超薄栅1.9nm到3.0 nm器件在恒压应力下的栅电流变化.实验结果显示应力诱导漏电流包括两个部分,一部分是由界面陷阱辅助隧穿引起的,另一部分是氧化物陷阱辅助隧穿引起的.     

不同厚度超薄栅氧化物MOSFET的应力诱导漏电流

研究了不同厚度的超薄栅1.9nm到3.0nm器件在恒压应力下的栅电流变化.实验结果显示应力诱导漏电流包括两个部分,一部分是由界面陷阱辅助隧穿引起的,另一部分是氧化物陷阱辅助隧穿引起的.     

一种提高栅氧化物介电常数的方法

从90 nm技术节点开始,等离子氮化SiON栅氧化层被广泛用作先进的CMOS器件制造。作为传统SiO2栅氧化层的替代材料,SiON栅氧化层因其具有较高的介电常数而能有效地抑制硼等栅极掺杂原子在栅氧化层中的扩散。氮化后热退火处理(Post Nitridation Anneal,PNA)是制备等离子氮化SiON栅氧化层的一个重要步骤,主要用于修复晶格损伤并形成稳定Si-N键,同时在氧化氛围下通过界面的二次氧化反应来修复SiO2/Si界面的损伤。本文通过对传统栅氧制备工艺中PNA单一高温退火工艺的温度、气体氛围进行优化,提供了一种通过提高栅氧化物的氮含量来提其高介电常数的方法。实验数据表明,与传统的制备方法相比,采用本方法所制备的SiON栅氧化层中氮含量可以提高30%以上,栅氧界面态总电荷可减少一个数量级,PMOS器件的NBTI寿命t0.1%和t50%可分别提高15.3%和32.4%。     

Mechanical Properties of Robust Ultrathin Silk Fibroin Films

Robust ultrathin multilayer films of silk fibroin were fabricated by spin coating and spin‐assisted layer‐by‐layer assembly and their mechanical properties were studied both in tensile and compression modes for the first time. The ultrathin films were characterized by a high elastic modulus of 6–8 GPa (after treatment with methanol) with the ultimate tensile strength reaching 100 MPa. The superior toughness is also many times higher than that usually observed for conventional polymer composites (328 kJ m^–3 for the silk material studied here versus typical values of < 100 kJ m^–3). These outstanding properties are suggested to be caused by the gradual development of the self‐reinforcing microstructure of highly crystalline β‐sheets, serving as reinforcing fillers and physical crosslinks, a process that is well known for bulk silk materials but it is demonstrated here to occur in ultrathin films as well, despite their limited dimensions. However, the confined state within films thinner than the lengths of the extended domains causes a significantly reduced elasticity which should be considered in the design of nanosized films from silk materials. Such regenerated silk fibroin films with outstanding mechanical strength have potential applications in microscale biodevices, biocompatible implants, and synthetic coatings for artificial skin.     

直接隧穿应力下超薄栅氧MOS器件退化

研究了栅氧厚度为1.4nm MOS器件在恒压直接隧穿应力下器件参数退化和应力感应漏电流退化.实验结果表明,在不同直接隧穿应力过程中,应力感应漏电流(SILC)的退化和Vth的退化均存在线性关系.为了解释直接隧穿应力下SILC的起因,建立了一个界面陷阱和氧化层陷阱正电荷共同辅助遂穿模型.     

直接隧穿应力下超薄栅氧MOS器件退化

研究了栅氧厚度为1.4nm MOS器件在恒压直接隧穿应力下器件参数退化和应力感应漏电流退化. 实验结果表明,在不同直接隧穿应力过程中,应力感应漏电流（SILC）的退化和Vth的退化均存在线性关系. 为了解释直接隧穿应力下SILC的起因,建立了一个界面陷阱和氧化层陷阱正电荷共同辅助遂穿模型.     

过渡金属超薄膜的光学性质及其应用

讨论了单层过渡金属超薄膜以及它与介质膜组成的多层膜的光学特性，对它们进行了定量的分析，并以实例说明了过渡金属超薄膜在中性分光镜、窄带高反滤光片等方面的应用     

硅衬底注氮方法制备超薄SiO2栅介质

利用栅氧化前在硅衬底内注氮可抑制氧化速率的方法,制得3.4nm厚的SiO2栅介质,并将其应用于MOS电容样品的制备.研究了N+注入后在Si/SiO2中的分布及热退火对该分布的影响;考察了不同注氮剂量对栅氧化速率的影响.对MOS电容样品的I-V特性,恒流应力下的Qbd,SILC及C-V特性进行了测试,分析了不同氧化工艺条件下栅介质的性能.实验结果表明:注氮后的热退火过程会使氮在Si/SiO2界面堆积;硅衬底内注入的氮的剂量越大,对氧化速率的抑制作用越明显;高温栅氧化前进行低温预氧化的注氮样品较不进行该工艺步骤的注氮样品具有更低的低场漏电流和更小的SILC电流密度,但二者恒流应力下的Qbd值及高频C-V特性相近.     

硅衬底注氮方法制备超薄SiO2栅介质

利用栅氧化前在硅衬底内注氮可抑制氧化速率的方法,制得3.4nm厚的SiO2栅介质,并将其应用于MOS电容样品的制备.研究了N 注入后在Si/SiO2中的分布及热退火对该分布的影响;考察了不同注氮剂量对栅氧化速率的影响.对MOS电容样品的I-V特性,恒流应力下的Qbd,SILC及C-V特性进行了测试,分析了不同氧化工艺条件下栅介质的性能.实验结果表明:注氮后的热退火过程会使氮在Si/SiO2界面堆积;硅衬底内注入的氮的剂量越大,对氧化速率的抑制作用越明显;高温栅氧化前进行低温预氧化的注氮样品较不进行该工艺步骤的注氮样品具有更低的低场漏电流和更小的SILC电流密度,但二者恒流应力下的Qbd值及高频C-V特性相近.     

Electrical Characteristics of the HfAlON Gate Dielectric With Interfacial UV-Ozone Oxide

In this letter, the electrical properties of a HfAlON dielectric with UV-O₃ interfacial oxide were comprehensively studied and then compared with those of a HfAlON dielectric with interfacial chemical oxide. In the comparison of dielectric characteristics including leakage current density, transconductance, subthreshold swing, saturation drain current, effective electron mobility, and constant voltage stress reliabilities, the results clearly indicate that high-density interfacial UV-O₃ oxide is beneficial in reducing both bulk and interface traps as well as diminishing stress-induced trap generation, and possesses a high potential to be integrated with further high-kappa dielectric applications.     

HfO2高K栅介质薄膜的电学特性研究

研究了高 K(高介电常数 )栅介质 Hf O2 薄膜的制备工艺 ,制备了有效氧化层厚度为 2 .9nm的超薄MOS电容。对电容的电学特性如 C-V特性 ,I-V特性 ,击穿特性进行了测试。实验结果显示 :Hf O2 栅介质电容具有良好的 C-V特性 ,较低的漏电流和较高的击穿电压。因此 ,Hf O2 栅介质可能成为 Si O2 栅介质的替代物。     

N_2和NH_3退火对铪铝氧栅介质C-V特性的影响

采用原子层淀积(ALD)的方法在Si(100)衬底上制备了铪铝氧(HfAlO)高介电常数介质,并研究了N2和NH3退火对于介质薄膜的影响。改变原子层淀积的工艺,制备了三组含有不同Al∶Hf原子比的铪铝氧(HfAlO)高介电常数介质。电容电压特性(C-V)测试表明,薄膜的积累电容密度随着薄膜中Al∶Hf原子比的减少而增加。实验表明,用N2和NH3对样品进行淀积后退火,可以减小等效电容厚度(CET)、降低固定正电荷密度以及减小滞回电压,从而有效地提高了介质薄膜的电学特性。     

液晶聚合物薄膜的介电性能

研究了两种液晶聚合物薄膜的介电性能。结果表明,液晶聚合物的介电常数随频率的增加而缓慢变小,高温下的介电常数较大。介电损耗在一定的温度范围内（室温至３５０℃）出现峰值,峰值位置随频率的增加向高温方向移动。     

超薄栅MOS结构恒压应力下的直接隧穿弛豫谱

随着器件尺寸的迅速减小,直接隧穿电流将代替FN电流而成为影响器件可靠性的主要因素.根据比例差值算符理论和弛豫谱技术,针对直接隧穿应力下超薄栅MOS结构提出了一种新的弛豫谱--恒压应力下的直接隧穿弛豫谱(DTRS).该弛豫谱保持了原有弛豫谱技术直接、快速和方便的优点,能够分离和表征超薄栅MOS结构不同氧化层陷阱,提取氧化层陷阱的产生/俘获截面、陷阱密度等陷阱参数.直接隧穿弛豫谱主要用于研究直接隧穿注入的情况下超薄栅MOS结构中陷阱的产生和复合,为超薄栅MOS结构的可靠性研究提供了一强有力工具.     

超薄栅MOS结构恒压应力下的直接隧穿弛豫谱

随着器件尺寸的迅速减小 ,直接隧穿电流将代替 FN电流而成为影响器件可靠性的主要因素 .根据比例差值算符理论和弛豫谱技术 ,针对直接隧穿应力下超薄栅 MOS结构提出了一种新的弛豫谱——恒压应力下的直接隧穿弛豫谱 (DTRS) .该弛豫谱保持了原有弛豫谱技术直接、快速和方便的优点 ,能够分离和表征超薄栅 MOS结构不同氧化层陷阱 ,提取氧化层陷阱的产生 /俘获截面、陷阱密度等陷阱参数 .直接隧穿弛豫谱主要用于研究直接隧穿注入的情况下超薄栅 MOS结构中陷阱的产生和复合 ,为超薄栅 MOS结构的可靠性研究提供了一强有力工具 .     

Ultrathin SWNT Films with Tunable,Anisotropic Transport Properties

Directional transport properties at the nanoscale remain a challenge, primarily due to issues pertaining to control over the underlying anisotropy and scalability to macroscopic scales. Here, we develop a facile approach based on template‐guided fluidic assembly of high mobility building blocks – single walled carbon nanotubes (SWNTs) – to fabricate ultrathin and anisotropic SWNTs films. A major advancement is the complete control over the anisotropy in the assembled nanostructure, realized by three‐dimensional engineering of the dip‐coated SWNTs ultrathin film into alternating hydrophilic and hydrophobic microline patterns with prescribed intra/inter‐line widths and line thicknesses. Variations in the contact line profile results in an evaporation‐controlled assembly mechanism that leads to alternating, and more importantly, contiguous SWNTs networks. Evidently, the nanoscopic thickness modulations are direct reflections of the substrate geometry and chemistry. The nanostructured film exhibits significant anisotropy in electrical and thermal transport properties as well as an optically transparent nature, as revealed by characterization studies. The direct interplay between the anisotropy and the 3D microline patterns of the substrate combined with the wafer‐level scalability of the fluidic assembly allows us to tune the transport properties for a host of nanoelectronic applications.     

Ultrathin Supported Lipid Monolayer with Unprecedented Mechanical and Dielectric Properties

The development of ultrathin dielectrics for low power electronics operations, flexible and printed electronics, and field‐effect‐transistor‐based sensors is still a challenge. Here, monolayers of engineered lipids supported on silicon are reported presenting exceptional mechanical and dielectric properties. The lipid monolayers are stabilized using a simple procedure based on a two‐stage reticulation process in both their aliphatic chains and their head‐group. With a thickness lower than 3 nm, such layers are demonstrated to offer exceptional mechanical and dielectric stability with unprecedented low leakage current and dielectric strength. Surprisingly, the mechanical and dielectric pressures required to rupture/breakdown the monolayers are shown to be similar. These results suggest the presence of a strong correlation between mechanical and dielectric properties, as well as between the mechanisms of rupture and breakdown.