低位线摆幅的低功耗SRAM设计

本文提出了一种低位线摆幅（LVBS）的低功耗SRAM结构。这种SRAM采用电荷分享方法降低线电压幅值，在写操作时使得位线电压摆幅减少了50％，从而显著降低了位线动态功耗。同时本文还分析了由于位线电压降低带来的静态噪声容限（SNM）等问题。实验结果表明相比较常规SRAM，LVBS SRAM可以节约30％的动态功耗。     

一种阵列布局优化的256 kb SRAM

介绍了一种阵列布局优化的256 kb(8 k×32位)低功耗SRAM。通过采用分级位线和局部灵敏放大器结构,减少位线上的负载电容;通过电压产生电路,获得写操作所需的参考电压,降低写操作时的位线电压摆动幅度,有效地减少了SRAM读写操作时的动态功耗。与传统结构的SRAM相比,该256 kb SRAM的写功耗可减少37.70 mW。     

一种高速只读存储器拓扑结构的设计

随着只读存储器密度越来越大,对读取速度的要求越来越高,位线大电容逐渐成为影响只读存储器读取速度的关键问题.设计了一种存储器拓扑结构,这种结构通过改变存储单元读取点的位置,能有效避免位线大电容充放电对读取速度的不利影响,极大地缩短了读取周期,提高了只读存储器的读取速度.该拓扑结构的优势在TSMC 0.13μm工艺仿真库里得到验证.     

采用源极增强带带隧穿热电子注入编程的新型p沟选择分裂位线NOR快闪存贮器

提出一种新型的PMOS选择分裂位线NOR结构快闪存贮器,具有高编程速度、低编程电压、低功耗、高访问速度和高可靠性等优点.该结构采用源极增强带带隧穿热电子注入进行编程,当子位线宽度为128位时,位线漏电只有3.5μA左右,每位编程功耗为16.5μW,注入系数为4×10-4,编程速度可达20μs,存贮管的读电流可达60μA/μm以上.分裂位线结构和低编程电压使得该结构具有很好的抗位线串扰特性和可靠性.     

采用源极增强带带隧穿热电子注入编程的新型p沟选择分裂位线NOR快闪存贮器

提出一种新型的PMOS选择分裂位线NOR结构快闪存贮器,具有高编程速度、低编程电压、低功耗、高访问速度和高可靠性等优点.该结构采用源极增强带带隧穿热电子注入进行编程,当子位线宽度为128位时,位线漏电只有3.5μA左右,每位编程功耗为16.5μW,注入系数为4×10-4,编程速度可达20μs,存贮管的读电流可达60μA/μm以上.分裂位线结构和低编程电压使得该结构具有很好的抗位线串扰特性和可靠性.     

6G移动网络中闪存系统的性能优化方案:比特重映射

第6代移动通信技术(6G)网络所产生的海量数据对数据存储带来了全新挑战,推动着存储技术的迅猛发展。与非门(NAND)闪存存储器具有读写速度快,可靠性高等优点,故在6G网络中具有广泛的应用前景。为了提高NAND闪存的可靠性,针对两种不同位线结构的错误特性,该文分别提出基于全位线结构的等精度重映射方案和基于奇偶位线结构的不等精度的重映射方案。仿真结果表明,两种新型比特重映射方案有效提升了闪存的误码性能。基于此,该文所提重映射技术可被视作6G网络中可靠而高效的存储优化技术。     

一种降低高性能SRAM过大位线漏电流的方法

随着半导体工艺的进步,器件特征尺寸不断缩小,晶体管漏电流呈现出增长趋势。高速SRAM位线上,过大的漏电流会引起SRAM的性能出现严重下降,甚至导致SRAM读失效的发生。特别是当位线上积累的漏电流已经超过SRAM的工作电流时,传统方法将趋于失效。提出位线自截断技术来消除过大漏电流对SRAM的不利影响。采用SMIC 65nm CMOS工艺,设计了一款SRAM,通过仿真测试,验证了该方法的正确性。     

一种基于时钟抽取偏置电压技术的存储器位线

基于一种新型时钟延时单元,设计了一种片上存储器的位线。在不增加版图面积的前提下,通过周期性地改变保持管的衬底偏置电压,减小了短路功耗、泄漏功耗和延迟时间,同时增加了电路的抗工艺波动能力。在SMIC 65 nm工艺下,完成了传统位线、改进后的位线以及静态随机存取存储器(SRAM)的设计。仿真结果表明,在1 GHz时钟频率下,改进后的两种位线与传统位线相比,功耗延迟积分别减小了19.1%和15.9%。最后,通过蒙特卡洛分析可知,改进后的位线相比于传统位线具有较强的抗工艺波动能力,即功耗延迟积的方差减小了97.1%。     

磁性随机存储器中的电流磁场分布模型

根据磁性随机存储器(MRAM)设计的实际需要,建立了MRAM中相互垂直的字线和位线电流所产生的磁场的解析分布模型。利用该模型讨论了存储单元与位线间距离(d1),字、位线宽度(w)及字、位线厚度(t)对存储单元自由层表面磁场分布的影响。结果表明,d1或w增大时,自由层表面磁场的强度及非均匀程度都减小。t增大时,自由层表面磁场的强度及非均匀程度都增大。其中d1对磁场分布的影响程序是最大的。该模型为MRAM更精确的器件模拟及器件结构的优化设计工作提供了必要的基础。     

一种提高SRAM写能力的自适应负位线电路设计

随着器件尺寸缩小到纳米级,在SRAM生产过程中,工艺偏差变大会导致SRAM单元写能力变差.针对这一问题,提出了一种新型负位线电路,可以提高SRAM单元的写能力,并通过控制时序和下拉管的栅极电压达到自我调节负位线电压,使负电压被控制在一定范围内.本设计采用TSMC 40nm工艺模型对设计的电路进行仿真验证,结果证明,设计的电路可以改善写能力,使SRAM在电压降到0.66V的时候仍能正常工作,并且和传统设计相比,本电路产生的负电压被控制在一个范围内,有利于提高晶体管的使用寿命,改善良率,节省功耗.     

A Voltage Scalable 0.26 V, 64 kb 8T SRAM With V$_{min}$ Lowering Techniques and Deep Sleep Mode

A voltage scalable 0.26 V, 64 kb 8T SRAM with 512 cells per bitline is implemented in a 130 nm CMOS process. Utilization of the reverse short channel effect in a SRAM cell design improves cell write margin and read performance without the aid of peripheral circuits. A marginal bitline leakage compensation (MBLC) scheme compensates for the bitline leakage current which becomes comparable to a read current at subthreshold supply voltages. The MBLC allows us to lower ${rm V}_{min}$ to 0.26 V and also eliminates the need for precharged read bitlines. A floating read bitline and write bitline scheme reduces the leakage power consumption. A deep sleep mode minimizes the standby leakage power consumption without compromising the hold mode cell stability. Finally, an automatic wordline pulse width control circuit tracks PVT variations and shuts off the bitline leakage current upon completion of a read operation.      

A precharged-capacitor-assisted sensing (PCAS) scheme with novellevel controllers for low-power DRAMs

A precharged capacitor-assisted sensing (PCAS) scheme suitable for low-power DRAM using boosted-sense ground (BSG) is proposed. In this scheme, the data on bitlines are sensed with the assistance of precharged capacitors. Precise data level generation is achieved with sense speed 4.2 ns faster than the conventional scheme in the case that bitline swing is 1.4 V. Necessary decoupling capacitors can be efficiently implemented in memory arrays by using junction capacitors between well and substrate so that the area penalty of decoupling capacitors can be minimized. To keep sensed data stable, two types of level controllers are introduced. A voltage downconverter (VDC) with a current mirror discharger (CMD) compensates for the change of both data levels during write/read operations. A level controller with charge transfer amplifier (CTA) prevents the BSG level from falling during the row active period. The two level controllers greatly improve data-retention characteristics     

A bitline leakage compensation scheme for low-voltage SRAMs

A bitline leakage current of an SRAM, induced by leakage current of the transmission transistors in the cells that are associated with the bitline, increases as the threshold voltage (V_TH) of the transistors is reduced for high performance at low power-supply voltage (V_DD). The increased bitline leakage causes slow or incorrect read/write operation of an SRAM because the leakage current acts as noise current for a sense amplifier. In this paper, the problem has been solved from a circuitry point of view, and the scheme which detects the bitline leakage current in a precharge cycle and compensates for it during a read/write cycle is proposed. Employing this scheme, the SRAM with 360-μA bitline leakage current can perform a read/write operation at the same speed as one that has no bitline leakage current. This enables a 0.1-V reduction in V_TH, and keeps the V_TH and delay scalability of a high-performance SRAM in technology progress. An experimental 8-Kb SRAM with 256 rows is fabricated in a 0.25-μm CMOS technology, which demonstrates the effectiveness of the scheme     

SRAM bitline circuits on PD SOI: advantages and concerns

This paper presents a study of sub-0.25-μm CMOS SRAM bitline circuitry on partially depleted (PD) silicon-on-insulator (SOI) technology. SOI implementations outperform conventional bulk ones due to significant reduction of collective device junction capacitance on the bitlines. Floating body effects are investigated for both read and write cycles. Array content dependent behaviors are identified for the first time and analyzed with worst-case temporal and spatial pattern combinations     

Compact wide bandwidth dual-port DRAM architecture suitable for mobile multimedia processors

A DRAM architecture capable of providing dual-port interface is presented. The architecture utilises a novel global bitline scheme to obtain a very wide data bandwidth not possible using traditional DRAM architectures. Furthermore, the area penalty is minimised by using a conventional one-transistor one-capacitor cell coupled with special sensing units that have 84.6% more transistor count. The architecture allows simultaneous read and write access using a conventional two-metal DRAM fabrication process.     

Variation resilient subthreshold SRAM cell design technique

This article presents a circuit technique for designing a variability resilient subthreshold static random access memory (SRAM) cell. The architecture of the proposed cell is similar to the conventional 10T SRAM cell with the exception that dynamic threshold MOS is used for the read/write access FETs and cell content body bias scheme is used for bitline droppers (FETs used to drop bitlines). Moreover, the proposed bitcell utilises single differential port unlike conventional 10T bitcell which utilises dual differential ports. The proposed design offers 2.1× improvement in T _RA (read access time) and 3.2× improvement in T _WA (write access time) compared to CON10T at iso-device-area and 200?mV. It exhibits three roots in its read voltage transfer characteristic (VTC) even at 150?mV showing its ability to function as a bistable circuit. The combination of write and read VTCs for write static noise margin of the proposed design also shows single root signifying its write-ability even at 150?mV. It proves its robustness against process variations by featuring narrower spread in T _RA distribution (by 1.3×) and in T _WA distribution (by 1.2×) at 200?mV.     

A 500-MHz multi-banked compilable DRAM macro with direct write and programmable pipelining

This work describes a 500-MHz compiled eDRAM macro offered in a 90-nm logic-based process. The macro architecture is optimized for high bandwidth while enabling compilation in bank and data-word dimensions. A direct write scheme simultaneously improves random bank cycle time and row access time without signal loss. The benefits of ground sensing, reference cells, and bitline twisting was reviewed. A variable stage pipeline extends the macro bandwidth while offering flexibility in clock frequencies. The redundancy system is modified to support direct write and piping. Finally, BIST was enhanced to utilize electrically blown fuses, enabling one-touch test and repair. Hardware results was presented.     

A replica technique for wordline and sense control in low-powerSRAM's

With the migration toward low supply voltages in low-power SRAM designs, threshold and supply voltage fluctuations will begin to have larger impacts on the speed and power specifications of SRAM's. We present techniques based on replica circuits which minimize the effect of operating conditions' variability on the speed and power. Replica memory cells and bitlines are used to create a reference signal whose delay tracks that of the bitlines. This signal is used to generate the sense clock with minimal slack time and control wordline pulsewidths to limit bitline swings. We implemented the circuits for two variants of the technique, one using bitline capacitance ratioing in a 1.2-μm 8-kbyte SRAM, and the other using cell current ratioing in a 0.35-μm 2-kbyte SRAM. Both the RAM's were measured to operate over a wide range of supply voltages, with the latter dissipating 3.6 mW at 150 MHz at 1 V and 5.2 μW at 980 kHz at 0.4 V     

A 0.2 V, 480 kb Subthreshold SRAM With 1 k Cells Per Bitline for Ultra-Low-Voltage Computing

A 2 muW, 100 kHz, 480 kb subthreshold SRAM operating at 0.2 V is demonstrated in a 130 nm CMOS process. A 10-T SRAM cell allows 1 k cells per bitline by eliminating the data-dependent bitline leakage. A virtual ground replica scheme is proposed for logic "0" level tracking and optimal sensing margin in read buffers. Utilizing the strong reverse short channel effect in the subthreshold region improves cell writability and row decoder performance due to the increased current drivability at a longer channel length. The sizing method leads to an equivalent write wordline voltage boost of 70 mV and a delay improvement of 28% in the row decoder compared to the conventional sizing scheme at 0.2 V. A bitline writeback scheme was used to eliminate the pseudo-write problem in unselected columns.     

A 1.6 GB/s DDR2 128 Mb Chain FeRAM With Scalable Octal Bitline and Sensing Schemes

An 87.7 mm² 1.6 GB/s 128 Mb chain FeRAM with 130 nm 4-metal CMOS process is demonstrated. In addition to small bitline capacitance inherent to chain FeRAM architecture, three new FeRAM scaling techniques - octal bitline architecture, small parasitic capacitance sensing scheme, and dual metal plateline scheme - reduce bitline capacitance from 100 fF to 60 fF. As a result, a cell signal of ±220 mV is achieved even with the small cell size of 0.252 ?m². An 800 Mb/s/pin read/write bandwidth at 400 MHz clock is realized by installing SDRAM compatible DDR2 interface, and performance is verified by simulation. The internal power-line bounce noise due to 400 MHz clock operation is suppressed to less than 50 mV by an event-driven current driver, which supplies several hundreds of mA of current within 2 ns response. The precise timing and voltage controls are achieved by using the data stored in a compact FeRAM-fuse, which consists of extra FeRAM memory cells placed in edge of normal array instead of conventional laser fuse links. This configuration minimizes area penalty to 0.2% without cell signal degradation.