Bulk-driven floating-gate and bulk-driven quasi-floating-gate techniques for low-voltage low-power analog circuits design

In this paper, novel non-conventional techniques,¹ named by the author of this paper “bulk-driven floating-gate (BD-FG)” MOS transistor (MOST) and “bulk-driven quasi-floating-gate (BD-QFG) MOST” for low-voltage (LV) low-power (LP) analog circuit design are presented. These novel techniques appear as a good solution to merge the advantages of floating-gate (FG) and quasi-floating-gate (QFG) with the advantages of bulk-driven (BD) technique and suppress their disadvantages. Consequently, the transconductance and transient frequency of BD-FG and BD-QFG MOSTs approach the conventional gate driven (GD) MOST values. Furthermore, a novel LV LP class AB second generation current conveyor based on BD-FG MOST is presented in this paper as an example. The supply voltage is only ±0.4 V with a rail-to-rail voltage swing capability and total power consumption of mere 10 μW. PSpice simulation results using the 0.18 μm P-well CMOS technology are included to confirm the attractive properties of these new techniques.     

单片化低压低功耗Si CMOS运算放大器的实现

基于新型的折叠共栅共源PMOS差分输入级拓扑、轨至轨AB类低压CMOS推挽输出级模型、低压低功耗LV/LP技术特别考虑和EDA平台的实验设计与模拟仿真,并设计配置了先进的Si 2 mm P阱硅栅CMOS集成工艺技术。已经得到一种具有VT = 0.7 V、电源电压1.1~1.5 V、静态功耗典型值330 mW、75 dB开环增益和945 kHz单位增益带宽的LV/LP运算放大器。该运放可应用于ULSI库单元和诸多相关技术领域,其实践有助于Si CMOS低压低功耗集成电路技术的进一步开发与交流。     

Low-voltage and low-power circuit design for mixed analog/digitalsystems in portable equipment

This paper describes low-voltage and low-power (LV/LP) circuit design for both analog LSI's and digital LSI's which are used in mixed analog/digital systems in portable equipment. We review some LV/LP circuits used in digital LSI's, such as general logic gate, DSP, and DRAM, and others used in analog LSI's, such as operational amplifiers, video-signal processing circuits, A/D and D/A converters, filters, and RF circuits, along with a wide range of items used in recently developed LSI's. Since analog circuits have fundamental difficulties in reducing the operating voltage and the power consumption, in spite of recent progress in LV/LP circuit techniques, these difficulties will be a major issue for decreasing the total power consumption of some mixed analog/digital systems used in portable equipment     

LV/LP CMOS Four-Quadrant Analog Multiplier Cell in Modified Bridged-Triode Scheme

A new LV/LP CMOS four-quadrant analog multiplier designed in a modified bridged-triode scheme (MBTS) is presented. Its bi-directional bridged structure brings several benefits in terms of good linearity, lower voltage operation/power consumption, less total harmonic distortions and wider frequency response. The fabricated chip in TSMC 0.35 m n-well SPQM CMOS technology has a nonlinearity error less than 42 dB over ±0.5 V input range under a nominal supply voltage of ±1.5 V, and consumes the total power dissipation of 2.7 mW.     

LV/LP CMOS Four-Quadrant Analog Multiplier Cell in Modified Bridged-Triode Scheme

A new LV/LP CMOS four-quadrant analog multiplier designed in a modified bridged-triode scheme (MBTS) is presented. Its bi-directional bridged structure brings several benefits in terms of good linearity, lower voltage operation/power consumption, less total harmonic distortions (THD) and wider frequency response. The fabricated chip in TSMC 0.35 m n-well SPQM CMOS technology has a nonlinearity error less than 42 dB over ±0.5 V input range under a nominal supply voltage of ±1.5 V,and consumes the total power dissipation of 2.7 mW.     

Evolution of a CMOS Based Lateral High Voltage Technology Concept

This work describes the evolution of a CMOS based lateral high voltage (HV) technology concept, where the HV part is integrated in a low voltage (LV) CMOS technology. The starting point is an existing substrate related state of the art 0.35 μm LV CMOS technology (C35) which is optimized for digital and analog applications. The technology covers two different gate oxide thicknesses which allow to control two LV logic levels with different gate voltages and drain voltages (max.V_GS=max.V_DS=3.3V, max.V_GS=max.V_DS=5.5 V). The key requirement for the HV integration is to preserve the LV design rules (DR) and the LV transistor parameters. Only in this case it is possible to reuse the digital and analog intellectual property (IP) blocks. The major challenge of this integration is to overcome the relatively high surface concentration of the 0.35 μm CMOS process which defines the threshold voltages and the short channel effects. Because the HV devices use the same channel formation like the LV devices, a process concept for the drift region connection to the channel is the key point in this integration approach. A benchmark for the process complexity is given by the mask count (low volume production) and the number of alignments (high volume production). Starting from a very simple approach n-channel HV transistors are described which can be integrated in the substrate related LV CMOS concept without adding additional masks. During the next steps the LV CMOS process is modified continuously using additional masks and alignment steps. From each step to step the new HV properties are explained and the trade-off between process complexity and device performance is discussed.     

A novel low-voltage low-power fully differential voltage and current gained CCII for floating impedance simulations

In this paper we present a new current-mode basic building block that we named voltage and current gained second generation current conveyor (VCG-CCII). The proposed active block allows to control and tune both the CCII current gain and the voltage gain through external control voltages. It has been designed, at transistor level in a standard CMOS technology (AMS 0.35 μm), with a low single supply voltage (2 V), as a fully differential active block. The proposed integrated solution, having both low-voltage (LV) and low-power (LP) characteristics, can be applied with success in suitable IC applications such as floating capacitance multipliers and floating inductance simulators, utilizing a minimum number of active components (one and two, respectively). Simulation results, related to floating impedance simulators, are in good agreement with the theoretical expectations.     

Hardware design of motion data decoding process for H.264/AVC

In H.264/AVC, motion data can be basically derived by the following two schemes: one is a typical spatial prediction scheme based on the DPCM and the other is a sophisticated spatiotemporal prediction scheme for the skipped motion data, formally referred to as a direct mode. We verified through instruction level profiling that when these schemes are combined with various H.264/AVC coding techniques, the computational burden to derive the motion data could be considerably aggravated. Specifically, its computational complexity amounts to maximally 55% of that of the overall syntax parsing process. In this paper, we aim at an efficient hardware design of the motion data decoding process for H.264/AVC, for which all the key design considerations are addressed in detail and respective rational answers are presented. As comparing the resulting hardware design with the processor-based solution, its effectiveness was clearly demonstrated. The proposed design was implemented with 43.2 K logic gates and three on-chip memories of 3584 bits using Samsung Semiconductor’s Standard Cell Library in 65 nm L6LP process technology (SS65LP), and was capable of operating the H.264/AVC high-profile video bitstream of 1080p@60fps at 100 MHz consuming 843 μW.     

Saw minimum peak sidelobe filter for 15-bitM-sequence phase code signals

This paper presents computation results of the minimum peak sidelobe filter (LP filter) for the 15-bitM-sequence phase coded signal with feedback connection [4,3,0] and initial condition 1001. The design of the filter resorts to the linear programming method. The peak sidelobe level is reduced to −21.47 dB by the LP filter of length 15, and is 7.49 dB lower than that by the matched filter. The LP filter can suppress the peak sidelobe even more by increasing its length. The minimum peak sidelobe filter for the 15-bitM-sequence phase coded signal (initial condition 1001) has been implemented with a surface acoustic wave (SAW) device. Experiments show that the peak sidelobe level of the manufactured filter is −19 dB and, thus, only differs from the theoretical value of −21.47 dB by 2.47 dB.     

Smart Laser-Writable Micropatterns with Multiscale Photo/Moisture Reconstructible Structure

The design of a dynamic, versatile, convertible, and responsive micropatterned system is realized by a photo/moisture reconstructible multiscale film-substrate bilayer structure. Specifically, a hydrophilic polyvinyl alcohol (PVA)/laponite (LP) thin film is covalently bonded to a photothermally active polydimethylsiloxane (PDMS)/carbon black (CB) soft substrate. A laser engraver can inscribe programmable aligned micro-wrinkles by manipulating laser power and spatiotemporal control. These wrinkles can be modulated into three distinct systems 1) moisture erasable and laser re-writable wrinkles; 2) moisture driven reversible wrinkles; 3) moisture resistant wrinkles, which are achieved by controlling a) the moisture resistance of PVA; b) the dimensional stability of PVA/LP film regulated by the LP nanostructure, which can be adjusted by the laser power and the LP ratio. This programmable system can be applied in information encryption/recording and as a moisture responsive electrical switch, offering new routes for the modulations and applications of next generation smart materials.     

Design of transimpedance low-pass filters

The input of a transimpedance filter is a current signal, while its output is a voltage signal. In this article, a design method for a transimpedance filter is introduced. Also, the topologies and calculation methods of the parameters of three biquadratic transimpedance low-pass (LP) filter circuits are presented in detail, according to the value of Q which is low or medium or high. As for the high-order filter, it can be designed by transimpedance LP biquad section as first stage cascaded with voltage-mode LP filters. Finally, to verify the effectiveness of the design, a design example of a high-order transimpedance LP filter is given.     

On the SiO2-based gate-dielectric scaling limit forlow-standby power applications in the context of a 0.13 μm CMOS logictechnology

This paper describes a leading-edge 0.13 μm low-leakage CMOS logic technology. To achieve competitive off-state leakage current (I _off) and gate delay (T_d) performance at operating voltages (V_cc) of 1.5 V and 1.2 V, devices with 0.11 μm nominal gate length (L_g-nom) and various gate-oxide thicknesses (T_ox) were fabricated and studied. The results show that low power and memory applications are limited to oxides not thinner than 21.4 Å in order to keep acceptable off-state power consumption at V_cc=1.2 V. Specifically, two different device designs are introduced here. One design named LP (T_ox=26 Å) is targeted for V_cc=1.5 V with worst case I_off <10 pA/μm and nominal gate delay 24 ps/gate. Another design, named LP1 (T_ox=22 Å) is targeted for V_cc =1.2 V with worst case I_off<20 pA/μm and nominal gate delay 27 ps/gate. This work demonstrates n/pMOSFETs with excellent 520/210 and 390/160 μA/μm nominal drive currents at V_cc for LP and LP1, respectively. Process capability for low-power applications is demonstrated using a CMOS 6T-SRAM with 2.43 μm² cell size. In addition, intrinsic gate-oxide TDDB tests of LP1 (T _ox=22 Å) demonstrate that gate oxide reliability far exceeding 10 years is achieved for both n/pMOSFETs at T=125°C and V _cc=1.5 V     

Design of AT‐DMB Baseband Receiver SoC

This paper presents the design of an advanced terrestrial digital multimedia broadcasting (AT‐DMB) baseband receiver SoC. The AT‐DMB baseband is incorporated into a hierarchical modulation scheme consisting of high priority (HP) and low priority (LP) stream decoders. The advantages of the hierarchical modulation scheme are backward compatibility and an enhanced data rate. The structure of the HP stream is the same as that of the conventional T‐DMB system; therefore, a conventional T‐DMB service is possible by decoding multimedia data in an HP stream. An enhanced data rate can be achieved by using both HP and LP streams. In this paper, we also discuss a time deinterleaver that can deinterleave data for a time duration of 384 ms or 768 ms. The interleaving time duration is chosen using the LP symbol mapping scheme. Furthermore, instead of a Viterbi decoder, a turbo decoder is adopted as an inner error correction system to mitigate the performance degradation due to a smaller symbol distance in a hierarchically modulated LP symbol. The AT‐DMB baseband receiver SoC is fabricated using 0.13 µm technology and shows successful operation with a 50 mW power dissipation.     

A 660-μW 50-Mops 1-V DSP for a hearing aid chip set

This article presents the flow and techniques used to design a low-power digital signal processor chip used in a hearing aid system implementing multiband compression in 20 bands, pattern recognition, adaptive filtering, and finescale noise cancellation. The pad limited 20 mm² chip contains 1.3 M transistors and operates at 2.5 MHz under 1.05-V supply voltage. Under these conditions, the DSP consumes 660 μW and performs 50 million 22-bit operations per second, therefore achieving 0.013 mW/Mops (milli-watts per million operations), which is a factor of seven better than prior results achieved in this field. The chip has been manufactured using a 0.25-μm 5-metal 1-poly process with normal threshold voltages. This low-power application-specific integrated circuit (ASIC) relies on an automated algorithm to silicon flow, low-voltage operation, massive clock gating, LP/LV libraries, and low-power-oriented architectural choices     

A low power, low noise figure quadrature demodulator for a 60 GHz receiver in 65-nm CMOS technology

This paper presents the design of a low power (LP) and a low noise figure (NF) quadrature demodulator with an on-chip frequency divider for quadrature local oscillator (LO) signal generation. The transconductance stage of the mixer is implemented by an AC-coupled self-bias current reuse topology. On-chip series inductors are employed at the gate terminals of the differential input transconductance stage to improve the voltage gain by enhancing the effective transconductance. The chip is implemented in 65-nm LP CMOS technology. The demodulator is designed for an input radio frequency (RF) band ranging from 10.25 to 13.75 GHz. A fixed LO frequency of 12 GHz down-converts the RF band to an intermediate frequency (IF) band ranging from DC to 1.75 GHz. From 10 MHz to 1.75 GHz the demodulator achieves a voltage conversion gain (VCG) ranging from 14.2 to 13.2 dB, and a minimum single-sideband NF (SSB-NF) of 9 dB. The measured third-order input intercept point (IIP₃) is -3.3 dBm for a two-tone test frequency spacing of 1 MHz. The mixer alone draws a current of only 2.5 mA, whereas the complete demodulator draws a current of 7.18 mA from a 1.2 V supply. The measurement results for a frequency divider, which was fabricated individually, prior to being integrated with the quadrature demodulator, in 65-nm LP CMOS technology, are also presented in this paper.     

The Design of High-Performance Dynamic Asynchronous Pipelines: Lookahead Style

A new class of asynchronous pipelines is proposed, called lookahead pipelines (LP), which use dynamic logic and are capable of delivering multi-gigahertz throughputs. Since they are asynchronous, these pipelines avoid problems related to high-speed clock distribution, such as clock power, management of clock skew, and inflexibility in handling varied environments. The designs are based on the well-known PSO style of Williams and Horowitz as a starting point, but achieve significant improvements through novel protocol optimizations: the pipeline communication is structured so that critical events can be detected and exploited earlier. A special focus of this work is to target extremely fine-grain or gate-level pipelines, where the datapath is sectioned into stages, each consisting of logic that is only a single level deep. Both dual-rail and single-rail pipeline implementations are proposed. All the implementations are characterized by low-cost control structures and the avoidance of explicit latches. Post-layout SPICE simulations, in 0.18-mum technology, indicate that the best dual-rail LP design has more than twice the throughput (1.04 giga data items/s) of Williams' PSO design, while the best single-rail LP design achieves even higher throughput (1.55 giga data items/s).     

SOI: a metamorphosis of silicon

For the next millennium, SOI offers the opportunity to integrate high-performance and/or innovative devices that can push away the present frontiers of the CMOS down-scaling. SOI will play a significant role in the future of microelectronics if subsisting problems can be rapidly solved. The short-term prospects of SOI-based microelectronics will also closely depend on the penetration rate of LP/LV SOI circuits into the market, A key challenge is associated with the industrial strategy, which must be oriented to overcome the bulk-Si monocultural barrier. Designers, process engineers, and managers are extremely busy loading the bulk-Si machine. When, eventually, they can afford to take a careful look at the assets of SOI technology, they do realize the immediate and long-term benefits offered in terms of performance and scaling extensions. Several companies have already accomplished this step; others will follow soon. SOI should not be regarded as a totally different technology. It is just a metamorphosis of silicon     

NOVEL SECOND-ORDER CURRENT MODE FILTERS USING CCIIs

Two new current mode active-RC networks using the second generation current conveyer (CCII) devices are presented. The circuits provide high-Q bandpass (BP)/lowpass(LP) filter characteristics; the highpass(HP) response may also be obtained with suitable design. Current mode sine wave signal generation (Q→α) is possible by tuning a grounded resistor. With non-ideal CCIIs the design equations are slightly altered owing to CCII port current and voltage tracking errors (Ei,v).     

功率MOSFET的研究与进展

器件设计工艺、封装、宽禁带半导体材料和计算机辅助设计4大技术的发展进步使得功率MOSFET的性能指标不断达到新的高度。超级结技术使得高压功率MOSFET的导通电阻大大降低,降低栅极电荷和极间电容的改进沟槽工艺和横向扩散工艺技术进一步提高了低压功率MOSFET的优值因子,中小功率MOSFET继续朝着单片集成智能功率电子发展。功率MOSFET封装呈现出集成模块化、增强散热性和高可靠性的特点。基于宽禁带半导体材料SiC和GaN的功率MOSFET具有高温、高频和低功耗等优异性能,计算机辅助设计工具引领功率MOSFET在工艺设计、制造和电路系统应用方面快速发展。     

High-accuracy variable-phase filter design utilising iterative linear-programming strategy

This paper proposes an iterative strategy employing the linear programming (LP) method for the design of an all-pass variable-phase (AP-VP) digital filter in the minimax error sense. Mathematically, designing an AP-VP digital filter belongs to a non-linear optimisation problem. The novel LP design method first reduces this non-linear minimisation problem to a linear minimisation problem and then solves the linearised optimisation problem iteratively via using the LP method. The iterative LP-solving scheme is able to reduce the largest design errors significantly and thus can get a considerable accuracy improvement as compared to the noniterative one. We will utilise three design examples to show that this iterative scheme can get much better design results (much smaller maximum errors) than the noniterative method in the literature. Therefore, this iterative LP design strategy can significantly enhance the performance of the AP-VP digital filter.