Operational-amplifier compilation with performance optimization

A method for designing analog circuits in which topological design is followed by simultaneous device sizing and layout design is described. By merging circuit and layout design into a single design process, analog circuits can be optimally designed taking layout parasitics fully into account. Using the method, a CMOS operational-amplifier compiler (OAC) has been developed. Given a set of performance specifications and process parameters, OAC generates a layout with circuit performance optimized to meet specified performance constraints. A procedural layout technique is employed to generate a compact and practical layout. A nonlinear optimization method for device sizing which relies on the results of simulations based on the circuit extracted from the layout is applied. Design experiments have shown that OAC can produce satisfactory results with respect to both circuit performance and layout density     

Automatic layout synthesis of analog ICs using circuit recognition and constraint analysis techniques

A systematic method for automatic layout synthesis of analog integrated circuit modules is presented. This method uses analog circuit recognition and critical net analysis techniques to derive proper layout constraints for analog circuit performance optimization. These layout constraints are analyzed and prioritized according to the recognized analog circuit topologies and classified net sensitivities. The weighted constraints are then used to drive the physical layout generation process to obtain a high-quality custom circuit layout. An efficient, constraint-driven analog floorplanning technique based on a zone-sensitivity partitioning algorithm is specially developed to generate a slicing floorplan incorporating the layout constraints. This layout synthesis approach has three key advantages. First, it can produce a satisfactory analog circuit performance with negligible degradation due to the layout-introduced parasitic effects. Second, it allows a complete automation for netlist-to-layout synthesis so that the layout tool can be used by VLSI system designers. Finally, this method is quite general and can be applied to handle a wide variety of analog circuits. Experimental results in CMOS operational amplifiers and a comparator are presented.     

Low Area/Power Synthesis Using Hybrid Pass Transistor/CMOS Logic Cells in Standard Cell-Based Design Environment

This brief presents a logic synthesis flow that depends on the popular Synopsys Design Compiler to perform logic translation and minimization based on the standard cell library with both pass transistor logic (PTL) and CMOS logic cells. The hybrid PTL/CMOS logic synthesis can generate appropriate circuits considering various design constraints. The proposed multilevel PTL logic cells are automatically constructed from only a few basic cells. Postlayout simulations with UMC 90-nm technology are presented based on the standard cell library with pure PTL, pure CMOS, or hybrid PTL/CMOS cells. Experimental results show that, in most cases, pure PTL circuits have smaller area and power, whereas CMOS circuits, in general, have smaller delay.      

VLSI栅阵列单元生成系成

本文介绍一个新的ＶＬＳＩＣＭＯＳ电路栅阵列布图系统ＧＭＳ（ＧａｔｅＭａｔｒｉｘｌａｙｏｕｔＳｙｓｔｅｍ），它可以作为单元生成器在ＶＬＳＩ布图中自动产生基本单元。ＧＭＳ的布图过程包括：栅排序、线网分配和版图压缩，在考虑了许多实际约束条件的基础上，ＧＭＳ使用了一个新的栅排序算法，对Ｌｉ［６］算法做了较大改进，ＧＭＳ还把线网分配问题，转化为扩展的一维分配问题，在给出扩展一维分配问题定义的基础上，开发了一个线网分配算法，取得了较好的结果，ＧＭＳ允许用户对布图结果作叠代改进，对布图结果进行了压缩，从而减小了布图面积，ＧＭＳ已在ＭｉｃｒｏＶａｘＩＩ上用Ｃ语言实现，我们测试了许多实例，取得了较好的结果。     

ALGA: Automated layout generator for analog CMOS circuits

A computer-aided design (CAD) system called ALGA for an analog circuit layout is presented. The main contribution of this paper is to construct a weight graph that represents the topological connectivity of a given analog circuit. By using the weight graph, some efficient techniques can be designed to avoid devices mismatch and place all devices according to the device size constraints. Moreover, an algorithm is presented to perform the device placement step and propose an effective approach to reduce noise coupling in the routing step. A design method has been implemented in several Complementary Metal Oxide Semiconductor (CMOS) analog circuits. It is seen that the proposed system can generate good analog circuit design.     

A metal-oriented layout structure for CMOS logic

A design method is described for the realization of large digital modules of random logic for custom integrated circuits in CMOS technology. The layout structure is based on the gate matrix concept with a metal orientation instead of a polysilicon orientation. The symbolic layout is obtained by using 11 different microcells with simple assembly rules. It is derived from the functional specifications of the circuit (Karnaugh maps) using a very simple and attractive method. A CAD program for translating the symbolic layout into a geometrical one is described. It works by assembling geometrical microcells. The advantages and disadvantages of the metal-oriented structure are analyzed through examples of industrial designs. The technique is not suitable for fast circuits. However, it results in an improvement of productivity by a factor of about four and a packing density for large modules which is at least comparable with that of nonoriented hand layouts.     

Statistical Design of Low Power Square-Law CMOS Cells for High Yield

A robust design of low voltage low power square law CMOS composite cells using statistical VLSI design techniques is presented. Since random device/process variations do not scale down with feature size or supply voltage, the statistical design of low voltage circuits is essential in order to keep functional yields of low voltage circuits at levels that are competitive and cost effective. The Response Surface Methodology and Design of Experiment techniques were used as statistical techniques. This article shows that statistical techniques will result in area/layout optimization which will enhance functional yield of low voltage analog ICs.     

PAD: A New Interactive Knowledge-Based Analog Design Approach

This paper presents a new Procedural Analog Design tool called PAD. It is a chart-based design environment dedicated to the design of analog circuits aiming to optimize design and quality by finding good tradeoffs. This interactive tool allows step-by-step design of analog cells by using guidelines for each analog topology. Its interactive interface enables instantaneous visualization of design tradeoffs. At each step, the user modifies interactively one subset of design parameters and observes the effect on other circuit parameters. At the end, an optimized design is ready for simulation (verification and fine-tuning). The present version of PAD covers the design of basic analog structures (one transistor or groups of transistors) and the procedural design of transconductance amplifiers (OTAs) and different operational amplifier topologies. The basic analog structures calculator embedded in PAD uses the complete set of equations of the EKV MOS model, which links the equations for weak and strong inversion in a continuous way [1, 2]. Furthermore, PAD provides a layout generator for matched substructures such as current mirrors, cascode stages and differential pairs.Danica Stefanovic was born in 1976. She received the B.S. and M.S. degrees in electrical engineering from the University of Nis (Serbia and Montenegro) in 2000 and 2003 respectively. In 2001/2002 she was a scholarship holder of Swiss Confederation working with Electronic Laboratories, Swiss Federal Institute of Technology (EPFL), on a research project in the domain of analog circuits design techniques and their translation into specific CAD tool. She is currently working towards Ph.D. degree at the Swiss Federal Institute of Technology (EPFL). Her research interests include low power, low voltage analog design methodologies and optimisation techniques.Maher Kayal was born in 1959. He received the M.S. and Ph.D. degrees in electrical engineering from the Swiss Federal Institute of Technology (EPFL, Switzerland) in 1983 and 1989 respectively.In 1990, he had a Research Associate in the Swiss Federal Institute of Technology. From 1999 he became a professor in the Electronics Laboratories of this institute. He has published many scientific papers and contributed in three books dedicated to mixed-mode CMOS design. His current research interests include: mixed-mode circuit design, sensors, signal processing and CAD tools for analog design and layout automation. He received in 1990 the Swiss Ascom award for the best work in telecommunication fields and in 1997 the best ASIC award at the European Design and Test Conference ED&TC.Marc Pastre was born in 1977. He received the M.S. degree in computer science at EPFL (Swiss Federal Institute of Technology) in 2000. He is currently working towards his Ph.D. at the Electronics Laboratories LEG (EPFL). His research interests include mixed circuits, ADCs/DACs, sensor frontends and CAD tools.     

High-performance designs with CMOS analog standard cells

The authors describe an approach to the design of complex analog functions comprising the major functions normally encountered in analog systems using a library of 3-/spl mu/m CMOS analog cells. It is shown that through the use of a fixed-height cell system and a predefined connection system, circuits can be designed that suffer little, if any, area penalty when compared to a full custom layout. In addition, the overall system performance achieved can equal that of some full custom designs.     

Efficient design centering of analog integrated circuits using binary search

This paper introduces a procedure for automatically design centering analog integrated circuits called the divide-and-focus method (DAF). DAF is a simple, efficient, and effective algorithm for design centering complex circuits, even if the performance of the original nominal design is poor. DAF uses a binary search of each dimension of parameter space to rapidly focus on regions promising high yield. DAF was applied to a third-order elliptic CMOS transconductance-C integrated circuit filter derived from an automated layout and containing 126 nodes and 319 MOSFETS. Using five key capacitor values as design centering parameters, DAF improved yield in the presence of parasitic capacitance (as extracted from the layout) by a factor of 19 from an initial value of 4% to a final value of 76%. By relaxing constraints on component value symmetry, DAF found a higher yield than was possible when maintaining symmetry, where DAF achieved a yield of 34%. Since DAF uses Monte Carlo analysis to estimate circuit yield, its execution time can be further reduced by exploiting the parallelism implicit in Monte Carlo techniques. Using a local area network of 10 workstations similar to those available at most engineering sites, DAF completed the design centering of the filter 7.4 times faster than when using a single workstation.Supported in part by a Research Initiation grant (CCR-9111941) from the National Science Foundation.Supported in part by a grant (MIP-9121360) from the National Science Foundation.     

A performance-driven placement tool for analog integrated circuits

This paper presents a new approach toward performance-driven placement of analog integrated circuits. The freedom in placing the devices is used to control the layout-induced performance degradation within the margins imposed by the designer's specifications. This guarantees that the resulting layout will meet all specifications by construction. During each iteration of the simulated annealing algorithm, the layout-induced performance degradation is calculated from the geometrical properties of the intermediate solution. The placement tool inherently handles symmetry constraints, circuit loading effects and device mismatches. The feasibility of the approach is demonstrated with practical circuit examples     

A layout-based schematic method for very high-speed CMOS celldesign

In very high-speed CMOS cell design, the result of schematic simulation is inaccurate because of missing parasitic components, such as diodes and parasitic capacitances. Designer cannot pass enough information to the simulator by conventional transistor symbols, therefore, simulation error occurs. In this paper, we address a layout-based schematic (LBS) method for high-speed CMOS cell design. In this method, we introduce several types of MOS transistors and estimate parasitic wire capacitances by using layout knowledge. The simulation results show that the difference between LBS and real layout is much smaller, less than 3% in rise time, compared to in the worst case of up to 65% in the original schematic. This method can be applied to both digital and analog circuits and it is helpful for layout automation. Time and cost will be reduced in high-speed circuit design     

Automated design of switched-current filters

This paper describes the automated design and synthesis of switched-current (SI) filters using SCADS, a flexible CAD system integrated in a major VLSI design suite. With this system, the nonspecialist can produce high performance analog filters suitable for mixed signal CMOS IC's fabricated using only standard digital processes. To achieve high levels of performance on silicon, filter designs are realized using an enhanced differential circuit technique (S²I) in its integrators and sample-and-hold cells. The design system is described in terms of the embedded circuits, its integrated tool set, the filter design flow and the engineering procedures for ensuring reliable circuit operation. Examples of high performance video frequency filters are presented, each generated automatically by SCADS within one day. Fabricated in a 0.8 μm standard CMOS process, they demonstrate state-of-the-art performance     

Crosstalk noise reduction in synthesized digital logic circuits

As CMOS technology scales into the deep submicrometer regime, digital noise is becoming a metric of importance comparable to area, timing, and power, for analysis and design of CMOS VLSI systems. Noise has two detrimental effects in digital circuits: First, it can destroy logical information carried by a circuit net. Second, it causes delay uncertainty: Non critical paths might become critical because of noise. As a result, circuit speed becomes limited by noise, primarily because of capacitive coupling between wires. Most design approaches address the crosstalk noise problem at the layout generation stage, or via postlayout corrections. With continued scaling, too many circuit nets require corrections for noise, causing a design convergence problem. This work suggests to consider noise at the gate-level netlist generation stage. The paper presents a simplified analysis of on-chip crosstalk models, and demonstrates the significance of crosstalk between local wires within synthesized circuit blocks. A design flow is proposed for automatically synthesizing CMOS circuits that have improved robustness to noise effects, using standard tools, by limiting the range of gate strengths available in the cell library. The synthesized circuits incur a penalty in area/power, which can be partially recovered in a single postlayout corrective iteration. Results of design experiments indicate that delay uncertainty is the most important noise-related concern in synthesized static CMOS logic. Using a standard synthesis methodology, critical path delay differences up to 18% of the clock cycle time have been observed in functional blocks of microprocessor circuits. By using the proposed design flow, timing uncertainty was reduced to below 3%, with area and power penalties below 20%.     

Directly performance-constrained template-based layout retargeting and optimization for analog integrated circuits

Due to intrinsic intricacy, layout parasitics exhibit a significant impact on the performance of analog integrated circuits. In this paper a directly performance-constrained parasitic-aware automatic layout retargeting and optimization algorithm is presented. Unlike the conventional sensitivity analysis, a general central-difference based scheme using any simulator for sensitivity computation is deployed. We propose a piecewise sensitivity model to enforce more accurate sensitivity computation during parasitic optimization. Moreover, mixed-integer performance constraints due to parasitics are included in the formulated mixed integer nonlinear programming problem rather than through either indirect parasitic-bound constraints or inaccurate worst-case sensitivities. A graph technique and mixed-integer nonlinear programming are effectively combined to solve the formulated parasitic optimization problem. The automatically generated target layouts can satisfy performance constraints to ensure the desired specifications. The experimental results show that the proposed algorithm can achieve effective retargeting of analog circuits with less layout area and significant reduction in execution time.     

CMOS Analog Implementation of a Discrete-Time 9-Tap FIR Filter with Circular Buffer Architecture

This paper presents the design and simulation of a 9-Tap CMOS Analog Discrete-Time Finite Impulse Response (FIR) Filter system. This unique design features a Circular Buffer Architecture which achieves high sampling rate that can be easily expanded to improve speed and extended to higher order filters. Novel area-efficient four quadrant CMOS analog adder and multiplier circuits are employed to respond for high frequency and wide linear range inputs. The layout for all circuits has been realized using the design tool MAGIC with a 1.2 m CMOS process. The performance for each circuit and the whole system are characterized using HSPICE simulation based on the extracted MAGIC netlist. The 9-tap filter was designed to achieve 5 MHz sampling rate. The implemented design requires a total chip area of 1690.9 m by 2134.2 m and ±5 volt power supply.