低相位噪声压控振荡器的设计及仿真

随着通信技术对射频收发机性能要求的提高,高性能压控振荡器已成为模拟集成电路设计、生产和实现的关键环节.针对压控振荡器设计过程中存在相位噪声这一核心问题,采用STMC 0.18μm CMOS工艺,提出了一种1.115GHz的电感电容压控振荡器电路,利用Cadence中的SpectreRF对电路进行仿真.仿真结果表明:在4~6V的电压调节范围内,压控振荡器的输出频率范围为1.114 69~1.115 38GHz,振荡频率为1.115GHz时,在偏离中心频率10kHz处、100kHz处以及1MHz处的相位噪声分别为-90.9dBc/Hz,-118.6dBc/Hz,-141.3dBc/Hz,以较窄的频率调节范围换取较好的相位噪声抑制,从而提高了压控振荡器的噪声性能.     

一种采用开关阶跃电容的压控振荡器(下): 电路设计和实现

为了验证阶跃可变电容压控振荡器调谐特性理论分析的正确性,提出了一种采用开关阶跃电容的新型压控振荡器电路,该压控振荡器电路采用0.25μm 1P5M CMOS工艺实现.一种新型开关阶跃电容实现了频率调谐功能,该电容的调谐电容是传统反型MOS管可变电容的146%.在1/f3区域,差分调谐振荡器的相位噪声比单端调谐振荡器低7dB.在载波频率偏差10kHz,100kHz和1MHz处测得差分调谐时的相位噪声分别是-83,-107和-130dBc/Hz,功耗为8.6mW.     

一种采用开关阶跃电容的压控振荡器(下): 电路设计和实现

为了验证阶跃可变电容压控振荡器调谐特性理论分析的正确性,提出了一种采用开关阶跃电容的新型压控振荡器电路,该压控振荡器电路采用0.25μm 1P5M CMOS工艺实现.一种新型开关阶跃电容实现了频率调谐功能,该电容的调谐电容是传统反型MOS管可变电容的146%.在1/f3区域,差分调谐振荡器的相位噪声比单端调谐振荡器低7dB.在载波频率偏差10kHz,100kHz和1MHz处测得差分调谐时的相位噪声分别是-83,-107和-130dBc/Hz,功耗为8.6mW.     

一种钽酸锂压控振荡器的设计与实现

该文使用具有低电容比、宽调谐范围的钽酸锂晶体设计了一巴特勒共基低相位噪声压控振荡器,此设计在寻求高有载品质因数QL的同时保持了振荡器的输出功率。使用的钽酸锂晶体的无载品质因数Q0约为1.24×103,其频率为10.727MHz。设计出的巴特勒振荡器QL≈33%Q0,输出功率约为11dBm。不加压控的情况下,实际测得该振荡器的相位噪声结果为-85dBc/Hz@10 Hz和-145dBc/Hz@1kHz。在此基础上,增加一变容二极管作为压控元件设计了钽酸锂压控振荡器,在2~10 V范围内,测得控制电压压控斜率约为86.6×10-6/V,相位噪声测试结果优于-82dBc/Hz@10Hz和-142dBc/Hz@1kHz,实现了具有宽调谐范围的低相位噪声钽酸锂振荡器的设计。     

基于电容补偿的高线性低噪声2.4GHz CMOS LC 压控振荡器

实现了一个基于标准0.18µm CMOS工艺的2.4GHz高线性低噪声交叉耦合LC压控振荡器。基于三段分布式偏置的开关容抗管电路和差分开关电容电路,提出了一种调谐灵敏度补偿结构,减小了压控振荡器的增益变化,获得了高线性度和良好的相位噪声性能。与传统结构的压控振荡器相比,本文提出的压控振荡器在整个频率调谐范围内具有更加恒定的增益。当载波频率为2.42GHz 时,在100kHz和1MHz的频偏处相位噪声分别为-100.96dBc/Hz和-122.63dBc/Hz。工作电压为1.8V时,电路功耗为2.5mW。该压控振荡器面积为500×810 µm2。     

低功耗低噪声正交压控振荡器设计

设计了一种用于WLAN 802.11 n收发机频率合成器的新颖低功耗、低相位噪声正交输出LC电压控制振荡器(QVCO)。电路设计中使用了Cadence IC5.033和ADS2004软件以及TSMC0.18μm CMOS工艺模型库,电路依靠并联的耦合支路相互作用使两个独立压控振荡器输出相位成正交,采用PMOS并联耦合支路和开关控制偏置两种新技术降低了VCO的相位噪声,其仿真结果为1 MHz频偏处-128.6 dBc/Hz和10 kHz频偏处-84 dBc/Hz。采用数字电容阵列提高了QVCO的频率调谐范围,QVCO的频率范围仿真结果为3.1 GHz~4.1 GHz。QVCO的电源电压为1.8 V,功耗17 mW。实现了低功耗正交输出压控振荡器,同时通过新颖的电路设计技术改善了相位噪声,改变了正交输出LC压控振荡器高噪声的传统观念,为今后在正交输出LC压控振荡器的设计提供了一些参考。     

2.5 GHz低相位噪声LC压控振荡器

在0.35 μm SiGe BiCMOS工艺条件下,设计了一个全集成的低相位噪声LC压控振荡器(VCO).该VCO采用尾电阻结构替代传统的尾电流源结构实现电流控制,以减小尾电流源产生的噪声.该VCO的调谐范围为480 MHz,可以覆盖2.32～2.8 GHz.当振荡频率为2.5 GHz时,100 kHz和1 MHz频偏处的相位噪声分别为-104.3 dBc/Hz和-124.3 dBc/Hz.振荡器工作电压为5 V,尾电流为5 mA.工作在2.5 GHz时,其100 kHz频偏处的性能系数为-178 dBc/Hz.     

卫星电视天线射频电路中LC压控振荡器设计

设计了一款应用于卫星电视天线电路中低功耗、低相噪的宽带单片集成压控振荡器。该振荡器利用PMOS尾电流源和MIM电容阵列结构。在保证调谐范围的前提下,有效地降低了相位噪声。使得该压控振荡器实现了3.384～4.022 GHz频段的覆盖,在中心频率为3.7 GHz时,100 Hz和1 MHz频偏处的相位噪声分别为-90.4 dBc/Hz和-119.1 dBc/Hz,工作电压下为1.8 V,功耗仅为2.5 mW。     

射频卫星电视天线电路中LC压控振荡器设计

本文设计了一款应用于卫星电视天线电路中低功耗、低相噪的宽带单片集成压控振荡器。该振荡器利用PMOS尾电流源和MIM电容阵列结构。在保证调谐范围的前提下,有效的降低了相位噪声。使得该压控振荡器实现了3.384GHz~4.022GHz频段的覆盖,在中心频率为3.7GHz时,100Hz和1MHz频偏处的相位噪声分别为-90.4dBc/Hz和-119.1dBc/Hz,工作电压下为1.8V,功耗仅为2.5mW。     

具有电容阵列和电感阵列的1.8~2.6GHz CMOS压控振荡器

设计了一个具有开关电容阵列和开关电感阵列的1.76~2.56GHz CMOS压控振荡器。电路采用0.18µm 1P6M CMOS工艺实现。经测试,压控振荡器的频率调谐范围为37%。在频率调谐范围内及1MHz频偏处,相位噪声变化范围为-118.5dBc/Hz至 -122.8dBc/Hz。在1.8V电源电压下,功耗约为14.4mW。基于具有电容阵列和电感阵列的可重构LC谐振回路,对压控振荡器的调谐范围参数进行了分析和推导,所得结果为电路设计提供了指导。     

A 900-MHz 1.5-V CMOS voltage-controlled oscillator using switched resonators with a wide tuning range

A 900-MHz fully integrated VCO was fabricated in a 0.18-/spl mu/m foundry CMOS process. Under 1.5 V power supply, this VCO can be tuned from 667 MHz to 1156 MHz which corresponds to a 53.6% tuning range. The VCO has nearly constant phase noise over the whole tuning frequency, credit to the switched resonators used in this VCO. The phase noise at a 600 kHz offset is -123.1 dBc/Hz at 1125 MHz center frequency and -124.2 dBc/Hz at 667 MHz center frequency.     

一种简易微波VCO的设计*

描述了一种高性能简易微波VCO器件的设计和实验。该器件基于负阻原理设计,利用微波FET和变容二极管等分立元件制作,具有高性价比的特点。设计过程中利用ADS软件进行电路的匹配和优化,通过合适的外电路设计对变容二极管VCO的调频线性度进行改善,同时,降低了VCO的相位噪声。实际电路的测试结果表明,当该VCO的中心频率为4.3GHz时,其调谐范围大于200MHz,输出功率大于5.2dBm,相位噪声优于-112dBc/Hz@1MHz和-83dBc/Hz@100kHz。     

Low phase noise IP VCO for multistandard communication using a 0.35-/spl mu/m BiCMOS SiGe technology

In this letter, we report that a commonly used 0.35-/spl mu/m, 60-GHz-F/sub MAX/ BiCMOS SiGe monolithic microwave integrated circuit (MMIC) technology is able to provide very low phase noise signal generation in the X-band frequency range. This statement has been demonstrated using a differential LC voltage-controlled oscillator (VCO) in which varactors are realized with metal-oxide semiconductor (MOS) transistors and inductors with a patterned ground shield technology. This VCO features an output power signal in the range of -5 dBm and exhibits a phase noise of -96 dBc/Hz at a frequency offset of 100kHz from carrier and -120 dBc/Hz at a frequency offset of 1 MHz. The VCO features a tuning range of 430 MHz or 4.3% of its operating frequency. Its power consumption is in the range of 70 mW (200 mW with buffers circuits) for a chip size of 800/spl times/1000 /spl mu/m/sup 2/ (including RF probe pads).     

A 5-GHz fully integrated full PMOS low-phase-noise LC VCO

A 5-GHz fully integrated, full PMOS, low-phase-noise and low-power differential voltage-controlled oscillator (VCO) is presented. This circuit is implemented in a 0.35-/spl mu/m four-metal BiCMOS SiGe process. At 2.7-V power supply voltage and a total power dissipation of only 13.5 mW, the proposed VCO features a worst case phase noise of -97 dBc/Hz and -117 dBc/Hz at 100 kHz and 1 MHz frequency offset, respectively. The oscillator is tuned from 5.13 to 5.68 GHz with a tuning voltage varying from 0 to 2.7 V.     

A fully integrated 5.8 GHz U-NII band 0.18-/spl mu/m CMOS VCO

A fully integrated 5.8 GHz CMOS L-C tank voltage-controlled oscillator (VCO) using a 0.18-/spl mu/m 1P6M standard CMOS process for 5 GHz U-NII band WLAN application is presented. The VCO core circuit uses only PMOS to pursue a better phase noise performance since it has less 1/f noise than NMOS. The measurement is performed by using a FR-4 PCB test fixture. The output frequency of the VCO is from 5860 to 6026 MHz with a 166 MHz tuning range and the phase noise is -96.9 dBc/Hz at 300 kHz (or -110 dBc/Hz at 1 MHz) with V ctrl = 0 V. The power consumption of the VCO excluding buffer amplifiers is 8.1 mW at V/sub DD/ = 1.8 V and the output power is -4 dBm.     

用于434/868MHz FSK/OOK CMOS发射机的锁相环设计

一种可输出434/868MHz信号的Σ-Δ分数分频锁相环在0.35μmCMOS工艺中集成。该发射机系统采用直接调制锁相环分频比的方式实现FSK调制,OOK的调制则通过功率预放大器的开-关实现。为了降低芯片的成本和功耗,发射机采用了电流数字可控的压控振荡器(VCO),以及片上双端-单端转换电路,并对分频器的功耗设计进行研究。经测试表明,锁相环在868MHz载波频偏为10kHz、100kHz和3MHz处的相位噪声分别为-75dBc/Hz、-104dBc/Hz和-131dBc/Hz,其中的VCO在100kHz频偏处的相位噪声为-108dBc/Hz。在发送模式时,100kHz相邻信道上的功率与载波功率之比小于-50dB。在直流电压2.5V的工作条件下,锁相环的电流为12.5mA,包括功率预放大器和锁相环在内的发送机总面积为2mm2。     

新型复合沟道Al0.3Ga0.7N/Al0.05Ga0.95N/GaN HEMT低相位噪声微波单片集成压控振荡器

设计并研制了一种新型复合沟道Al0.3Ga0.7N/Al0.05Ga0.95N/GaN HEMT(CC-HEMT)微波单片集成压控振荡器(VCO),且测试了电路的性能.CC-HEMT的栅长为1μm,栅宽为100μm.叉指金属-半导体-金属(MSM)变容二极管被设计用于调谐VCO频率.为提高螺旋电感的Q值,聚酰亚胺介质被插入在电感金属层与外延在蓝宝石上GaN层之间.当CC-HEMT的直流偏置为Vgs=-3V,Vds=6V,变容二极管的调谐电压从5.5V到8.5V时,VCO的频率变化从7.04GHz到7.29GHz,平均输出功率为10dBm,平均功率附加效率为10.4%.当加在变容二极管上电压为6.7V时,测得的相位噪声为-86.25dBc/Hz(在频偏100KHz时)和-108dB/Hz(在频偏1MHz时),这个结果也是整个调谐范围的平均值.据我们所知,这个相位噪声测试结果是文献报道中基于GaN HEMT单片VCO的最好结果.     

A 2 V 1.8 GHz fully integrated CMOS dual-loop frequency synthesizer

A 2 V 1.8 GHz fully integrated CMOS dual-loop frequency synthesizer is designed in a standard 0.5 /spl mu/m digital CMOS process for wireless communication. The voltage-controlled oscillator (VCO) required for the low-frequency loop is designed using a ring-type VCO and achieves a tuning range of 89% from 356 to 931 MHz and a phase noise of -109.2 dBc/Hz at 600 kHz offset from 856 MHz. With an active chip area of 2000/spl times/1000 /spl mu/m/sup 2/ and at a 2 V supply voltage, the whole synthesizer achieves a tuning range from 1.8492 to 1.8698 GHz in 200 kHz steps with a measured phase noise of -112 dBc/Hz at 600 kHz offset from 1.86 GHz. The measured settling time is 128 /spl mu/s and the total power consumption is 95 mW.     

A 15/30-GHz Dual-Band Multiphase Voltage-Controlled Oscillator in 0.18- μm CMOS

A multiphase oscillator suitable for 15/30-GHz dual-band applications is presented. In the circuit implementation, the 15-GHz half-quadrature voltage-controlled oscillator (VCO) is realized by a rotary traveling-wave oscillator, while frequency doublers are adopted to generate the quadrature output signals at the 30-GHz frequency band. The proposed circuit is fabricated in a standard 0.18-mum CMOS process with a chip area of 1.1times1.0 mm². Operated at a 2-V supply voltage, the VCO core consumes a dc power of 52 mW. With a frequency tuning range of 250 MHz, the 15-GHz half-quadrature VCO exhibits an output power of -8 dBm and a phase noise of -112 dBc/Hz at 1-MHz offset frequency. The measured power level and phase noise of the 30-GHz quadrature outputs are -16 dBm and -104 dBc/Hz, respectively