A Flexible UMTS-WiMax Turbo Decoder Architecture

This work proposes a VLSI decoding architecture for concatenated convolutional codes. The novelty of this architecture is twofold: 1) the possibility to switch on-the-fly from the universal mobile telecommunication system turbo decoder to the WiMax duo-binary turbo decoder with a limited resources overhead compared to a single-mode WiMax architecture; and 2) the design of a parallel, collision free WiMax decoder architecture. Compared to two single-mode solutions, the proposed architecture achieves a complexity reduction of 17.1% and 27.3% in terms of logic and memory, respectively. The proposed, flexible architecture has been characterized in terms of performance and complexity on a 0.13-mum standard cell technology, and sustains a maximum throughput of more than 70 Mb/s.     

Implementation of a Flexible LDPC Decoder

Low-density parity-check codes (LDPC) are among the most powerful error correcting tools today available. For this reason they became very popular in several applications such as the digital satellite broadcasting system (DVB-S2), wireless local area network (IEEE 802.11n) and metropolitan area network (802.16e). Whereas several code-specific decoders have been proposed in the literature, the implementation of a high performance yet flexible LDPC decoder still is a challenging topic. This work presents a novel formulation of the decoding algorithm that strongly simplifies internal communication requirements and enables the development of decoders supporting generally defined LDPC codes. The resulting architecture is tailored to decode both IEEE 802.11n and IEEE 802.16e LDPC codes, as well as any other code of comparable complexity. The implementation cost deriving from the full flexibility offered by the proposed approach is also evaluated.     

Turbo Decoder Using Contention-Free Interleaver and Parallel Architecture

This paper introduces a turbo decoder that utilizes multiple soft-in/soft-out (SISO) decoders to decode one codeword. In addition, each SISO decoder is modified to allow simultaneous execution over multiple successive trellis stages. The design issues related to the architecture with parallel high-radix SISO decoders are discussed. First, a contention-free interleaver for the hybrid parallelism is presented to overcome the complicated collision problem as well as reduce interconnection network complexity. Second, two techniques for the high-speed add-compare-select (ACS) circuits are given to lessen area overhead of the SISO decoder. Third, a modification of the processing schedule is made for higher operating efficiency. Two designs with parallel architecture have been implemented. The first design with 32 SISO decoders, each of which processes 2 symbols per cycle, has 160 Mb/s and 0.22 nJ/b/iter after measurement. The second design uses 16 SISO decoders to deal with 4 symbols per cycle and achieves 100% efficiency, leading to 1000 Mb/s and 0.15 nJ/b/iter in post-layout simulation.      

A Memory Efficient Partially Parallel Decoder Architecture for Quasi-Cyclic LDPC Codes

This paper presents a memory efficient partially parallel decoder architecture suited for high rate quasi-cyclic low-density parity-check (QC-LDPC) codes using (modified) min-sum algorithm for decoding. In general, over 30% of memory can be saved over conventional partially parallel decoder architectures. Efficient techniques have been developed to reduce the computation delay of the node processing units and to minimize hardware overhead for parallel processing. The proposed decoder architecture can linearly increase the decoding throughput with a small percentage of extra hardware. Consequently, it facilitates the applications of LDPC codes in area/power sensitive high-speed communication systems     

Turbo码的编译码器及性能分析

介绍Turbo码的编译码器和迭代译码器的结构 ,并分析Turbo的性能     

一种多模LDPC译码器的可重构结构

在分析低密度奇偶校验码(LDPC)算法的基础上,根据可重构思想,提出了一种支持12种模式LDPC的可重构结构。调用不同配置参数,重新组合译码器结构,实现可重构译码。利用接收到的移位配置信息,重构不同位宽的数据循环移位网络。采用NMS优化的TDMP算法,降低了系统硬件开销和系统级应用的复杂度,节省了芯片面积。该译码器基于TSMC 0.13 μm CMOS工艺进行设计。结果表明,该译码器的最大时钟频率达240 MHz,最高吞吐率达1.568 Gbit/s。相比于其他可重构结构的译码器,该译码器的芯片面积更小,支持的模式更多。     

A Hybrid Decoder for Block Turbo Codes

We propose a novel iterative decoder for block turbo codes (BTCs). The proposed decoder combines soft-input/softoutput (SISO) and hard-input/hard-output (HIHO) constituent decoders in order to obtain better error performance and reduce the computational complexity compared to classical BTC decoders. We show that the new decoder, called ?hybrid decoder?, offers a better complexity/performance tradeoff than a classical BTC decoder.     

一种用于cdma2000年的低复杂度Turbo码译码器

由于Turbo码优异的纠错性能,使得其在第三代移动通信（3G)系统中倍受重视。无论是WCDMA还是cdma2000都将其作为侯选的信道编码方案,并且将其列为3G的核心技术之一。但是Turbo码存在译码复杂度大、译码延时长的缺点。在这里,我们提出一种用于cdma2000的低复杂度Turbo码译码器,即结合CRC校验来减少译码过程中的迭代次数。仿真结果证明使用该译码器可以在大信噪比时大大降低译码复杂度和译码延时。     

A Simple Efficient Stopping Criterion for Turbo Decoder

The performance of a turbo decoder depends strongly on the number of iterations in its decoding process. It is necessary to stop the decoding process at an appropriate moment to alleviate the serious burden, in terms of both the computational speed and latency, part of which is associated with too many iterations. In this letter, we introduce a criterion for finding the opportune moment to stop the decoding process, called a hard decision aided criterion based on bit interleaved parity, which is known to have much simpler hardware logic, compared with other schemes, and does not lead to any significant performance degradation.     

Array LDPC码解码器设计

Array—LDPC码是一种高码率的LDPC（低密度奇偶校验）码,具有高性能、易编码等特点,广泛应用于DSL（数字用户线）传输中。在分析ArrayLDPC码结构和MS（最小和）算法的基础上,提出一种在较低硬件复杂度下实现较高并行度的解码器架构。该架构显著降低了节点间的信息通信量,同时,用局部CPU之间有规律的信息传递取代了VPU与CPU之间复杂的信息交换,解决了硬件实现中的布线问题。设计结果表明,采用这种架构设计的（2209,2021）Array．LDPC解码器具有吞吐率高、结构简单的优点,在0．18μmCMOS工艺下,面积仅为2．4mm2,而吞吐率可达到1．03Gbps。     

Improving Network-on-Chip-based Turbo Decoder Architectures

In this work novel results concerning Network-on-Chip-based turbo decoder architectures are presented. Stemming from previous publications, this work concentrates first on improving the throughput by exploiting adaptive-bandwidth-reduction techniques. This technique shows in the best case an improvement of more than 60 Mb/s. Moreover, it is known that double-binary turbo decoders require higher area than binary ones. This characteristic has the negative effect of increasing the data width of the network nodes. Thus, the second contribution of this work is to reduce the network complexity to support double-binary codes, by exploiting bit-level and pseudo-floating-point representation of the extrinsic information. These two techniques allow for an area reduction of up to more than the 40 % with a performance degradation of about 0.2 dB.     

A Parallel Turbo Decoder Based on Recurrent Neural Network

Wireless Personal Communications - A neural network-based decoder, based on a long short-term memory (LSTM) network, is proposed to solve the problem that large decoding delay and performance...     

基于DSP实现的8状态turbo码译码器

国际电信联合会在UMTS/3GPP规范中推荐8状态turbo码作为数据纠错的方案。本文回顾了turbo码的MAX-LOG-MAP译码算法,并分析了输入量化方式对译码性能的影响。在100MHz的定点DSP芯片上实现该算法时,译码速度达到110kbps～300kbps。     

多元LDPC译码器设计

在多元低密度奇偶校验码(NB-LDPC)的扩展最小和译码算法（EMS）中,由于消息向量的递归计算和校验/变量节点信息之间的迭代交换,导致译码器存在较大延迟。针对此问题本文提出了一种新型译码器结构,它优化了校验节点更新单步运算单元,根据前向后向算法规则,以3路单步运算单元完成校验节点更新,硬件资源消耗略有增加,但所需时钟周期约降为一般结构的1/3;并采用全并行运算的变量节点信息更新单元,无需利用前向后向算法将更新过程分解为多个单步运算,消除了变量节点更新的递归计算,且具有低复杂度低延时等优点,并在现场可编程门阵列(FPGA)Xilinx Virtex-4 (XC4VLX200)平台上对一个GF(16)域上(480,360)的准循环多元LDPC码进行了综合仿真。仿真结果证明,设计的译码器在较小资源消耗条件下能成倍提高吞吐量。      

Decoder Design for RS-Based LDPC Codes

This brief studies very large-scale integration (VLSI) decoder architectures for RS-based low-density parity-check (LDPC) codes, which are a special class of LDPC codes based on Reed-Solomon codes. The considered code ensemble is well known for its excellent error-correcting performance and has been selected as the forward error correction coding scheme for 10GBase-T systems. By exploiting the shift-structured properties hidden in the algebraically generated parity-check matrices, novel decoder architectures are developed with significant advantages of high level of parallel decoding, efficient usage of memory, and low complexity of interconnection. To demonstrate the effectiveness of the proposed techniques, we completed a high-speed decoder design for a (2048, 1723) regular RS-LDPC code, which achieves 10-Gb/s throughput with only 820 000 gates. Furthermore, to support all possible RS-LDPC codes, two special cases in code construction are considered, and the corresponding extensions of the decoder architecture are investigated.     

一种新的LDPC译码算法及其硬件实现

介绍了LDPC编译码技术,提出了分层修正最小和算法并对该算法进行了定点仿真和硬件实现.仿真结果和硬件实现表明,该算法性能优良并能降低迭代次数以提高吞吐量.     

一种高效的多码率LDPC译码器的设计

利用最小和算法(Min-Sum Algorithm,MSA),提出了一种存储高效的、低复杂度的多码率LDPC译码器.通过引入映射网络和地址产生器,采用流水线设计,降低了硬件实现复杂度,减少了存储需求量,提高了系统吞吐量.通过资源复用,在不增加存储器的情况下,实现了码率可调.采用该结构,在FPGA上实现了一个适合中国移动多媒体广播(CMMB)标准的LDPC译码器,1/2码率10次迭代时,吞吐量可达70.5Mb/s,3/4码率15次迭代时,吞吐量可达73.2 Mb/s.     

改进Turbo码译码器硬件实现的方法

简要描述了基于Log-MAP译码算法的MAP译码器结构,介绍了几种改善其硬件实现结构的途径:选择合理的计算顺序和进行适当简化方法;引入了滑动窗方法;给出了通过改变数据存储结构来减小存储器的大小的方法。分析了改进方法对译码性能和实现的影响。     

Turbo Product Code Decoder Without Interleaving Resource: From Parallelism Exploration to High Efficiency Architecture

This article proposes to explore parallelism in Turbo-Product Code (TPC) decoding through a parallelism level classification and characterization. From this design space exploration, an innovative TPC decoder architecture without any interleaving resource is presented. This architecture includes a fully-parallel SISO decoder capable of processing n symbols in one clock period. Syntheses results show the better efficiency of such an architecture compared with existing solutions. Considering a six-iteration turbo decoder of a BCH(32,26)² product code, synthesized in 90 nm CMOS technology, 10 Gb/s can be achieved with an area of 600 Kgates. Moreover, a second architecture enhancing parallelism rate is described. The throughput is 50 Gb/s while an area estimation gives 2.2 Mgates. Finally, comparisons with existing TPC decoders and existing LDPC decoders are performed. They validate the potential of proposed TPC decoder for Gb/s optical fiber transmission systems.