A Digital CMOS PWCL With Fixed-Delay Rising Edge and Digital Stability Control

A digital pulsewidth control loop (PWCL) with a fixed-delay rising edge and digital stability control is proposed for multiphase clock applications. In the duty-cycle tracking mode, the linear range of the input duty cycle was measured to be 28%-70%, with a maximum linearity deviation of 0.5%. In the duty-cycle correction mode, the correction range of the input duty cycle was measured to be 25%-75%, with the output duty cycle within 50 plusmn 0.4%. The chip was fabricated by using a 0.25-mum CMOS process with a 2.5-V supply. The chip area and the power consumption were 200 mumtimes250 mum and 18 mW at an input clock frequency of 1.0 GHz, respectively     

All-digital delay-locked loop/pulsewidth-control loop with adjustable duty cycles

An all-digital delay-locked loop (DLL) and an all-digital pulsewidth-control loop (PWCL) with adjustable duty cycles are presented. For the DLL, by using the flash time-to-digital conversion, both the phase alignment and the duty cycle of the output clock are assured in 10 cycles. For the PWCL, the sequential time-to-digital conversion is adopted to reduce the required D-flip-flops and lock within 28 cycles. For both of the proposed circuits, the requirement of the input clock with 50% duty cycle is eliminated. The proposed circuits have been fabricated in a 0.35-/spl mu/m CMOS process. The proposed DLL generates the output clock with the duty cycle of 25%, 50% and 75%, and the operation frequency range is from 140 to 260 MHz. For the proposed PWCL, the duty cycle is adjusted from 30% to 70% in steps of 10%. The operation frequency range is from 400 to 600 MHz.     

Design and implementation of differential pulsewidth control loop for GHz VLSI systems

A novel differential pulsewidth control loop (PWCL) is proposed, in which a balanced charge pump is employed so that the PWCL does not require a 50% duty cycle reference clock. A test chip is realised in a 0.35 /spl mu/m CMOS process, and the measured results show that the tuning range for the duty cycle of the input clock is from 27 to 71% at 1 GHz operating frequency.     

Pulsewidth control loop with a frequency detector for wide frequency range operation

A pulsewidth control loop (PWCL) with a frequency detector for wide frequency range operation is presented. The proposed PWCL is implemented with a duty cycle controlled circuit and frequency detector to correct the wide range frequency and duty cycle of the input clock. The duty cycle controlled circuit is able to modify the gain with different frequency and duty cycle ranges. The frequency and duty cycle of the input clock are detected by the frequency detector. The frequency detector is based on a ring oscillator and the input clock duty cycle and frequency are detected within two input clock cycles. The proposed circuit has been fabricated in a 0.35 μm CMOS technology. The proposed circuit generates the output clock of 50% duty cycle with the input range from 20% to 80% and frequency range 50–800 MHz. The measured duty cycle error is less than 1% within the frequency range from 50 MHz to 800 MHz.     

A 500-MHz-1.25-GHz fast-locking pulsewidth control loop with presettable duty cycle

A 500-MHz-1.25-GHz fast-locking pulsewidth control loop (PWCL) with presettable duty cycle is realized in 0.35-/spl mu/m CMOS technology. The proposed voltage-difference-to-digital converter and switched charge pump circuits reduce the lock time of a conventional PWCL. Compared with the conventional PWCL, the proposed circuit can reduce the lock time by a factor of 2.58. A method to preset the duty cycle of the output clock is also described. Circuit measurements verify that the duty cycle of the output clock can be adjusted from 35% to 70% in steps of 5%.     

1?MHz–3.5?GHz, wide range input duty 50% output duty cycle corrector

A duty cycle corrector (DCC) is proposed in this paper. By directly controlling the duty cycle in the clock distribution path, it can work at a frequency as high as 3.5?GHz. The DCC adopts the continuous-time integrator as the duty cycle detector. The output pulse is scaled down according to the input frequency, which reduces the control voltage ripple and expands the minimum operation frequency to 1?MHz. The test chip is fabricated using SMIC 0.18???m CMOS process. The experiment results show that the frequency range of the input signal was 1?MHz?C3.5?GHz, and the duty cycle range of the input signal is from 0.1?C99.9%. The peak-to-peak jitter and power dissipation are 33.3?ps and 0.6?mW, respectively, at an operating frequency of 2?GHz.     

A differential pulsewidth control loop for high-speed VLSI systems

For those adopting double data rate technology systems, the precise system timing plays a crucial role since both rising and falling edges of the system clock signal are used to sample the input data. Due to this requirement, it is necessary to accurately maintain the duty cycle of the clock signal at 50%. For a multistage clock buffer, a pulsewidth control loop (PWCL) circuit was therefore proposed to adjust the duty cycle of its output signal. This paper is aimed at introducing a new proposed differential PWCL (DPWCL) together with investigating its mechanism through a comprehensive theoretical analysis. By taking advantage of a differential topology, the dc offset in generating the control voltage can be removed thereby improving the duty cycle control accuracy. Moreover, the proposed DPWCL employs a low-pass filter to generate the reference voltage so that the DPWCL does not necessitate a 50% duty cycle reference clock.     

Clock buffer with duty cycle corrector

A clock buffer with duty cycle corrector circuit is presented. The proposed circuit can generate either 50% duty cycle or conserve the duty cycle as input clock. It corrects the input duty cycle of 10-90% for generated 50% duty cycle of output clock with error less than 0.9%. Moreover, it enhances the input clock signal driving ability and keeps the same duty cycle as input clock within range from 20% to 80% with a maximum duty error of 0.5%. The proposed circuit operation frequency range is from 100 MHz to 1 GHz. The proposed circuit has been fabricated in a 0.18 μm CMOS technology.     

一种4路正交时钟校准电路的设计

采用TSMC 40 nm CMOS工艺,设计了一种正交时钟校准电路,它包含2个脉冲宽度调整环路和1个内嵌的延迟锁相环。与其他校准电路相比,本文校准电路无需50%占空比的参考时钟或者单端转差分(STC)电路,就能获得4路占空比为50%的时钟,还能调整时钟的相对相位以输出4路正交时钟。当工作频率为3.125 GHz时,该校准电路能将占空比为10%~90%的输入时钟自动调整至占空比为50%±0.2%的时钟,相位调整范围为58°~122°,电路功耗为2.2 mW,可应用于RapidIO物理层接收机电路中。     

A 200 MHz-to-1.4 GHz fast-locking pulse width control loop

In this article, we propose a wide frequency range low lock time pulse width control loop (PWCL) circuit. The control stage of the PWCL with proposed frequency selection block can increase its output charge/discharge current at high frequency clocks. Therefore, narrow pulses can be generated at the output of this stage, which leads to the enhancement of the frequency range. Lock time of the circuit is also reduced, owing to the use of optimised second-order passive lead–lag loop filters instead of conventional loop filters. A 0.18-µm CMOS technology and 1.8-V supply voltage are used to verify the operation of the circuit. The simulation results show that the acceptable frequency range is from 200 MHz to 1.4 GHz, while maximum lock time of the circuit at this frequency range is about 580 ns. The proposed PWCL consumes 1 mW of power at 1.4 GHz.     

CMOS digital duty cycle correction circuit for multi-phase clock

A digital duty cycle correction circuit with a fixed-delay rising-edge output is proposed for use in applications with the multi-phase clock and the standby mode. Two integrators are used in the duty cycle detector to eliminate the effect of reference voltage variations. The output duty cycle is adjusted to 50/spl plusmn/0.25% throughout the input duty cycle range from 20% to 80% at the frequency of 1.25 GHz. 0.18 /spl mu/m CMOS technology is used in this work.     

All-Digital Fast-Locked Synchronous Duty-Cycle Corrector

An all-digital fast-locked synchronous duty-cycle corrector is presented. It corrects the duty cycle and synchronizes the input and output clocks in 10 clock cycles. The proposed circuit has been fabricated in a 0.18-mum CMOS technology. The measured duty-cycle error is between 1.5% and -1.4% for the input duty cycle of 40%~60%. The measured peak-to-peak jitter is 12.9ps at 1GHz. The measured operation frequency range is from 0.8GHz to 1.2 GHz     

Low-voltage pulsewidth control loops for SOC applications

The proposed pulsewidth control loop (PWCL) adopts the same architecture as the conventional PWCL, but with a new duty-cycle detector and a new pulse generator. Using the new building block circuits, the clock frequency can be increased tremendously, and the output of the PWCL has fixed rising edge, which will not disturb the phase-locking result by a preceding phase-locked loop (PLL) or delay-locked loop (DLL). This means that the clock buffer can include a PLL/DLL and a PWCL to perform phase locking as well as pulsewidth adjustment simultaneously. All the building blocks used in the new PWCL have simple circuit structures that are suitable for low-voltage operation. A test chip is implemented in a 0.35-/spl mu/m CMOS process with only 1.8-V V/sub DD/ successfully generates a clock signal with a 0.6-ns pulsewidth for a heavily pipelined multiplier to operate at 400 MHz. The features of operating at low voltage, providing variable duty cycle, and being able to cooperate with PLL/DLL make the new PWCL suitable for system-on-chip (SOC) applications.     

Unified all-digital duty-cycle and phase correction circuit for QDR I/O interface

A unified all-digital duty-cycle and phase correction circuit, consisting of dual duty cycle corrector loops and one shared control block, is proposed for a quadrature data rate I/O interface. The proposed scheme makes four duty-corrected and phase-corrected phase clocks from two clocks of 08 and 908 using the sequential three steps correction. The use of a newly devised duty cycle detector, which is digitally operated without external reference voltage, is proposed. With simulated results using 0.18 μm CMOS technology, the output duty cycle is corrected to 50 + 0.4% as the input duty cycle ranges from 40 to 60%. The phase difference with the four-phase output clock is adjusted to 50± 0.6% (250±3 ps) as the input phase-skew ranges from 40 to 60% (250±50 ps) at a frequency of 1 GHz.     

A low-jitter mutual-correlated pulsewidth control loop circuit

This work presents a low-jitter pulsewidth control loop (PWCL) circuit. A mutual-correlated scheme is implemented to adjust the duty cycle and increase the stability of the PWCL. The design is less sensitive to process variation. The jitter induced by voltage ripple is suppressed. The circuit is implemented using 0.35 /spl mu/m 1P4M CMOS process. The area of the PWCL is 136 /spl times/ 143 /spl mu/m/sup 2/. At an operating frequency of 300 MHz, the power dissipation and voltage ripple are reduced by 35.4% and 93.7%, respectively. A test chip is successfully verified to obtain 42-ps jitter at an operating frequency of 900 MHz.     

一种新型超高速高精度时钟占空比校准电路

设计了一种超高速高精度时钟占空比校准电路。采用一种新的脉冲宽度校准单元,通过控制电压调整时钟上升、下降时间来实现占空比调整。同时,设计了一种时钟放大模块,降低了占空比校准单元对输入时钟幅度的要求,提高了占空比校准精度。分析了各电路模块的作用以及对整体性能的影响。采用SMIC 65 nm CMOS工艺,在1.8 V电源电压下对各模块以及整体电路进行仿真验证。仿真结果表明,该时钟占空比校准电路能对输入频率为1～4 GHz、占空比为20%～80%的时钟进行精确校准,校准后的占空比为(50±1)%,系统稳定时间为200个输入时钟周期,功耗为10 mW。     

基于FPGA的虚拟通用计数器/信号源集成

将通用计数器与信号源集成于FPGA内，借助EPP实现与PC机的通信，以Delphi实现虚拟图形化界面。采用等精度等测量技术和余数插补法，虚拟地实现2个通道0．1Hz～10MHz信号的频率、周期、占空比、脉宽、计数及其频率比、相位差、时间间隔测量，1个扩展通道10MHz～1GHz信号的频率、周期、计数测量，和1个通道频率、占空比、幅度、直流分量步进可调的矩形波(1Hz～1MHz)、正弦波(1Hz～16kHz)等信号的产生。重点介绍了其系统EDA设计、仿真及实验结果。实验表明，本设计是切实可行的。     

Broadband electronically tunable planar active radiating elementsand spatial power combiners using notch antennas

A Gunn device has been integrated with two types of active planar notch antennas. The first types uses a coplanar waveguide (CPW) resonator an a stepped-notched antenna with bias tuning to achieve a bandwidth of 275 MHz centered at 9.33 GHz with a power output of 14.2±1.5 dBm. The second type uses a CPW resonator with a varactor for frequency tuning to achieve a bandwidth of over 1.3 GHz centered at 9.6 GHz with a power output of 14.5±0.8 dBm. This is equivalent to over 14% electronic tuning bandwidth. Both configurations exhibit a very clean and stable output signal. A theoretical circuit model was developed to facilitate the design. The model agrees well with experimental results. Injection-locking experiments on the second configuration show a locking gain of 30 dB with a locking bandwidth of 30 MHz at 10.2 GHz. Power combining experiments of two-varactor-tuned CPW active notch antenna elements in a broadside configuration have achieved well over 70% combining efficiency throughout the wide tuning range. The circuits have advantages of small size, low cost, and excellent performance     

一种基于差动放大器的超高速脉宽调整电路

设计了一种用于超高速A/D转换器的脉宽调整电路。以基准输出电压为参照,利用差动放大器输出控制时钟输出占空比,最高可工作在1.7 GHz时钟频率下,锁定精度为50%±1%;拥有20%～80%占空比输入,且能很好地抑制时钟抖动。电路采用0.18μm工艺制作,芯片面积为0.3 mm×0.1 mm,在1.9 V电源电压下,功耗小于40 mW。     

A Broadband CMOS Frequency Tripler Using a Third-Harmonic Enhanced Technique

A third harmonic enhanced technique is proposed to implement a broadband and low-phase-noise CMOS frequency tripler. It nonlinearly combines a pair of differential fundamental signals to generate deep cuts at the peaks of the fundamental waveform, resulting in a strong third harmonic frequency output. This mechanism has inherent suppression on the fundamental and the other harmonics so that only a low-Q high-pass filter on the lossy silicon substrate is applied at the output to further reject the fundamental and the second harmonic frequencies, in contrast to the high-Q filters used in most of the previous tripler designs. The fabricated circuit using 0.18 m CMOS technology is compact and has an input frequency range from 1.7 GHz to 2.25 GHz, or an output frequency range from 5.1 GHz to 6.75 GHz, resulting in about 28% frequency bandwidth. The optimum conversion loss from the tripler is 5.6 dB (27.5% efficiency) at an input power of 2 dBm. The suppressions for the fundamental, second and fourth harmonics in the measurement are better than 11 dB, 9 dB, and 20 dB within an input power range from 2 dBm to 7 dBm.