Small-signal high-frequency response of the insulated-gate field-effect transistor

A complete solution is presented for the small-signal high-frequency response of an idealized model of the insulated-gate field-effect transistor. Theyparameters are found by solving Bessel's equation and are plotted as functions of signal frequency and the quiescent conditions. In addition to these general results, simple approximate results that apply only beyond the point of pinch-off are derived for operation at moderately low frequencies.     

Negative resistance of a modified insulated-gate field-effect transistor

The current-voltage characteristics of a new circuit element showing negative resistance are described and analyzed. The device is an enhancement field-effect transistor interacting with a bipolar transistor.     

Modeling and simulation of insulated-gate field-effect transistor switching circuits

A new equivalent circuit for the insulated-gate field-effect transistor (IGFET) is described. This device model is particularly useful for computer-aided analysis of monolithic integrated IGFET switching circuits. The results of computer simulations using the new equivalent circuit are in close agreement with experimental observations. As an example of a practical application, simulation results are shown for an integrated circuit IGFET memory cell.     

A two-dimensional mathematical model of the insulated-gate field-effect transistor

This paper is concerned with the mathematical details of a numerical model of the insulated-gate field-effect transistor; a computer-aided analysis of the device, based on this model, appears separately. A finite-difference scheme is presented for obtaining an approximate solution of a system of nonlinear elliptic partial differential equations describing the carrier distribution in such a device model. In particular, our scheme allows the device current, as a function of the applied bias voltages, to be reliably calculated. The results of numerical experiments appraising the accuracy of the method are also included.     

A time-dependent numerical model of the insulated-gate field-effect transistor

A new method is described for computing the flow of mobile carriers in a semiconductor device, in two space dimensions plus time. In this method, each variable is updated separately, and in each step only linear systems of equations are solved. The method is stable, independently of the time step. Various current components are resolved by stream functions, and current balance is maintained.A sample computation is included, involving the switching off of an n-channel IGFET.     

A general four-terminal charging-current model for the insulated-gate field-effect transistor—I

A general form of equivalent circuit model for the IGFET is presented in which a complete representation is given of the charging currents in the device. At the heart of the model is the essential step of “partitioning” the channel charging current between the source and drain terminals. This is carried out in terms of the distinct physical mechanisms associated with the charging of the device via the gate and substrate terminals respectively. The circuit elements of the model are all defined on a quasi-static (charge control) basis by the relationships between the charges stored in the IGFET and the voltages applied to its four terminals.     

Physical processes in insulated-gate field-effect transistors

The current-voltage characteristics of insulated-gate field-effect transistors have been calculated for arbitrary ratios of the gate insulator-semiconductor thickness. Comparison of the calculations to experimental results with CdS thin film transistors shows a good correspondence for both enhancement and depletion type units. It is found that the failure of experimental devices to show current saturation for drain voltages beyond pinch-off can be attributed to the presence of partially ionised donors at the CdS-SiO interface.     

An InAs channel heterojunction field-effect transistor with hightransconductance

A report is presented on an InAs channel field-effect transistor (FET) based on AlGaSb/InAs/AlSb/AlGaSb structures grown by molecular-beam epitaxy. Excellent pinch-off characteristics have been obtained. An FET with a gate length of 1.7 μm showed transconductances ranging from 460 mS/mm (at V_ds=0.5 V) to 509 mS/mm (at V_ds=1 V) and a K factor of 1450 mS/Vmm (at V_ds=1 V) at room temperature     

The transient response of insulated-gate field-effect transistors

The equations describing the current flow and charge distribution in insulated-gate field-effect transistors are developed. These include Ohm's law, the continuity equation and the trapping equation when it is assumed that only one trapping level is dominant. The boundary conditions at the source, at the drain and at the gate insulator-semiconductor surface are also included. The result is a set of non-linear partial differential equations, whose solution is obtained by numerical methods.

The important physical properties of the gate insulator-semiconductor surface are: the initial lifetime of free carriers, the lifetime of a carrier in a trap, the density of trap sites, the initial ratio of trapped carriers to trap sites and the carrier mobility. The important geometrical properties of the device are the gate insulator thickness and the channel length. Solutions for various values of these parameters are given.     

Modulation of space-charge-limited current flow in insulated-gate field-effect tetrodes

The electrical characteristics of n-channel depletion-type and p-channel enhancement-type space-charge-limited tetrodes are presented. The devices are derived from the MOSFET structure and are fabricated on nearly intrinsic silicon substrates with very small channel lengths. In both structures, the current flowing between drain and source can be modulated by either of two high-impedance control terminals. The dominant conduction mechanism is space-charge-limited current flow, and the observed current-voltage characteristics of each device follow the Mott and Gurney relationship at high current levels.     

Ambipolar field-effect transistor

The results of measurements performed on an amorphous-silicon thin-film transistor structure are presented and interpreted. The device characteristics show a continuous alternation between n-channel and p-channel operation, an “ambipolar” effect that is made possible by the provision of ohmic source and drain contacts.     

Vacuum-insulated-gate field-effect transistor

A vacuum-insulated-gate field-effect transistor (VIGFET) is fabricated using a modified polysilicon-gate MOS process. The vacuum insulation is formed by first selectively etching the initial SiO/sub 2/ layer under the polysilicon gate in HF and then depositing LPCVD SiO/sub 2/ (LTO) to seal the evacuated cavity under the gate. Initial measurements of n-channel FET drain characteristics result in an effective value for the channel-electron mobility*gate capacitance product of k'= mu /sub n/C'=21 mu A V/sup -2/, comparable to that of conventional MOSFETs.<>     

Impedance and noise in the channel of a GaAs Schottky-gate field-effect transistor

The behaviour of the impedance and noise of the channel of a GaAs Schottky-gate field effect transistor is experimentally analyzed in the temperature range 77–300K and in the frequency range of 150 to 900 MHz. The channel of the transistor (source and gate being short circuited) shows a thermal noise level in good agreement with van der Ziel's theory. At 77K, the observed excess of the noise temperature is attributed to an effect of hot carriers.     

V-shaped notched-channel field-effect transistor

A junction field-effect transistor with a V-shaped notched channel fabricated by preferential etching of (100) silicon is described. This transistor exhibits a higher maximum transconductance and a lower turn-on resistance than conventional silicon f.e.t.s. with rectangular channels. The fabrication, characteristics and possible applications of this device are described.     

Vertical tunnel field-effect transistor

The realization of a novel vertically grown tunnel field-effect transistor (FET) with several interesting properties is presented. The operation of the device is shown by means of both experimental results as well as two-dimensional computer simulations. This device consists of a MBE-grown, vertical p-i-n structure. A vertical gate controls the band-to-band tunneling width, and hence the tunneling current. Both n-channel and p-channel current behavior is observed. A perfect saturation in drain current-voltage (I/sub D/--V/sub DS/) characteristics in the reverse-biased condition for n-channel, an exponential and nearly temperature independent drain current-gate voltage (I/sub D/--V/sub GS/) relation for both subthreshold, as well as on-region, and source-drain off-currents several orders of magnitude lower then the conventional MOSFET are achieved. In the forward-biased condition, the device shows normal p-i-n diode characteristics.     

Dipole heterostructure field-effect transistor

It is proposed to reduce the gate current by using a dipole created by two doped planes, n⁺⁺ and p⁺⁺, in charge control layer, dipole heterostructure field-effect transistors (dipole HFETs) fabricated in AlGaAs/GaAs use doped p⁺⁺ and n ⁺⁺ planes in the charge control AlGaAs layer to form a dipole that provides a considerably larger barrier between the channel and the gate than that in conventional heterostructure FETs. This leads to a reduction of the forward-biased gate current in enhancement-mode n-channel devices, by a factor of approximately 9 at 1.2 V in the experimental devices, when compared with equivalent conventional HFETs. A much broader transconductance region, in the range of 0.5-2.5-V gate bias, a higher maximum drain current, and no negative transconductance are also observed. A comparison between the gate current-voltage characteristics of conventional and dipole HFETs for 1-μm-long and 10-μm-wide gate devices is given. The measured results clearly indicate that a dipole HFET has a much smaller gate leakage current leading to superior performance of enhancement-mode devices. The results demonstrate the effectiveness of the dipole layer concept for digital HFET devices