计算机网络安全故障分析与排除

针对计算机网络故障越来越多的现象,首先介绍了计算机网络常见的故障,然后提出了解决网络故障的一般步骤,常用工具,最后结合实例对网络故障进行了诊断和处理。     

Feature-based classifier ensembles for diagnosing multiple faults in rotating machinery

Recent researches in fault classification have shown the importance of accurately selecting the features that have to be used as inputs to the diagnostic model. In this work, a multi-objective genetic algorithm (MOGA) is considered for the feature selection phase. Then, two different techniques for using the selected features to develop the fault classification model are compared: a single classifier based on the feature subset with the best classification performance and an ensemble of classifiers working on different feature subsets. The motivation for developing ensembles of classifiers is that they can achieve higher accuracies than single classifiers. An important issue for an ensemble to be effective is the diversity in the predictions of the base classifiers which constitute it, i.e. their capability of erring on different sub-regions of the pattern space. In order to show the benefits of having diverse base classifiers in the ensemble, two different ensembles have been developed: in the first, the base classifiers are constructed on feature subsets found by MOGAs aimed at maximizing the fault classification performance and at minimizing the number of features of the subsets; in the second, diversity among classifiers is added to the MOGA search as the third objective function to maximize. In both cases, a voting technique is used to effectively combine the predictions of the base classifiers to construct the ensemble output. For verification, some numerical experiments are conducted on a case of multiple-fault classification in rotating machinery and the results achieved by the two ensembles are compared with those obtained by a single optimal classifier.     

On finding minimal-length test sets for diagnosing faults in combinational circuits

A fault-detection matrix contains sufficient information for finding minimal-length, fault-diagnosis test sets. The necessary and sufficient condition is that the submatrix of the fault-detection matrix must not contain equal rows. Cited examples demonstrate that characteristics in the fault-detection matrix can be used to facilitate the search for tests.     

A multi-agent architecture for diagnosing simultaneous faults along water canals

Water is intensively used in mankind activities, in particular in agriculture. Water is commonly conveyed for agriculture purposes through water canal networks which are large-scale spatially distributed systems crossing extensive regions. In the presence of leaks, unauthorized water withdrawals, water depth sensor faults or gate faults, the quality of service can be severely compromised. A system able to diagnose which type of fault is present at a given time is of vital importance to access the current state of the water canal and proceed to restore its nominal condition. This paper proposes a multi-agent architecture to simultaneously detect, isolate and estimate lateral outflows (e.g., leaks or water withdrawals) and hardware faults (e.g., a gate obstruction or a downstream water depth sensor fault) in water canal networks. First, the main canal network is broken down into several subsystems composed of a single canal pool with the corresponding gate. Then, an agent is assigned to each subsystem aiming at its fault diagnosis. The approach is based on the generation and evaluation of residuals obtained from the comparison of model-based output signals with real data. Application to an experimental water canal bears out the proposed architecture as a valuable tool for monitoring and supervising general water canals.     

A simple and efficient method for diagnosing equipment faults based on quantitative physical knowledge

This paper proposes a method for identifying and locating the origin of a fault of a piece of equipment using approximate linear quantitative equations of variable increments which are derived from equations representing the steady state of the equipment and measured values of the variables. The proposed method differs fundamentally from strict numerical simulation methods and qualitative methods. Although the solution which is obtained by the proposed method is approximate, it is devised so that errors which are contained in them can be reduced. The proposed method, because only linear equations are dealt with, has the advantage of being easy to implement and process and of taking much less computation time.     

A multiple observers and dynamic weighting ensembles scheme for diagnosing new class faults in wind turbines

This paper presents an incremental way to design the decision module of a diagnostic system by resorting to dynamic weighting ensembles of classifiers. The method is applied for sensor fault detection and isolation in a doubly fed induction generator for wind turbine application. Three sets of observers are combined to generate residuals that are robust to operating point changes. These signals are progressively fed into a dynamic weighting ensembles algorithm, called Learn⁺⁺.NC, for fault classification. The algorithm incrementally learns the residuals–faults relationships and dynamically classifies the faults including multiple new classes. It resorts to a dynamically weighted consult and vote mechanism to combine the outputs of the base-classifiers.     

Detecting and diagnosing faults in dynamic stochastic distributions using a rational B-splines approximation to output PDFs

This paper presents a novel approach to detect and diagnose faults in the dynamic part of a class of stochastic systems . the Such a group of systems are subjected to a set of crisp inputs but the outputs considered are the measurable probability density functions (PDFs) of the system output, rather than the system output alone. A new approximation model is developed for the output probability density functions so that the dynamic part of the system is decoupled from the output probability density functions. A nonlinear adaptive observer is constructed to detect and diagnose the fault in the dynamic part of the system. Conver-gency analysis is performed for the error dynamics raised from the fault detection and diagnosis phase and an applicability study on the detection and diagnosis of the unexpected changes in the 2D grammage distributions in a paper forming process is included.     

Multi-decision diagnosis: decentralized architectures cooperating for diagnosing the presence of faults in discrete event systems

This article deals with decentralized diagnosis, where a set of diagnosers cooperate for detecting faults in a discrete event system. We propose a new framework, called multi-decision diagnosis, whose basic principle consists in using several decentralized diagnosis architectures working in parallel. We first present a generic form of multi-decision diagnosis, where several decentralized diagnosis architectures work in parallel and combine their global decisions disjunctively or conjunctively. We then study in more detail the inference-based multi-decision diagnosis, that is, in the case where each of the decentralized architectures in parallel is based on the inference-based framework. We develop a method that checks if a given specification is diagnosable under the inference-based multi-decision architecture. We also show that with our method, the worst-case computational complexity for checking codiagnosability for our inference-based multi-decision architecture is in the same order of complexity as checking codiagnosability for the inference-based architecture designed by Kumar and Takai. In fact, multi-decision diagnosis is fundamentally undecidable and we have formulated a decidable variant of it. Multi-decision diagnosis is formally based on language decomposition, but it is worth noting that our objective is not to answer the existential question of language decomposition in the general case. Our objective is rather to propose a decentralized diagnosis architecture that generalizes the decidable existing ones.     

Efficient residuals pre-processing for diagnosing multi-class faults in a doubly fed induction generator,under missing data scenarios

This paper focuses on the development of a pre-processing module to generate the latent residuals for sensor fault diagnosis in a doubly fed induction generator of a wind turbine. The pre-processing module bridges a gap between the residual generation and decision modules. The inputs of the pre-processing module are batches of residuals generated by a combined set of observers that are robust to operating point changes. The outputs of the pre-processing module are the latent residuals which are progressively fed into the decision module, a dynamic weighting ensemble of fault classifiers that incrementally learns the residuals-faults relationships and dynamically classifies the faults including multiple new classes.The pre-processing module consists of the Wold cross-validation algorithm along with the non-linear iterative partial least squares (NIPALS) that projects the residual to the new feature space, extracts the latent information among the residuals and estimates the optimal number of principal components to form the latent residuals. Simulation results confirm the effectiveness of this approach, even in the incomplete scenarios, i.e., the missing data in the batches of generated residuals due to sensor failures.     

Minimizing FPGA interconnect delays

Optimizing FPGA routing architectures for speed performance also involves improving the CAD tools for mapping circuits. We provide a detailed example of how to design FPGA architectures by examining several important issues associated with interconnect resources for FPGAs that use SRAM programming technology. Our experiments examine two important metrics: the speed performance of implemented circuits and the effective use of available interconnect resources. The goal is to improve upon FPGA speed performance by decreasing delays associated with the interconnect. Our results are most directly applicable to FPGA architectures similar in style to the Xilinx XC4000 series. However, some significant results are of a more general nature and perhaps applicable to other styles of FPGAs as well. In addition to routing architectures, we address the CAD tools that allocate these routing resources to implement circuits     

SerialExpress-a high performance workstation interconnect

As part of the IEEE P2100 working group, we produced a SerialExpress draft standard that specifies a high-performance interconnect for use with workstations. Our goal was to develop an inexpensive, efficient, robust, scalable protocol for use in system area network (SAN) applications. Within this environment, we used buslike read and write transactions to provide an efficient mechanism for transferring data and controlling information between processor and I/O nodes. Our bandwidth, distance, and latency goals mandated the concurrent transmission of small (64-byte) packets to avoid the arbitration delay constraints of a broadcast bus protocol. We also wanted our solution to scale over a wide range of technologies. This article discusses the resulting draft standard, focusing on the technical aspects. In the future, we plan to address its implementation technologies and implications. This draft defines a protocol for low-cost, technology-independent, high-bandwidth, low-latency, and distance-insensitive interconnections for system area network applications     

Spider: a high-speed network interconnect

SGI's Spider chip-Scalable, Pipelined Interconnect for Distributed Endpoint Routing-create a scalable, short-range network delivering hundreds of gigabytes per second in bandwidth to large configurations. Individual Spider chips sustain a 4.8-Gbyte/s switching rate, connecting to each other and to endpoints across cables up to 5 meters in length. By delivering very high bandwidth-thousands of times higher than standard Ethernet-at low latencies, Spider is ideal for CPU interconnect applications, high-end network switches, or high-performance graphics interconnects. The Spider chip design drew on the principles of computer communications architecture. Isolation between the physical, data link, and message layers led to a well-structured design that is transportable and more easily verified than a nonlayered solution. Because the chip implements all layers in hardware, latency is very low. Thus, we could realize the benefits of layering without sacrificing performance     

Asynchronous interconnect for synchronous SoC design

System-on-chip (SoC) designs integrate a variety of cores and I/O interfaces, which usually operate at different clock frequencies. Communication between unlocked clock domains requires careful synchronization, which inevitably introduces metastability and some uncertainty in timing. Thus, any chip with multiple clock domains is already globally asynchronous. We have devised a more elegant and efficient solution to the multiple-clock-domain problem. Instead of gluing synchronous domains directly to each other with clock-domain bridges, we use asynchronous-circuit design techniques to handle all clock-domain crossing as well as all cross-chip communication and routing. The phase-locked loop (PLL) and clock distribution can be entirely local to each synchronous core, easing timing closure and improving the reusability of cores across multiple designs. Our solution, Nexus, is a globally asynchronous, locally synchronous (GALS) interconnect that features a 16-port, 36-bit asynchronous crossbar. The crossbar connects through asynchronous channels to clock-domain converters for each synchronous module. To ensure that Nexus will work robustly in a commercial application, we developed and applied many verification and test strategies, including novel variations of noise analysis, timing analysis, and fault and delay testing.     

Testing the interconnect of RAM-based FPGAs

Testing FPGAs before user programming can be an expensive procedure. Applying their general test configuration and test pattern generation methodology, the authors devise an efficient test procedure for the interconnect structure and demonstrate its applicability to commercial FPGAs     

Finding and fixing faults

Knowing that a program has a bug is good, knowing its location is better, but a fix is best. We present a method to automatically locate and correct faults in a finite state system, either at the gate level or at the source level. We assume that the specification is given in Linear Temporal Logic, and state the correction problem as a game, in which the protagonist selects a faulty component and suggests alternative behavior. The basic approach is complete but as complex as synthesis. It also suffers from problems of readability: the correction may add state and logic to the system. We present two heuristics. The first avoids the doubly exponential blowup associated with synthesis by using nondeterministic automata. The second heuristic finds a memoryless strategy, which we show is an NP-complete problem. A memoryless strategy corresponds to a simple, local correction that does not add any state. The drawback of the two heuristics is that they are not complete unless the specification is an invariant. Our approach is general: the user can define what constitutes a component, and the suggested correction can be an arbitrary combinational function of the current state and the inputs. We show experimental results supporting the applicability of our approach.     

On-chip optical interconnect using visible light

We propose and fabricate a monolithic optical interconnect on a GaN-on-silicon platform using a wafer-level technique. Because the InGaN/GaN multiple-quantum-well diodes (MQWDs) can achieve light emission and detection simultaneously, the emitter and collector sharing identical MQW structure are produced using the same process. Suspended waveguides interconnect the emitter with the collector to form in-plane light coupling. Monolithic optical interconnect chip integrates the emitter, waveguide, base, and collector into a multi-component system with a common base. Output states superposition and 1×2 in-plane light communication are experimentally demonstrated. The proposed monolithic optical interconnect opens a promising way toward the diverse applications from in-plane visible light communication to light-induced artificial synaptic devices, intelligent display, on-chip imaging, and optical sensing.     

外置预加重均衡器在高速背板互联中的应用

<正>高速串行接口由于连接简单、数据吞吐量大和先天的共模干扰抑制优势,成为背板互联的首选接口。然而由于传输线、连接器以及过孔对高频信号的衰减,对于这些背板互联应用,如何保证信号的衰减被完全补偿,以及如何保证设计时留有足够的余量