通用逻辑门电路的SET实现及应用

通用逻辑门具有更强的逻辑功能,相比传统逻辑门更适合作为阵列逻辑单元。单电子晶体管（SingleElectronTransistor,SET）被认为是众多纳米电子器件中的强有力竞争者。为了拓展SET的应用,减少逻辑综合所用逻辑门的种类,提出了通用逻辑门的SET电路实现方案,设计出基于sET的通用逻辑门树形结构的全比较器等电路,用Hspicer软件对所设计的电路进行仿真,结果表明,该电路具有正确的逻辑功能,为SET通用逻辑门的进一步研究应用奠定了基础。     

Electronic devices based on purified carbon nanotubes grown by high-pressure decomposition of carbon monoxide

The excellent properties of transistors, wires and sensors made from single-walled carbon nanotubes (SWNTs) make them promising candidates for use in advanced nanoelectronic systems. Gas-phase growth procedures such as the high-pressure decomposition of carbon monoxide (HiPCO) method yield large quantities of small-diameter semiconducting SWNTs, which are ideal for use in nanoelectronic circuits. As-grown HiPCO material, however, commonly contains a large fraction of carbonaceous impurities that degrade the properties of SWNT devices. Here we demonstrate a purification, deposition and fabrication process that yields devices consisting of metallic and semiconducting nanotubes with electronic characteristics vastly superior to those of circuits made from raw HiPCO. Source-drain current measurements on the circuits as a function of temperature and backgate voltage are used to quantify the energy gap of semiconducting nanotubes in a field-effect transistor geometry. This work demonstrates significant progress towards the goal of producing complex integrated circuits from bulk-grown SWNT material.     

Silica nanowires fabricated with layer-by-layer self-assembled nanoparticles

In this paper we demonstrate an approach to fabricate silica nanowires by combining "top-down" e-beam lithography and "bottom-up" layer-by-layer (LbL) nano self-assembly techniques. The simple and low-cost LbL self-assembly technique is used to grow silica nanoparticle thin film, while the e-beam lithography based lift-off technique is implemented to pattern the self-assembled thin film to nanometer scale. The silica nanowires fabricated by this method have an average width of 90 nm, while the minimum width obtained is 63 nm. Our experimental results indicate a new approach to fabricate nanowires that can be used in nanoelectronic devices and circuits.     

Failure analysis requirements for nanoelectronics

Failure analysis (FA) plays a vital role in the development and manufacture of integrated circuits. However, instrumental limits are already threatening FA in the tenth-micron CMOS realm, and nanoelectronic devices will find key analytical tools two orders of magnitude removed in capability. This paper will introduce state-of-the-art microelectronic failure analysis processes, instrumentation, and principles. It will discuss the major limitations and future prospects determined from industry roadmaps. Specifically highlighted is the need for a fault isolation methodology for failure analysis of fully integrated nanoelectronics devices.     

Implementation of high speed optical universal logic gates using the electro-optic effect-based Mach–Zehnder interferometer structures

The universal logic gates are the most important logic gates responsible for optimized design of different types of complex digital logic circuits. It is of great interest to implement the function of universal logic gates such as NAND and NOR logic gates using the concepts of electro-optic effect. The smart use of electro-optic effect can provide very effective optical power switching devices. The implementation of universal logic gates operation in the optical domain can improve the performance of the devices and includes the advantages of the optical communication system. The proper configuration of Mach–Zehnder interferometer working on the principle of electro-optic effect can provide the optical responses equivalent to the NAND and NOR logic gates. The proposed devices can be analyzed to check the various performance affecting parameters in order to specify the physical parameters.     

Nanoscale impedance microscopy-a characterization tool for nanoelectronic devices and circuits

A recently developed conductive atomic force microscopy (cAFM) technique, nanoscale impedance microscopy (NIM), is presented as a characterization strategy for nanoelectronic devices and circuits. NIM concurrently monitors the amplitude and phase response of the current through a cAFM tip in response to a temporally periodic applied bias. By varying the frequency of the driving potential, the resistance and reactance of conductive pathways can be quantitatively determined. Proof-of-principle experiments show 10-nm spatial resolution and ideal frequency-dependent impedance spectroscopy behavior for test circuits connected to electron beam lithographically patterned electrode arrays. Possible applications of NIM include defect detection and failure analysis testing for nanoscale integrated circuits.     

Design of synthetic biological logic circuits based on evolutionary algorithm

The construction of an artificial biological logic circuit using systematic strategy is recognised as one of the most important topics for the development of synthetic biology. In this study, a real‐structured genetic algorithm (RSGA), which combines general advantages of the traditional real genetic algorithm with those of the structured genetic algorithm, is proposed to deal with the biological logic circuit design problem. A general model with the cis ‐regulatory input function and appropriate promoter activity functions is proposed to synthesise a wide variety of fundamental logic gates such as NOT, Buffer, AND, OR, NAND, NOR and XOR. The results obtained can be extended to synthesise advanced combinational and sequential logic circuits by topologically distinct connections. The resulting optimal design of these logic gates and circuits are established via the RSGA. The in silico computer‐based modelling technology has been verified showing its great advantages in the purpose.Inspec keywords: biocomputing, biological techniques, combinational circuits, genetic algorithms, logic design, logic gates, sequential circuitsOther keywords: in silico computer‐based modelling, RSGA, sequential logic circuits, XOR gates, NOR gates, NAND gates, OR gates, AND gates, Buffer gates, NOT gates, fundamental logic gates, cis‐regulatory input function, real‐structured genetic algorithm, artiflcial biological logic circuit design     

Field‐Free Programmable Spin Logics via Chirality‐Reversible Spin–Orbit Torque Switching

Spin–orbit torque (SOT)‐induced magnetization switching exhibits chirality (clockwise or counterclockwise), which offers the prospect of programmable spin‐logic devices integrating nonvolatile spintronic memory cells with logic functions. Chirality is usually fixed by an applied or effective magnetic field in reported studies. Herein, utilizing an in‐plane magnetic layer that is also switchable by SOT, the chirality of a perpendicular magnetic layer that is exchange‐coupled with the in‐plane layer can be reversed in a purely electrical way. In a single Hall bar device designed from this multilayer structure, three logic gates including AND, NAND, and NOT are reconfigured, which opens a gateway toward practical programmable spin‐logic devices.     

High performance ring oscillators from 10-nm wide silicon nanowire field-effect transistors

We explore 10-nm wide Si nanowire (SiNW) field-effect transistors (FETs) for logic applications, via the fabrication and testing of SiNW-based ring oscillators. We report on SiNW surface treatments and dielectric annealing, for producing SiNW FETs that exhibit high performance in terms of large on/off-state current ratio (∼10⁸), low drain-induced barrier lowering (∼30 mV) and low subthreshold swing (∼80 mV/decade). The performance of inverter and ring-oscillator circuits fabricated from these nanowire FETs are also explored. The inverter demonstrates the highest voltage gain (∼148) reported for a SiNW-based NOT gate, and the ring oscillator exhibits near rail-to-rail oscillation centered at 13.4 MHz. The static and dynamic characteristics of these NW devices indicate that these SiNW-based FET circuits are excellent candidates for various high-performance nanoelectronic applications.      

Tunable Spin Characteristic Properties in Spin Valve Devices Based on Hybrid Organic–Inorganic Perovskites

The hybrid organic–inorganic perovskites (HOIPs) form a new class of semiconductors which show promising optoelectronic device applications. Remarkably, the optoelectronic properties of HOIP are tunable by changing the chemical components of their building blocks. Recently, the HOIP spintronic properties and their applications in spintronic devices have attracted substantial interest. Here the impact of the chemical component diversity in HOIPs on their spintronic properties is studied. Spin valve devices based on HOIPs with different organic cations and halogen atoms are fabricated. The spin diffusion length is obtained in the various HOIPs by measuring the giant magnetoresistance (GMR) response in spin valve devices with different perovskite interlayer thicknesses. In addition spin lifetime is also measured from the Hanle response. It is found that the spintronic properties of HOIPs are mainly determined by the halogen atoms, rather than the organic cations. The study provides a clear avenue for engineering spintronic devices based on HOIPs.     

Operation and Modeling of Semiconductor Spintronics Computing Devices

Semiconductor spintronic devices are considered from the point of view of suitability for digital logic. Functionality of earlier proposed devices is reviewed for cascadability and signal gain. Spin gain transistor, which uses electronic control of ferromagnetism in semiconductors, is treated in more detail via semiconductor Bloch equations for both localized and free-carrier magnetic moments. Dependence of the steady state magnetization and temporal switching characteristics on material parameters is determined. Finally, fundamental physical limits for spintronic devices are determined via use of an idealized model. They are compared with similar limits for electronic devices. It is found that, though spintronic devices switch slower, their switching energy is smaller, therefore they scale with size on a curve with lower power dissipation.     

Renewable Time‐Responsive DNA Circuits

DNA devices have been shown to be capable of evaluating Boolean logic. Several robust designs for DNA circuits have been demonstrated. Some prior DNA‐based circuits are use‐once circuits since the gate motifs of the DNA circuits get permanently destroyed as a side effect of the computation, and hence cannot respond correctly to subsequent changes in inputs. Other DNA‐based circuits use a large reservoir of buffered gates to replace the working gates of the circuit and can be used to drive a finite number of computation cycles. In many applications of DNA circuits, the inputs are inherently asynchronous, and this necessitates that the DNA circuits be asynchronous: the output must always be correct regardless of differences in the arrival time of inputs. This paper demonstrates: 1) renewable DNA circuits, which can be manually reverted to their original state by addition of DNA strands, and 2) time‐responsive DNA circuits, where if the inputs change over time, the DNA circuit can recompute the output correctly based on the new inputs, that are manually added after the system has been reset. The properties of renewable, asynchronous, and time‐responsiveness appear to be central to molecular‐scale systems; for example, self‐regulation in cellular organisms.     

Demultiplexers for Nanoelectronics Constructed From Nonlinear Tunneling Resistors

When using linear resistors to implement nanoelectronic resistor-logic demultiplexers, codes can be used to improve the voltage margins of these circuits. However, the resistors which have been fabricated in nanoscale crossbars are observed to be nonlinear in their current versus voltage (I-V) characteristics, showing an exponential dependence of current on voltage; we call these devices tunneling resistors. The introduction of nonlinearity can either improve or degrade the voltage margin of a demultiplexer circuit, depending on the particular code used. Therefore, the criterion for choosing codes must be redefined for demultiplexer circuits built from this type of nonlinear resistor. We show that for well-chosen codes, the nonlinearity of the resistors can be advantageous, producing a better voltage margin than can be achieved with linear resistors     

Recent Advances in Molecular Spintronics: Multifunctional Spintronic Devices

The field of spintronics has triggered an enormous revolution in information storage since the first observation of giant magnetoresistance (GMR). Molecular semiconductors are characterized by having very long spin relaxation times up to milliseconds, and are thus widely considered to hold immense potential for spintronic applications. Along with the development of molecular spintronics, it is clear that the study of multipurpose spintronic devices has gradually grown into a new research and development direction. The abundant photoelectric properties of molecular semiconductors and the intriguing functionality of the spinterface, together with novel designs of device structures, have promoted the integration of multiple functions and different mechanisms into discrete spintronic devices. Here, according to the different relationships between the integrated mechanisms, multifunctional molecular spintronic devices containing parallel and interactive types are highlighted. This is followed by the introduction of pure‐spin‐current‐type molecular spintronic devices that have already demonstrated great potential for multifunction exploration. Finally, the challenges and outlook that make this field young and energetic are outlined.     

Three-dimensional simulation of realistic single electron transistors

We present an approach, and its implementation in a computer program, for the three-dimensional (3-D) simulation of realistic single electron transistor (SET) structures, in which subregions with different degrees of quantum confinement are simultaneously considered. The proposed approach is based on the self-consistent solution of the many body Schrodinger equation with density functional theory and on the computation of the conductance of tunnel constrictions through the solution of the 3-D Schrodinger equation with open boundary conditions. We have developed an efficient code (ViDES) based on such an approach. As examples of addressable SET structures, we present the simulation of a SET, one defined by metal gates on an AlGaAs/GaAs heterostructures, and of a SET defined by etching and oxidation on the silicon-on-insulator material system. Since SETs represent prototypical nanoscale devices, the code may be a valuable tool for the investigation and optimization of a broad range of nanoelectronic solid-state devices.     

Low Schottky Barrier Black Phosphorus Field‐Effect Devices with Ferromagnetic Tunnel Contacts

Black phosphorus (BP) has been recently unveiled as a promising 2D direct bandgap semiconducting material. Here, ambipolar field‐effect transistor behavior of nanolayers of BP with ferromagnetic tunnel contacts is reported. Using TiO₂/Co contacts, a reduced Schottky barrier <50 meV, which can be tuned further by the gate voltage, is obtained. Eminently, a good transistor performance is achieved in the devices discussed here, with drain current modulation of four to six orders of magnitude and a mobility of μ_h ≈ 155 cm² V^?1 s^?1 for hole conduction at room temperature. Magnetoresistance calculations using a spin diffusion model reveal that the source–drain contact resistances in the BP device can be tuned by gate voltage to an optimal range for injection and detection of spin‐polarized holes. The results of the study demonstrate the prospect of BP nanolayers for efficient nanoelectronic and spintronic devices.     

On the Reliability of Majority Gates Full Adders

This paper studies the reliability of three different majority gates full adder (FA) designs, and compares them with that of a standard XOR-based FA. The analysis provides insights into different parameters that affect the reliability of FAs. The probability transfer matrix method is used to exactly calculate the reliability of the FAs under investigation. All simulation results show that majority gates FAs are more robust than a standard XOR-based FA. They also show how different gates affect the FAs' reliabilities and are extrapolated to give reliability estimates from the device level. Such reliability analyses should be used for a better characterization of FA designs for future nanoelectronic technologies, in addition to the well-known speed and power consumption (which have long been used for selecting and ranking FA designs).     

Molecular memory based on nanowire-molecular wire heterostructures

This article reviews the recent research of molecular memory based on self-assembled nanowire-molecular wire heterostructures. These devices exploit a novel concept of using redox-active molecules as charge storage flash nodes for nanowire transistors, and thus boast many advantages such as room-temperature processing and nanoscale device area. Various key elements of this technology will be reviewed, including the synthesis of the nanowires and molecular wires, and fabrication and characterization of the molecular memory devices. In particular, multilevel memory has been demonstrated using In2O3 nanowires with self-assembled Fe-bis(terpyridine) molecules, which serve to multiple the charge storage density without increasing the device size. Furthermore, in-depth studies on memory devices made with different molecules or with different functionalization techniques will be reviewed and analyzed. These devices represent a conceptual breakthrough in molecular memory and may work as building blocks for future beyond-CMOS nanoelectronic circuits.     

Effect of Electron and Hole Injection on Spin Polarization in Bis-(8-hydroxyquinoline) Zinc Molecule

Journal of Superconductivity and Novel Magnetism - The spintronic properties of molecules are essential for the development of multifunctional organic spintronic devices. Here, the spin...     

ZnO nanosquids: branching nanowires from nanotubes and nanorods

One-dimensional (1D) semiconductor nanostructures are promising building blocks for future nanoelectronic and nanophotonic devices. ZnO has proven to be a multifunctional and multistructural nanomaterial with promising properties. Here we report the growth of ZnO nanosquids which can be directly grown on planar oxidized Si substrates without using catalysts and templates. The formation of these nanosquids can be explained by the theory of nucleation, and the vapor-solid crystal growth mechanism. The branching nanowires of these ZnO nanosquids could have potential application in multiplexing future nanoelectronic devices. The sharp band-edge emission at approximately 380 nm indicates that these ZnO nanosquids are also applicable for interesting optoelectronic devices.