Investigation and minimization of underfill delamination in flip chip packages

A generalized plane strain condition is assumed for an edge interfacial crack between die passivation and underfill on an organic substrate flip chip package. C4 solder bumps are explicitly modeled. Temperature excursions are treated as loading conditions. The design factors studied include underfill elastic modulus, underfill coefficient of thermal expansion (CTE), fillet height, and die overhang. Varying underfill modulus and CTE produces a different stress field at underfill/die passivation interface, different stress intensity factor (SIF), and phase angle (/spl psi/) even under the same loading condition. The baseline case uses underfill with elastic modulus of 6 GPa, CTE of 36 ppm//spl deg/C and fillet height equal to half die thickness. Four more cases involving underfill material properties are investigated by varying elastic modulus between 3 and 9 GPa, and by varying CTE between 26 and 46 ppm//spl deg/C. The effect of fillet height is also studied by assuming no fillet and full fillet, i.e., fillet height equal to die thickness. Finally, two cases concerning the influence of die overhang, defined as the nominal distance between outermost solder joint and die edge, are investigated. Fracture parameters, including energy release rate (G) and phase angle (/spl psi/), are evaluated as a function of dimensions. Underfill material properties (elastic modulus and CTE), fillet configuration, and die overhang can be optimized to reduce the risk of underfill delamination in flip chip or direct chip attach (DCA) applications.     

Charge storage in double layers of thermally grown silicon dioxideand APCVD silicon nitride

Experimental results on charge storage and discharge in double layers of silicon dioxide and silicon nitride will be reported and discussed. SiO₂ with a thickness of 300 nm was thermally grown on silicon wafers, while cover layers of Si₃N₄ with thicknesses of 50, 100, and 150 nm were deposited chemically at atmospheric pressure. The samples were charged by the point-to-grid corona method. At room temperature, the measured surface potential V was stable during a period of almost three years. Isothermal measurements under different environmental conditions showed an improved charge retention compared to a single layer grown silicon dioxide. After ~3 h at 300°C, the observed voltage drop was <10% for the double layers and ~60% for bare SiO₂. Similar results were obtained under a humid condition of 95%RH and 60°C. Besides, thermally stimulated current (TSC) was measured in setup with a temperature ramp of 200°C/h. For the double layers, a current peak with a maximum temperature at ~500°C was observed. The measured current in the range of 300 to 400°C, the location of current maxima observed in thermally grown silicon dioxide or APCVD silicon nitride, was negligible. In addition to improved electret properties the internal stress in the investigated double layers can be adjusted by a proper thickness ratio of oxide layer to nitride layer. Therefore double layers of silicon dioxide and nitride seem to be promising materials for integrated sensors and actuators based on the electret effect     

Fundamental Limits of Organic Packages and Boards and the Need for Novel Ceramic Boards for Next Generation Electronic Packaging

The system-on-a-package (SOP) paradigm proposes a package level integration of digital, RF/analog and opto-electronic functions to address future convergent microsystems. Two major components of SOP fabrication are sequential build-up of multiple layers (4–8) of conducting copper patterns with interlayer dielectrics on a board and multiple ICs flip-chip bonded on the top layer. A wide range of passives, wave-guides and other RF and opto-electronic components buried within the dielectric layers provide the multiple functions on a single microminiaturized platform.The routing of future nanoscale ICs with 10,000+ I/Os require multiple build-up layers of ultra fine board feature sizes of 10 m lines/space widths and 40 m pad diameters. Current FR4 boards cannot achieve this build-up technology because of dimensional instability during processing. These boards also undergo high warpage during the sequential build-up process which limits the fine-line lithography and also causes misalignment between the vias and their corresponding landing pads. In addition, the CTE mismatch between the silicon die and the board leads to IC-package interconnect reliability concerns, particularly in future fine-pitch assemblies where underfilling becomes complicated and expensive.This work reports experimental and analytical work comparing the performance of organic and novel ceramic boards for SOP requirements. The property requirements as deduced from these results indicate that a high stiffness and tailorable CTE from 2–4 ppm/C is required to enable SOP microminiaturized board fabrication and assembly without underfill. A novel ceramic board technology is proposed to address these requirements.     

Fabrication of PZT Composite Thick Films for High Frequency Membrane Resonators

High frequency, thickness mode resonators were fabricated using a 7 m PZT thick film which was produced using a modified composite ceramic sol-gel process. Initial studies dealt with the integration of the PZT thick film onto the substrate. Two different diffusion barrier layers were tested, titanium oxide and zirconium oxide, in conjunction with the use of 2 types of silicon substrate (differing in the etch stop layer employed, either silicon nitride or silicon oxide). Zirconium oxide gave good results in conjunction with silicon oxide. Using these conditions, devices were produced and the acoustic properties measured for different electrode sizes ranging from 45*45 to 250*250 m². The best electrode size, which maximised the acoustic response and minimised the insertion loss, was found to have an area of 110*110 m². This device showed a resonant frequency of about 200 MHz, an effective electro-mechanical coupling coefficient of 0.29 and a Q factor of 22.     

Novel Low Voltage Piezoactuators for High Displacements

To improve the performance of piezoelectric actuators, new 3-D designs were developed to gain higher displacements or specific bending effects. Such 3-D actuators of e.g. helical structure have next to the standard actuator or sensor applications the potential to be used in Hi-Fi digital sound projectors. To lower the voltage of the power supply for these miniaturized devices, multilayer structures based on thin tapes must be used. Two processing routes to manufacture helical shaped multilayer PZT structures with specific electrode designs are tested. One route starts from tape cast PZT green tapes of 90 m or 50 m thickness, the other from extruded and stretched PZT filled thermoplastic films (Solufill) of 9 m thickness. The properties of these two films are compared. The sheets are screen printed and laminated similar to standard planar multilayer processing. To manufacture helical three-dimensional multi-layers from these laminates new processing techniques are required. The most important difference compared to planar multilayer processing is the necessity to bend the laminated structures. The bending behavior depends on the layer thickness, the number of layers, the diameter of the helix and the flexibility of the tape. In addition, specific measures have to be taken to ensure that the bent multilayer keeps its shape and keeps the alignment of the electrode design during binder burnout and sintering. Finally, working products of super-helical structure suitable for miniaturized loudspeaker application are built and tested.     

Effect of Thermal Treatment Temperature on the Crystallinity and Morphology of LiTaO3 Thin Films Prepared from Polymeric Precursor Method

Lithium tantalate thin films (LiTaO₃) with (50:50) stoichiometry were prepared by spin coating method using a polymeric organic solution. The films were deposited on silicon (100) substrates with 4 layers. The substrates were previously cleaned and then the solution of lithium tantalate was deposited by adjusting the speed at 5000 rpm. The thin films deposited were thermally treated from 350 to 600C for 3 hours in order to study the influence of the thermal treatment temperature on the crystallinity, microstructure, grain size and roughness of the final film. X-ray diffraction (XRD) results showed that the films are polycrystalline and secondary phases free. The thickness of films was observed by scanning electron microscopy (SEM). The atomic force microscopy (AFM) studies showed that the grain size and roughness are strongly influenced by thermal treatment.     

Board-Level ESD of Driver ICs on LCD Panel

In this paper, a method utilizing a charged-device model (CDM) test by the tape carrier package or chip-on-film (COF) samples to emulate the real-world board-level CDM or charged-board model (CBM) electrostatic discharge is proposed for large-sized chips such as liquid-crystal display (LCD) driver ICs, which successfully duplicated the same failure by CBM discharging. For small-sized chips, the evaluation board (or printed circuit board) emulation should minimize the parasitic $RLC$ loading of the interconnection on the board to achieve a more accurate CBM discharging. In addition, guidelines regarding chip-level design and layout optimization are proposed and have been successfully implemented to improve the immunity.      

Reliability Evaluation for Copper/Low-$k$ Structures Based on Experimental and Numerical Methods

Bump shear is widely used to characterize the interfacial strength of Cu/low- $k$ structures. In this paper, the blanket low-$k$ structure was used to evaluate the reliability and strength of Cu/low- $k$ structures based on experiment and finite-element modeling technique. The objectives of this paper are to determine the critical stress parameters for low-$k$ interfaces with different low-$k$ structures, to understand the failure mechanism, and to improve low-$k$ structure reliability by optimizing some parameters. In this paper, a comprehensive parametric study was carried out. Such parameters include the effect of three different low-$k$ structures, high-Pb solder bump versus Pb-free solder bump, different underbump metallization (UBM) thicknesses, barrier-layer material elastic modulus, and shear ram height on low-$k$ structure reliability. The simulation findings can be summarized as follows. The critical stress decreases with the number of layers of low-$k$ structure. An Sn–Ag solder bump results in a higher shear force and stress than a high-Pb solder bump. Reducing the UBM thickness can help improve the low- $k$ structure reliability.      

Zur Optimierung der Wickelkopfabsteifung von Hochspannungsmaschinen

Übersicht Die Kräfte auf die Spulenseiten im Wickelkopf werden mit Hilfe des Bio-Savartschen Gesetzes berechnet und in ihre tangentialen und radialen Komponenten zerlegt. Es zeigt sich, daß je nach Wicklungsauslegung (Sehnung, Strangverschachtelung) und Schalthandlung (dreipolig oder zweipolig) unterschiedlich große Beanspruchungen entstehen. Die Kraftverteilung ändert sich in axialer und in Umfangsrichtung, in der sie sich 2p-mal wiederholt. Aus den Maximalkräften wird eine fiktive worst case-Spule definiert, die den Absteifungsmaßnahmen zugrunde gelegt wird. Als Optimierungskriterium gilt, mit einer möglichst kleinen Zahl von Absteifungselementen Netzumschaltungen mit möglichst großen Luftdurchtrittsquerschnitt zu erreichen, ohne daß an irgendeiner Stelle die zulässige Biegebeanspruchung oder die zulässige Durchbiegung der Spulenschenkel überschritten werden. Das Optimierungsprogramm wird an Beispielmaschinen mit Spulen, die nach unterschiedlichen Fertigungstechnologien hergestellt sind, demonstriert.

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About the optimization of the end-winding support of h.v. machines

Contents The forces acting on the coil sides in the overhang are calculated by using the law of Biot-Savart and are splitted up into their tangential and radial components. It is shown that the stresses depend on the design features (chording, imbricating) of the winding and the switching operation (three-phase or two-phase). The force-density changes in circumferential direction with 2p repetitions and in axial direction. A worst-case coil is defined by butting the maximum force-densities side by side and the bracing is based on the stresses on this fictitious coil. The winding support is optimized, if the withstand-level in case of system transfer is maximum by using the minimum number of supporting elements (maximum rate of cooling-air flow) without exceeding the permissible figures of bending strain or bending stress at any point. The computer program is illustrated by examples of machines containing windings which are fabricated by different technologies (resin rich respectively vacuum impregnated).

     

Process modeling of stress and chemical effects in SiGe alloys using kinetic Monte Carlo

In state-of-the-art silicon based process technologies, strained and relaxed SiGe, strained-silicon layers, and process-induced stress are widely present. Based on a literature review, we developed and calibrated continuum and kinetic Monte Carlo process models for chemical and stress effects in SiGe (Zographos et al. in AIP Conf. Proc. 1496:212–216, 2012). In this paper, we explain in full detail the corresponding kinetic Monte Carlo models and calibration. The models take into account the effects on band gap, amorphization, recrystallization, point defect generation and diffusion, extended defect evolution, dopant diffusion and clustering, and dopant segregation. The influence of Ge concentration and strain profile on Si self-interstitials and vacancies properties are deducted from experimental data as well as from ab-initio studies. The {311} interstitial clusters are less stable in the presence of Ge or compressive hydrostatic pressure, and the transformation of {311} defects into dislocation loops is faster. The corresponding parameter adjustments have been calibrated based on experimental data generated within the ATOMICS research project. The effects of Ge and stress on dopant diffusion have been calibrated for boron, arsenic and phosphorus taking into account that in experiments using epitaxial layers of strained SiGe embedded in Si, or strained silicon embedded in relaxed SiGe, boron and phosphorus have been found to segregate at Si/SiGe interfaces.     

大功率压接型IGBT器件中的机械应力研究

机械应力是影响高压大功率压接型IGBT器件电气特性、热特性以及可靠性的关键因素之一。首先,从芯片与封装结构设计的角度,介绍单芯片以及多芯片并联机械压力分布均衡特性的研究现状及其关键设计技术。其次,从封装工艺的角度,分别对比弹性压接、刚性压接等不同焊接形式对芯片机械应力分布的影响规律。最后,结合压接封装结构特点,基于一种新型芯片终端结构,提出一种新型封装技术方案,可以有效提升单芯片以及并联芯片压力的均衡特性,为高压大容量压接型IGBT器件的设计提供参考依据。     

大功率压接型IGBT器件中的机械应力研究

机械应力是影响高压大功率压接型IGBT器件电气特性、热特性以及可靠性的关键因素之一。首先,从芯片与封装结构设计的角度,介绍单芯片以及多芯片并联机械压力分布均衡特性的研究现状及其关键设计技术。其次,从封装工艺的角度,分别对比弹性压接、刚性压接等不同焊接形式对芯片机械应力分布的影响规律。最后,结合压接封装结构特点,基于一种新型芯片终端结构,提出一种新型封装技术方案,可以有效提升单芯片以及并联芯片压力的均衡特性,为高压大容量压接型IGBT器件的设计提供参考依据。     

Electrooptical Modulating Device Based on a CMOS-Compatible -Si:H/ -SiCN Multistack Waveguide

In this paper, we report results on a field-effect-induced light modulation at $lambda$ $=$ 1.55 $mu$m in a high-index-contrast waveguide based on a multisilicon-on-insulator platform. The device is realized with the hydrogenated amorphous silicon ($alpha$ -Si:H) technology, and it is suitable for monolithic integration in a CMOS IC. The device exploits the free-carrier optical absorption electrically induced in the semiconductor core waveguide. The amorphous silicon waveguiding layer contains several thin dielectric films of amorphous silicon carbonitride ($alpha$ -SiCN) embedded along its thickness, thus highly enhancing the absorbing action of the modulator held in the on state.      

Reliability of La-Doped Hf-Based Dielectrics nMOSFETs

In this paper, the reliability of hafnium oxide gate dielectrics incorporating lanthanum (La) is investigated. The HfON with La demonstrated higher breakdown voltage and lower gate leakage than the control HfON with a similar equivalent oxide thickness and physical thickness. The superior breakdown characteristics of HfON that incorporate La are explained using La-induced interface-dipole formation. The La-induced dipole field at the interface between the $hbox{SiO}_{x}$ and high- $k$ hinders carrier injection in the inversion sweep, which in turn decreases gate leakage. In the accumulation region, the dipole formed near the interface regime appears to enhance the local field, which may lead to a local breakdown. While the devices with La show better immunity to positive-bias-temperature instability (PBTI) under normal operating conditions, the threshold-voltage shift $(Delta V_{rm th})$ at high field PBTI is significant. The results of a transconductance shift $(Delta G_{m})$ and flicker-noise analysis show that traps are easily generated during high field stress because the La weakens atomic bonding in the interface layer. These La-induced generated traps act like a capture/emission center, resulting in Lorentzian-like noise.      

Hybrid integration of smart pixels by using polyimide bonding:demonstration of a GaAs p-i-n photodiode/CMOS receiver

The fabrication procedure of smart pixels based on a hybrid integration of compound semiconductor photonic devices with silicon CMOS circuits is described. According to the 0.8-μm design rule, CMOS receiver/transmitter circuits are designed for use in vertical-cavity surface-emitting laser (VCSEL)-based smart pixels, and 16×16 and 2×2 Banyan-switch smart-pixel chips are also designed. By using our polyimide bonding technique, we integrated GaAs pin-photodiodes hybridly on the CMOS circuits. The photodetector (PD)/CMOS hybrid receiver operated error free at up to 800 Mb/s. Successful optical/optical (O/O) operation (a bit rate up to 311 Mbit/s) of the 2×2 Banyan-switch smart-pixel chip implemented with another VCSEL chip is also demonstrated     

Rapid die heating for low-stress die attach

During traditional isothermal die attach assembly, significant thermomechanical stress develops in the solder joints between the die and board. The coefficient of thermal expansion (CTE) of the silicon die and the woven composite circuit board materials are widely different. Under isothermal die attach, there is, hence, a mismatch between the thermal expansion displacements of the die and substrate, thereby leading to stress in the solder joints and die interconnect layers. One avenue to alleviate these stresses is to use alternate die attach processes that rely on localized heating of the die and solder joints so as to minimize the thermal expansion displacement mismatch. Die attach stress can be reduced significantly through rapid die heating (RDH), which results in the die being hotter than the board at the solder solidification point. Analytical modeling shows that RDH can reduce residual stress by up to 80% compared to traditional, isothermal die attach processing. Limited experimental results demonstrate 40% stress reduction to date. This paper will detail these results and physical analysis of the resulting solder joints.     

Influence of Nitrogen on Negative Bias Temperature Instability in Ultrathin SiON

Negative bias temperature instability (NBTI) and its recovery phenomenon in ultrathin silicon oxynitride (SiON₂) films were investigated. To discuss the influence of nitrogen incorporation into silicon dioxide films, we used NO-nitrided SiON and plasma-nitrided SiON. As a result, it was found that the recovery for plasma-nitrided SiON is less marked than that for NO-nitrided SiON, although NBTI can be suppressed by plasma nitridation. It is also experimentally confirmed that hydrogen plays an important role in these phenomena. On the basis of these results, we proposed nitrogen-originated NBT degradation involving hydrogen at SiON/Si interface and hole trapping/detrapping. Furthermore, NBTI under ac stress was investigated. Not only NBTI was more suppressed under ac stress than under dc stress as already reported, but also, this behavior of dynamic NBTI is independent of nitrogen distribution in SiON.     

压接式IEGT芯片布局对其温升的影响

压接式电子注入增强型门极晶体管PP-IEGT(press pack-injection enhanced gate transistor)封装内采用多芯片并联结构,芯片间的布局对器件温升与稳定性有着重要影响。在现有的对齐阵列布局下,芯片间严重的热耦合效应会导致器件结温较高,因此提出一种交错阵列的圆形布局。基于有限元热稳态仿真分析,对比了2种布局下的芯片温度分布,以及封装内各层组件的温度差异;同时,考虑不同功率损耗和外部散热条件的影响,对2种布局下各层组件温度变化进行了讨论。结果表明,提出的交错阵列布局可有效改善热耦合效应,芯片上的热量得到更好地耗散。此外,各芯片和器件整体的温度分布均匀性得到了提高,为更大电流参数PP-IEGT的芯片布局设计和稳定工作提供了参考。     

封装寄生参数对并联IGBT芯片瞬态电流分布的影响规律

大功率IGBT器件通过并联多个IGBT芯片来获得大电流等级,并联芯片动静态电流分布的一致性对于提高器件电流等级以及可靠性至关重要。首先介绍了大功率IGBT模块内部布局不一致导致的封装寄生参数差异性。其次,结合IGBT等效电路模型及其开关特性,分析了寄生参数差异性对于并联IGBT芯片瞬态电流分布特性的影响规律。最后,建立了并联IGBT芯片的等效电路模型,并应用Synopsys Saber软件建立了仿真电路,从封装寄生电感参数差异性、封装寄生电阻参数差异性,分析了参数差异对并联芯片的瞬态电流分布特性的影响。     

Development of silicon wafer packaging technology for deep UV LED

This paper reports a deep‐ultraviolet LED (deep‐UV‐LED) package based on silicon MEMS process technology (Si‐PKG). The package consists of a cavity formed by silicon crystalline anisotropic etching, through‐silicon vias (TSVs) filled with electroplated Cu, bonding metals made of electroplated Ni/AuSn and a quartz lid for hermetic sealing. A deep‐UV LED die is directly mounted in the Si‐PKG by AuSn eutectic bonding without a submount. It has advantages in terms of size, heat dissipation, light utilization efficiency, productivity and cost over conventional AlN ceramic packages. We confirmed a light output of 30 mW and effective reflection on Si (111) cavity slopes in the Si‐PKG. Based on simulation, further improvement of the optical output is expected by optimizing DUV‐LED die mount condition.