A Non-Feedback Δ-Σ Modulator for Digital-to-Analog Conversion Using Digital Frequency Modulation

This paper describes a novel noise-shaping Δ-Σ modulator for D/A-conversion which has no global feedback. The proposed topology is well suited for a pipelined clocking scheme allowing increased oversampling ratios for both first and higher order modulators. The maximum clock-frequency of the new modulator is limited only by the delay through one single accumulator regardless of modulator order, which represents a huge saving compared to the conventional modulator. The converter is very modular and scales easily to higher modulator orders. Still the proposed topology is mathematically equivalent to the classical Δ-Σ modulator. Theoretical analysis and circuit simulations for a first- and second-order modulator are presented. The first-order circuit has been implemented in a FPGA-circuit from Altera and measured results are presented.     

Designs of multi-bit sigma delta modulator

This paper presents new design variants of third order multi-bit sigma delta modulator (SDM): low distortion SDM and cascaded SDM. The proposed modulator based on the conventional SDMsuch L-0MASH(Multi-stAge noise SHaping) and interstage feedback topology. TheMASHSDM is not a single loop system. One of the drawback is that performance is limited by uncancelled noise from the first modulator and interstage feedback topology only cancels nonlinear errors introducing by multi-bitDACin the final stage, but the rest stage still containsDACnonlinearity errors without any noise shaping which still degrade overall system performance. An improved version of cascaded multi-bit SDM is proposed to overcome these problems mentioned above. In addition a third order low distortion SDM is also proposed. Simulation results verify the superiority of the both proposed modulator.     

A 1.1 mW 87 dB dynamic range ΔΣ modulator for audio applications

This paper presents a 1.1 mW 87 dB dynamic range third order AS modulator implemented in 0.18 μm CMOS technology for audio applications.By adopting a feed-forward multi-bit topology,the signal swing at the output of the first integrator can be suppressed.A simple current mirror single stage OTA with 34 dB DC gain working under 1 V power supply is used in the first integrator.The prototype modulator achieves 87 dB DR and 83.8 dB peak SNDR across the bandwidth from 100 Hz to 24 kHz with 3 kHz input signal.     

一种用于音频系统的1.1mW 87dB动态范围的ΔΣ调制器

本文描述了一款应用于音频系统的1.1mW 87dB动态范围的 Delta-Sigma 调制器的设计,设计采用0.18um CMOS工艺。由于采用带有前馈支路的多比特结构,第一级积分器的输出摆幅得到有效压缩。第一级积分器采用结构简单,直流增益仅34dB,工作在1V电压下的电流镜型跨导放大器。在3KHz信号输入下,该调制器可在100Hz~24KHz的频率范围内达到83.8dB的峰值SNDR和87dB的动态范围。     

A symbolic approach toward high-level variation-aware topology synthesis of Delta-Sigma modulators

This article presents a methodology for automated high-level variation-aware topology synthesis of ΔΣ (Delta-Sigma) modulators. The methodology targets an optimal high-level ΔΣ modulator topology in terms of statistical signal-to-noise ratio (SNR) variation. In the proposed methodology, a systematic symbolic formulation of statistical SNR variation is made so that variations of capacitors are directly translated to SNR variation. The symbolic formulation of statistical SNR variation is then taken as the cost function guiding the topology synthesis process. A ΔΣ modulator template topology, which compactly represents all possible modulator topologies, is used so that the solution space is complete. To facilitate the search for an optimal topology, a mixed-integer non-linearly constrained programming (MINLP) program is formulated. By solving the MINLP program, an optimal solution with least statistical SNR variation can be obtained. A few experiments have shown the solved optimal topologies have less SNR variations compared to traditional ones.     

Double-sampled ΔΣ modulator with relaxed feedback timing

A double-sampled delta-sigma (ΔΣ) modulator topology is proposed that can relax the critical timing constraints in the modulator feedback path. The speed requirements of the quantiser and dynamic element matching logic are thus greatly reduced. To verify the effectiveness of the proposed topology, a second-order double-sampled DS modulator is designed and simulated.     

一种改进的无感型MARX调制器

在窄脉宽、电压不是太高的情况下,无感型MARX调制器因其结构紧凑、性能可靠、成本低廉倍受人们青睐。然而对典型的无感MARX调制器来说,轻载情况下脉冲输出后沿特性并不理想。文中对这种典型电路进行改进,优化了放电回路,使脉冲输出包络不再受负载不同的影响,得到更好的脉冲输出波形。此外,改进后的调制器电路也得到了一定简化。     

Reconfigurable hybrid CT/DT delta-sigma modulator with op-amp sharing technique dedicated to multi mode receivers

A novel multi mode low pass hybrid continuous/discrete time delta sigma modulator which is suitable for low power wide band applications is presented in this article. The proposed topology can adapt itself for operating in various signal bandwidths as well as different signal to noise plus distortion ratios (SNDRs). The novelty of the proposed modulator lies in the fact that several techniques have been employed simultaneously that not only can reduce the power consumption, but also it can increase the performance of the modulator. Continuous time integrator is utilized to alleviate the specs for the first stage op-amp. The modulator employs an op-amp sharing technique, which decreases the power consumption dramatically due to elimination of the power hungry adder before the quantizer in the feed forward topology. Another attractive advantage of the proposed modulator is using the noise-shaping enhancement technique which can increase the performance of the modulator without using analog active blocks. The unused block of the modulator can be made inactive to achieve less power dissipation. Behavioral simulations in MATLAB environment show the SNDR of 91/86/73 dB over 0.2/2/20 MHz signal bandwidth.     

1–0–1 Cascaded Sigma–Delta Modulator with Internal Feedback

The conventional sigma–delta modulators, such as L-0 MASH and inter-stage feedback topology, have some main drawbacks, e.g. L-0 MASH can only be applied in single loop topology and dynamic range is its big problem, and inter-stage feedback topology only cancels nonlinear errors introducing by multi-bit DAC in the final stage, but the rest stages still contain DAC nonlinearity errors without any noise shaping which still degrade overall system performance. In this letter, an improved version of cascaded multi-bit sigma–delta modulator is proposed to overcome these problems mentioned above. Simulation results will verify the superiority of the proposed modulator.     

160mW大功率固态调制器的设计与实验

为提高脉冲调制器的可靠性,设计了基于大功率绝缘栅双极性晶体管模块为开关的大功率固态调制器系统.调制器采用加法器结构,设计输出脉冲功率160 mW,脉冲电压80 kV,脉冲电流2kA.详细介绍了大功率调制器的电路拓扑和系统参数,重点阐述了大功率调制器的组件电路.介绍了绝缘栅双极性晶体管的驱动电路,给出了组件的输出波形,进...     

A 5-GHz frequency-doubling quadrature modulator with a ring-typelocal oscillator

The direct-conversion quadrature modulator described here was developed by using a frequency-doubling circuit technique so that the modulator and the local oscillator can be integrated on a single silicon chip. The local oscillation frequency in the modulator can be reduced to half the carrier frequency, and this enables the integration on a single chip. A three-level mixer with a newly designed symmetrical topology for two local oscillator inputs is used for the frequency doubling, so the image component levels of the modulated signals are low. When the modulator was implemented on a single chip by using Si-bipolar process technology with a cutoff frequency of 40 GHz, the image ratio at a carrier frequency of 5 GHz was less than -34 dBc     

A self-balancing space vector switching modulator for three-level motor drives

This paper describes how to formulate a self-balancing space vector modulator for the three-level neutral point clamp topology typically used for high power induction motor drives. Besides space vector modulation principle is used to calculate pattern times within one control update cycle, several other techniques are proposed in order to obtain a production quality modulator. These include a pivot point concept to be used for pattern selections in order to achieve minimum switching losses, techniques for neutral point voltage balancing, power device minimum on/off time guarantee, adjacent state switching, and sine triangular equivalent etc. Lab test results are given for effectiveness of the modulator.     

5.2 mW 61 dB SNDR 15 MHz Bandwidth CT ΔΣ Modulator Using Single Operational Amplifier and Single Feedback DAC

We propose an architecture that reduces the power consumption and active area of such a modulator through a reduction in the number of active components and a simplification of the topology. The proposed architecture reduces the power consumption and active area by reducing the number of active components and simplifying the modulator topology. A novel second‐order loop filter that uses a single operational amplifier resonator reduces the number of active elements and enhances the controllability of the transfer function. A trapezoidal‐shape half‐delayed return‐to‐zero feedback DAC eliminates the loop‐delay compensation circuitry and improves pulse‐delay sensitivity. These simple features of the modulator allow higher frequency operation and more design flexibility. Implemented in a 130 nm CMOS technology, the prototype modulator occupies an active area of 0.098 mm² and consumes 5.23 mW power from a 1.2 V supply. It achieves a dynamic range of 62 dB and a peak SNDR of 60.95 dB over a 15 MHz signal bandwidth with a sampling frequency of 780 MHz. The figure‐of‐merit of the modulator is 191 fJ/conversion‐step.     

An automated high-level topology generation procedure for continuous-time ΣΔ modulator

This paper presents an automated procedure for generation of high-level topologies for continuous-time ΣΔ modulator system. A functional topology of the system is generated from the given transfer function model of the modulator. Mathematical transformation technique is applied iteratively over the initial topology to generate a functional topology which is optimized for modulator sensitivity, hardware complexity and relative power consumption. This is then implemented using behavioral models of operational transconductance amplifiers and capacitors. The generated high-level topology is ensured to work with reasonable accuracy under non-ideal conditions. The entire procedure has been implemented in Matlab/Simulink environment. Numerical results have been provided to demonstrate the procedure.     

A 12-bit 3.125 MHz Bandwidth 0–3 MASH Delta-Sigma Modulator

We demonstrate a 12-bit 0–3 MASH delta-sigma modulator with a 3.125 MHz bandwidth in a 0.18 $muhbox{m}$ CMOS technology. The modulator has an oversampling ratio of 8 (clock frequency of 50 MHz) and achieves a peak SNDR of 73.9 dB (77.2 $~$dB peak SNR) and consumes 24 mW from a 1.8 V supply. For comparison purposes, the modulator can be re-configured as a single-loop topology where a peak SNDR of 64.5 dB (66.3 dB peak SNR) is obtained with 22 mW power consumption. The energy required per conversion step for the 0–3 MASH architecture (0.95 pJ/step) is less than half of that required by the feedback topology (2.57 pJ/step).      

小型化高压固态脉冲调制器

针对高峰值功率发射机调制器的技术要求,介绍了常用的线型调制器和固态刚管调制器电路拓扑,讨论了不同调制器的特点和适用场合。介绍了小型化高压固态脉冲调制器的电路拓扑,分析了影响调制器性能的主要因素。该调制器基于单个大功率绝缘栅双极型晶体管模块和初级采用多组导线并联绕制的脉冲变压器,并采用能量回馈电路来箝位脉冲变压器的反峰电压。文中给出了调制器的输出脉冲波形,并指出了该调制器的适用场合。     

A Multi-Mode Sigma-Delta ADC for GSM/WCDMA/WLAN Applications

The demand for new telecommunication services requiring higher capacities, data rates and different operating modes have motivated the development of new generation multi-standard wireless transceivers. In multi-standard design, sigma-delta based ADC is one of the most popular choices. To this end, in this paper we present cascaded 2-2-2 reconfigurable sigma-delta modulator that can handle GSM, WCDMA and WLAN standards. The modulator makes use of a low-distortion swing suppression topology which is highly suitable for wide band applications. In GSM mode, only the first stage (2nd order ∑-Δ ADC) is used to achieve a peak SNDR of 88dB with over-sampling ratio of 160 for a bandwidth of 200KHz and for WCDMA mode a 2-2 cascaded structure (4th order) is turned on with 1-bit in the first stage and 2-bit in the second stage to achieve 74 dB peak SNDR with over-sampling ratio of 16 for a bandwidth of 2MHz. Finally, a 2-2-2 cascaded MASH architecture with 4-bit in the last stage is proposed to achieve a peak SNDR of 58dB for WLAN for a bandwidth of 20MHz. The novelty lies in the fact that unused blocks of second and third stages can be made inactive to achieve low power consumption. The modulator is designed in TSMC 0.18um CMOS technology and operates at 1.8 supply voltage.     

Vector modulator for W-band software radar techniques

Direct-carrier modulation is an attractive technique for low-cost high-performance radar transceivers. In this paper, it is shown that, when the technique is applied to a generic homodyne radar architecture, the signaling waveform can be software adapted without requiring any hardware modifications. The key circuit in this novel software radar is a W-band monolithic I-Q vector modulator employing two push-pull (bi-phase) amplitude modulators. To fully exploit this circuit's capacity to generate accurate constellations at millimeter-wave frequencies, a generalized theoretical analysis of the I-Q (push-pull) vector modulator is presented. This is a comprehensive analysis of the topology and does not assume ideal components. As a demonstration of the vector modulator's flexibility, a 76.5-GHz MMIC version has been fabricated and characterized by means of static S-parameter measurements and by several modulation spectra. Based on the theoretical model and the measured results, the I-Q (push-pull) vector modulator promises to be a vital component for the realization of future software radar     

Symbolic Statistical Analysis of SNR Variation for Delta–Sigma Modulators

Traditional methods for statistical analysis of delta-sigma modulators are based on Monte Carlo analysis to iteratively change the design parameters and evaluate the histogram of signal-to-noise ratio (SNR). But Monte Carlo analysis is time-consuming, especially when a number of candidate designs need to be considered. In this brief, a systematic symbolic formulation of statistical SNR variation is made so that variations of capacitors are directly translated to SNR variation. In addition, the symbolic formulation is derived from a generic modulator topology, so that the derived symbolic formulation is applicable to any topology that is covered by the generic topology. Experiments have shown the symbolic formulation can provide fast and reasonably accurate estimation of statistical SNR variation, especially for high-order modulators.     

Single-switch two-output flyback-forward converter operation

A double power converter with fully independent regulated outputs is introduced. The proposed topology results from magnetic integration of flyback and forward power converters. The derived converter shares a single power switch having a single magnetic component. Also, only one standard pulsewidth modulation (PWM) integrated modulator is needed in order to keep independent closed-loop control of both output voltages. The double regulation may be sustained over a wide spread of current loads. Boundaries of full regulation and experimental results are presented