An accurate and analytic threshold-voltage model for small-geometry MOSFETs with single-channel ion implantation in VLSI

This paper presents an accurate and analytic threshold-voltage model for n-channel enhancement MOSFETs with single-channel boron implantation. In the developed model, the step-profile approximation is used to simulate the channel-implanted profile and an accurate inversion condition is used to calculate the surface potential. Moreover, the built-in voltage across the step junction is taken into consideration, which insures the continuities of surface potential and maximum depletion width changes with respect to the applied substrate bias as the edge of maximum depletion width passes through the step junction. A modified charge-sharing model is also developed to consider the charge-sharing effect due to source and drain diffusion islands and is incorporated into the developed threshold-voltage model by the depletion-charge-superposition method. In addition, the charge-sharing effect due to the bird's beak and field-encroachment implant has also been considered in the developed model. The experimental devices fabricated by a set of test keys have been characterized. The measured threshold voltages are compared to the developed model and excellent agreement between comparisons has been obtained for wide ranges of channel lengths, channel widths, and applied substrate biases. Moreover, a method of extracting the implant parameters for a step profile and the flatband voltage is also presented.     

A method to predict harmonic distortion in small-geometry MOS analog integrated circuits

A method to predict the small-signal linear gain and level of harmonic distortion in analog MOS circuits is presented. This method, based on a generalized nonlinear transfer function approach, lends itself to implementation in the AC small-signal analysis routine of the circuit simulation program SPICE. A low-frequency nonlinear distortion model based on the CSIM simulator MOSFET model is applied to three simple MOSFET circuits. Results presented emphasize the need to consider small-signal quantities in the development of MOSFET models and in the determination of device parameters. The method can be easily extended to include capacitive effects and a prediction of intermodulation distortion.     

Selective ion implantation to reduce power consumption in MOS integrated circuits

A method of using implantation to reducek'in selected MOS transistors on an LSI chip is described. An application of this technique is described where the power consumed in circuits such as memory cells is reduced without impairing other operating parameters.     

Design methodologies for high-performance noise-tolerant XOR-XNOR circuits

Scaling down to deep submicrometer (DSM) technology has made noise a metric of equal importance as compared to power, speed, and area. Smaller feature size, lower supply voltage, and higher frequency are some of the characteristics for DSM circuits that make them more vulnerable to noise. New designs and circuit techniques are required in order to achieve robustness in presence of noise. Novel methodologies for designing energy-efficient noise-tolerant exclusive-OR-exclusive- NOR circuits that can operate at low-supply voltages with good signal integrity and driving capability are proposed. The circuits designed, after applying the proposed methodologies, are characterized and compared with previously published circuits for reliability, speed and energy efficiency. To test the driving capability of the proposed circuits, they are embedded in an existing 5-2 compressor design. The average noise threshold energy (ANTE) is used for quantifying the noise immunity of the proposed circuits. Simulation results show that, compared with the best available circuit in literature, the proposed circuits exhibit better noise-immunity, lower power-delay product (PDP) and good driving capability. All of the proposed circuits prove to be faster and successfully work at all ranges of supply voltage starting from 3.3 V down to 0.6 V. The savings in the PDP range from 94% to 21% for the given supply voltage range respectively and the average improvement in the ANTE is 2.67X.     

Proton implantation isolation for microwave monolithic circuits

We show that proton implantation isolation effectively reduces RF losses for microwave monolithic integrated circuits and that the degree of effectiveness is a function of the induced damage depth. RF losses are mostly due to the current conduction in semiconducting active or buffer layer.     

Ion implantation for threshold control in COSMOS circuits

The use of ion implantation for close threshold control of N-MOS and P-MOS transistors has been studied from an experimental and theoretical viewpoint. Experimental determinations of ion-implanted diffusion profiles, sheet resistivities, and threshold voltages for boron, phosphorus, and arsenic implantations are reported for doses in the range from 1 × 10¹¹to 1 × 10¹⁴ions/cm². Care has been taken to ensure accuracy of implanted dose in the 35-150 keV range in order to permit direct comparison of experiments with theory. Satisfactory agreement is observed between experiment and computer predictions using only the implantation dose and energy. The analytical model tested assumed outdiffusion in a neutral ambient from an implanted Gaussian layer. Experimental tests of the calculation are made for thresholds, sheet-resistance profiles, and amounts of dopant lost to the oxide masking layer. The theoretical model has been used as a basis for threshold control. The application of these principles is related to the practical fabrication of COSMOS circuits with close threshold control through suitable selection of starting substrate material and implantation conditions.     

A high-performance lateral geometry transistor for complementary integrated circuits

The lateral geometry transistor has shown itself to be highly useful in the realization of low-frequency integrated circuits. This simple structure has been limited essentially to dc applications, however, by bandwidth and switching time performance. The p-n-p device to be described in this paper substantially overcomes these deficiencies by the addition of an n+ diffusion directly beneath the emitter region. As a result of the steeper gradient at the bulk, or planar, portion of the emitter-base junction, injection occurs primarily near the surface. It is possible to control the dimensions of the buried layer such that injection of carriers greater than a few micrometers from the collector will be minimized. A further consequence of the n+ region is the introduction of a graded base such that minority carrier transport is enhanced. The improved transistor structure has demonstrated the feasibility of obtaining an f_{T} of 10 MHz to 20 MHz at collector currents of 100 µA and rise, fall, and storage times in the tens of nanoseconds.     

Vertically integrated SOI circuits for low-power and high-performance applications

Vertical integration offers numerous advantages over conventional structures. By stacking multiple-material layers to form double gate transistors and by stacking multiple device layers to form multidevice-layer integration, vertical integration can emerge as the technology of choice for low-power and high-performance integration. In this paper, we demonstrate that the vertical integration can achieve better circuit performance and power dissipation due to improved device characteristics and reduced interconnect complexity and delay. The structures of vertically integrated double gate (DG) silicon-on-insulator (SOI) devices and circuits, and corresponding multidevice-layer (3-D) SOI circuits are presented; a general double-gate SOI model is provided for the study of symmetric and asymmetric SOI CMOS circuits; circuit speed, power dissipation of double-gate dynamic threshold (DGDT) SOI circuits are investigated and compared to single gate (SG) SOI circuits; potential 3-D SOI circuits are laid out. Chip area, layout complexity, process cost, and impact on circuit performance are studied. Results show that DGDT SOI CMOS circuits provide the best power-delay product, which makes them very attractive for low-voltage low-power applications. Multidevice-layer integration achieves performance improvement by shortening the interconnects. Results indicate that up to 40% of interconnect performance improvements can be expected for a 4-device-layer integration.     

Mixed Full Adder topologies for high-performance low-power arithmetic circuits

This paper deals with the implementation of Full Adder chains by mixing different CMOS Full Adder topologies. The approach is based on cascading fast Transmission-Gate Full Adders interrupted by static gates having driving capability, such as inverters or Mirror Full Adders, thus exploiting the intrinsic low power consumption of such topologies. The obtained mixed-topology circuits are optimized in terms of delay by resorting to simple analytical models.Delay, power consumption and the Power-Delay Product (PDP) in both mixed-topology and traditional Full Adder chains were evaluated through post-layout Spectre simulations with a 0.35 μm, 0.18 μm and 90 nm CMOS technology considering different design targets, i.e., minimum power consumption, PDP, Energy-Delay Product (EDP) and delay. The results obtained show that the mixed-topology approach based on Mirror adders are capable of a very low power consumption (comparable to that of the low-power Transmission-Gate Full Adder) and a very high speed (comparable with or even greater than that of the very fast Dual-Rail Domino Full Adder). This also enables a high degree of design freedom, given that the same (mixed) topology can be used for a wide range of applications. This greater flexibility also affords a significant reduction in the design effort.     

Ion implantation of GaAs integrated circuits

The conditions required for the fabrication of low pinch-off voltage MESFETs by ion implantation have been established. Calculation of the device characteristics from measured carrier concentration profiles has shown that of Vp of -1.5V is best achieved using low implant energies together with ion doses of 2 × 10¹² cm^?2. Characterisation of the implant and annealing conditions has enabled the implanted dose to be corrected for the activation after annealing. Measurement of the processed devices has shown the variation in saturation current to be as low as 3 mA over 75% of the wafer area, showing suitability for use in logic circuit fabrication.     

A new threshold-voltage model for small-geometry buried-channel MOSFETs

This paper presents an analytic model for the threshold voltage of small-geometry buried-channel MOSFETs, in which the implanted buried-channel profile is approximated by a step profile. Based on the energy-band diagram, the threshold voltage of a buried-channel MOSFET is derived, in which the flatband voltage is physically defined. Using a new charge-sharing scheme, the threshold-voltage model considering the short-channel effect is calculated analytically. Similarly, based on the charge-sharing scheme, the narrow-width effect considering the field implant encroachment under the bird's beak is calculated. Combining both short-channel and narrow-width effects, the threshold-voltage model for small-geometry buried-channel MOSFETs is developed. In order to test the validity of the model, the buried-channel MOSFETs were fabricated in a production line and the threshold voltages were measured. Comparisons between the measured threshold voltage and the present model have been made. It is shown that satisfactory agreement has been obtained for wide ranges of channel lengths, channel widths and applied back-gate biases.     

Lithographyless ion implantation technology for agile fab

A new type of ion implanter developed for an agile fab can eliminate the processes concerned. with photoresist lithography from the ion implantation process. This new ion implantation technology can reduce the raw process time, footprint, and the cost of ownership to less than one-half that of conventional ion implantation technology. The authors are making further developments on this ion implanter and evaluating technical issues related to ion implantation. This technique is suitable for manufacturing submicron node IC devices. Based on the results of evaluating the prototype machine, we will produce the next /spl beta/-machine.     

离子注入均匀性的工艺控制

叙述了影响离子注入均匀性的几个主要因素,其中包括束流品质,离子束聚焦与扫描以及束流大小选择等。同时介绍了如何控制这些因素来获取优异的注入均匀性,通过这些控制手段,均匀性可以优于１ ％ ,结果令人满意。     

Stencil mask ion implantation technology

The ion implantation process is important for the development or manufacturing of semiconductor devices, because ion implantation conditions directly influence some characteristics of semiconductor devices. Recently, we developed a new implantation technology, stencil mask ion implantation technology (SMIT). In the SMIT system, the stencil mask acts like a resist mask, and ions passing through the mask holes are implanted into selected regions of the Si substrate chip by chip. Use of SMIT has several advantages, notably lower manufacturing cost and shorter process time than in the case of conventional processing, because no photolithography process (including deposition and stripping of resist) is required. We have already demonstrated an application of SMIT to transistor fabrication, using various implanted dose conditions for the same wafer. Threshold voltage values can be controlled as effectively by implanted doses as they can by conventional implantation, and the dose dependence of the threshold voltage could be obtained from one wafer to which various implantation conditions are applied. Using SMIT, implantation conditions can be changed chip by chip without additional processes. This flexibility of implantation conditions is another advantage of SMIT. In this paper, we propose stencil mask ion implantation technology and show some fundamental results obtained by applying SMIT     

Modeling ion implantation of HgCdTe

Ion implantation of boron is used to create n on p photodiodes in vacancy-doped mercury cadmium telluride (MC.T). The junction is formed by Hg interstitials from the implant damage region diffusing into the MC.T and annihilating Hg vacancies. The resultant doping profile is n⁺/n^-/p, where the n⁺ region is near the surface and roughly coincides with the implant damage, the n^- region is where Hg vacancies have been annihilated revealing a residual grown-in donor, and the p region remains doped by Hg vacancy double acceptors. We have recently developed a new process modeling tool for simulating junction formation in MC.T by ion implantation. The interstitial source in the damage region is represented by stored interstitials whose distribution depends on the implant dose. These interstitials are released into the bulk at a constant, user defined rate. Once released, they diffuse away from the damage region and annihilate any Hg vacancies they encounter. In this paper, we present results of simulations using this tool and show how it can be used to quantitatively analyze the effects of variations in processing conditions, including implant dose, annealing temperature, and doping background.     

Multiple Sb ion implantation for deep-submicron pMOS channel doping

We propose a channel doping technology for pMOSFET's in which Sb is multiply ion implanted to produce a uniform doping profile in the region deeper than the minimum projected range of the multiple ion implantation. We derive a threshold voltage model and show how to realize this uniform doping profile, which is verified with experimental data. We study the short-channel effect of this device using a two-dimensional (2-D) device simulator, and show that this transistor can readily operate with a gate length of down to 0.1 μm     

Characterization of horizontal Bridgman-grown semi-insulating GaAs for ion implantation

Thermal stability of horizontal Bridgman-grown (HB) Cr-doped seme-insulating GaAs is characterized systematically by leakage current measurement. Electrical characteristics for a Si-ion implanted n-layers on GaAs were evaluated by Hall and C-V measurements. The threshold voltage uniformity for MESFETs fabricated on implanted n-layer was also discussed. Not only the leakage current of annealed wafers but also the electrical properties of the ion implanted n-layers have a close correlation with the Cr concentration in the bulk GaAs. The uniformity of the ion implanted n-layer was degraded by the Cr concentration variations in the wafer. In addition to uniformity, mobility data, which show lower values for HB crystals than for undoped LEC crystal, imply the importance of high purity GaAs semi-insulating LEC crystal.     

Optimization of short-flow MOS charging monitor for ion implantation

Application of MOS capacitors for charging assessment is a widely accepted approach used by both process engineers and tool manufacturers. This paper presents results of optimizing short-flow on-wafer MOS capacitors with charge-collecting antennas to monitor charging caused by ion beams. The main factors considered during the optimization process include simplicity, testability, and sensitivity. Short-flow manufacturing of monitor wafers was developed to support the fast feedback "stick-and-test" approach.