Feedback nonlinear discrete-time systems

In this paper, we design an adaptive iterative learning control method for a class of high-order nonlinear output feedback discrete-time systems with random initial conditions and iteration-varying desired trajectories. An n-step ahead predictor approach is employed to estimate future outputs. The discrete Nussbaum gain method is incorporated into the control design to deal with unknown control directions. The proposed control algorithm ensures that the tracking error converges to zero asymptotically along the iterative learning axis except for the beginning outputs affected by random initial conditions. A numerical simulation is carried out to demonstrate the efficacy of the presented control laws.     

Transducer generated arrays of robotic nano-arms

We consider sets of two-dimensional arrays, called here transducer generated languages, obtained by iterative applications of transducers (finite state automata with output). Each transducer generates a set of blocks of symbols such that the bottom row of a block is an input string accepted by the transducer and, by iterative application of the transducer, each row of the block is an output of the transducer on the preceding row. We show how these arrays can be implemented through molecular assembly of triple crossover DNA molecules. Such assembly could serve as a scaffold for arranging molecular robotic arms capable of simultaneous movements. We observe that transducer generated languages define a class of languages which is a proper subclass of recognizable picture languages, but it contains the class of all factorial local two-dimensional languages. By taking the average growth rate of the number of blocks in the language as a measure of its complexity, we further observe that arrays with high complexity patterns can be generated in this way.     

Testability of software components

The concept of domain testability of software is defined by applying the concepts of observability and controllability to software. It is shown that a domain-testable program does not exhibit any input-output inconsistencies and supports small test sets in which test outputs are easily understood. Metrics that can be used to assess the level of effort required in order to modify a program so that it is domain-testable are discussed. Assessing testability from program specifications and an experiment which shows that it takes less time to build and test a program developed from a domain-testable specification than a similar program developed from a nondomain-testable specification are also discussed     

Simulink fault localization: an iterative statistical debugging approach

Debugging Simulink models presents a significant challenge in the embedded industry. This paper proposes SimFL, a fault localization approach for Simulink models by combining statistical debugging and dynamic model slicing. Simulink models, being visual and hierarchical, have multiple outputs at different hierarchy levels. Given a set of outputs to observe for localizing faults, we generate test execution slices, for each test case and output, of the Simulink model. In order to further improve fault localization accuracy, we propose iSimFL, an iterative fault localization algorithm. At each iteration, iSimFL increases the set of observable outputs by including outputs at lower hierarchy levels, thus increasing the test oracle cost but offsetting it with significantly more precise fault localization. We utilize a heuristic stopping criterion to avoid unnecessary test oracle extension. We evaluate our work on three industrial Simulink models from Delphi Automotive. Our results show that, on average, SimFL ranks faulty blocks in the top 8.9% in the list of suspicious blocks. Further, we show that iSimFL significantly improves this percentage down to 4.4% by requiring engineers to observe only an average of five additional outputs at lower hierarchy levels on top of high‐level model outputs. Copyright © 2016 John Wiley & Sons, Ltd.     

Optimal tradeoffs for addition on systolic arrays

The complexity of adding twon-bit numbers on a two-dimensional systolic array is investigated. We consider different constraints on the systolic array, including:

whether or not the input and output ports lie on the periphery of the array,

constraints placed on the arrival and departure times of inputs and outputs

. For all combinations of the above constraints, we obtain optimal tradeoffs among the resources of area, pipeline delay, and worst-case time. It turns out that there is a subtle interplay among the constraints and some of our results seem counterintuitive. For instance, we show that allowing more-significant bits to arrive earlier than less-significant bits can speed up addition by a factor of logn. We also show that multiplexing can often result in a smaller array. On the other hand, we show that some known results, such as Chazelle and Monier's bounds for arrays that have input/output ports on the perimeter, also hold in less constrained models.     

基于最小冗余线阵的二维DOA估计方法

针对传感器阵列二维DOA估计中阵元数较多且阵元利用率较低的问题,提出了一种低阵元冗余的二维DOA估计方法.该方法通过在最小冗余线阵基础上添加两个导向阵元的方法,将最小冗余线阵的应用拓展到二维DOA估计.同时该方法利用多个时延的阵元输出共轭循环相关函数构造"伪数据阵",在时空域中等效出两个具有旋转不变性的平行子阵,进而运用DOA矩阵法估计信号二维DOA.该方法不仅避免了最优时延选择问题,继承了DOA矩阵法无需谱峰搜索且无需二维角度参数配对等优点.还用较少的阵元获得了较大的阵列有效孔径.仿真结果表明,该方法与CCDM算法相比具有更好的低信噪比适应能力和稳健性.     

数字微流控生物芯片测试诊断过程分析和优化

针对数字微流控生物芯片的测试和诊断过程进行建模和分析,并根据并行测试的分块数和单元出错概率为相应的测试和诊断成本建立函数。通过Matlab对测试诊断成本函数的分析表明：随着并行测试分块数的增大,测试诊断成本的变化趋势不明显,也就是说,并行测试的分块数对测试诊断成本的影响不大;而随着单元出错概率p的增加,测试成本呈明显的增加趋势,且增加的幅度较大。另外,诊断过程中,根据单元出错概率对出错的子阵列再进行诊断,诊断过程必须持续若干次,直到所有故障定位后才能结束。在这些诊断中,针对最后一次定位的诊断成本是最大的,而且与其他次的诊断过程的成本相差几十个数量级,决定了总成本的大小。这些结论为数字微流控生物芯片的测试和诊断过程优化提供重要的理论依据,并为测试诊断方法的设计提供指导。     

Performance-optimized applied identification of separabledistributed-parameter processes

Studies practical algorithms for parametric identification of cross-directional processes from input/output data. Instead of working directly with the original two-dimensional array of the high-resolution profile scans, the proposed algorithms use separation properties of the problem. It is demonstrated that by estimating and identifying in turn cross directional and time responses of the process, it is possible to obtain unbiased least-square error estimates of the model parameters. At each step, a single data sequence is used for identification which ensures high computational performance of the proposed algorithm. A theoretical proof of algorithm convergence is presented. The discussed algorithms are implemented in an industrial identification tool and the note includes a real-life example using paper machine data     

Testable design of two-dimensional cellular logic arrays for detecting stuck-at and bridging faults

In this paper the problem of detecting bridging faults in two-dimensional (2-D) cellular logic arrays realizing an arbitrary Boolean function is considered in a new framework. A testable design of such combinational logic arrays has been proposed in which a set of universal tests can be initiated to detect all single stuck-at and bridging faults. The augmentation of the network for inducing testability is simple and is also independent of the function realized.     

十字形二维稀疏混合MIMO相控阵雷达收发阵列设计

针对二维混合多输入多输出(MIMO)相控阵雷达发射子阵分割带来的自由度损失进而影响雷达系统参数估计性能的问题,提出一种基于十字阵的二维稀疏混合MIMO相控阵雷达收发阵列设计方法.首先,结合稀疏阵列-共轭嵌套阵对混合MIMO相控阵雷达的收发端进行稀疏设计;其次,对混合MIMO相控阵雷达产生的合阵进行做差处理,得到阵元位置差的差异阵列;最后,通过空间平滑处理进行波达方向估计.仿真实验表明,相较于传统的二维混合MIMO相控阵雷达,所提出方法仅利用两个互相垂直的一维线阵便可形成阵列的二维平面扩展,同时,在不增加阵元个数的前提下可有效扩展雷达阵列虚拟阵元数目,提高阵列的自由度以及波达方向估计性能.     

Joint frequency, 2-D DOA,and polarization estimation using parallel factor analysis

This paper proposes a new algorithm for joint frequency, two-dimensional (2-D) directions-of-arrival (DOA), and polarization estimation using parallel factor (PARAFAC) analysis model and cumulant. The proposed algorithm designs a new array configuration, and extends the PARAFAC analysis model from the common data-domain and subspace-domain to the cumulant one, and forms three-way arrays by using the three cumulant matrices obtained from the properly chosen dipole outputs, and analyzes the uniqueness of low-...     

Designing linear systolic arrays

We develop a simple mapping technique to design linear systolic arrays. The basic idea of our technique is to map the computations of a certain class of two-dimensional systolic arrays onto one-dimensional arrays. Using this technique, systolic algorithms are derived for problems such as matrix multiplication and transitive closure on linearly connected arrays of PEs with constant I/O bandwidth. Compared to known designs in the literature, our technique leads to modular systolic arrays with constant hardware in each PE, few control lines, lexicographic data input/output, and improved delay time. The unidirectional flow of control and data in our design assures implementation of the linear array in the known fault models of Wafer Scale Integration.     

Cellular automata with limited inter-cell bandwidth

A d-dimensional cellular automaton is a d-dimensional grid of interconnected interacting finite automata. There are models with parallel and sequential input modes. In the latter case, the distinguished automaton at the origin, the communication cell, is connected to the outside world and fetches the input sequentially. Often in the literature this model is referred to as an iterative array. In this paper, d-dimensional iterative arrays and one-dimensional cellular automata are investigated which operate in real and linear time and whose inter-cell communication bandwidth is restricted to some constant number of different messages independent of the number of states. It is known that even one-dimensional two-message iterative arrays accept rather complicated languages such as {a^p∣p prime} or {a²ⁿ∣n∈N} (H. Umeo, N. Kamikawa, Real-time generation of primes by a 1-bit-communication cellular automaton, Fund. Inform. 58 (2003) 421-435). Here, the computational capacity of d-dimensional iterative arrays with restricted communication is investigated and an infinite two-dimensional hierarchy with respect to dimensions and messages is shown. Furthermore, the computational capacity of the one-dimensional devices in question is compared with the power of two-way and one-way cellular automata with restricted communication. It turns out that the relations between iterative arrays and cellular automata are quite different from the relations in the unrestricted case. Additionally, an infinite strict message hierarchy for real-time two-way cellular automata is obtained as well as a very dense time hierarchy for k-message two-way cellular automata. Finally, the closure properties of one-dimensional iterative arrays with restricted communication are investigated and differences to the unrestricted case are shown as well.     

增强上下文的错误定位技术

错误定位就是寻找程序错误的位置.现有的错误定位方法大多利用测试用例的覆盖信息,以标识一组导致程序失效的可疑语句,却忽视了这些语句相互作用导致失效的上下文.因此,提出一种增强上下文的错误定位方法Context-FL,以构建上下文的方式来优化错误定位性能.Context-FL利用动态切片技术构建数据与控制相关性的错误传播上下文,显示了导致失效的语句之间传播依赖关系;然后,基于可疑值度量来区分上下文片段中不同语句的可疑度;最后,Context-FL以标记可疑值的上下文作为定位结果.实验结果表明,Context-FL优于8种典型错误定位方法.     

基于信息融合的汽车衡称重传感器故障诊断

传统汽车衡不具备故障诊断功能,任一称重传感器发生故障都将导致称重系统失效.为此提出了一种基于信息融合的汽车衡称重传感器故障诊断方法,利用径向基函数神经网络(RBFNN)逼近汽车衡多路称重传感器之间的函数关系,预测各传感器的输出,并给出RBFNN的训练算法;以各传感器的预测信号与实测信号为输入,建立了融合检测模型,采用表决融合检测准则,完成故障传感器寻址、故障类型识别、故障程度判决和故障传感器正常输出估计等故障诊断.大量实验与现场检定证明,采用这种方法的汽车衡准确实现了称重传感器故障诊断,任一称重传感器失效后的汽车衡性能优于正常状态下4级秤的指标,其最大称重误差0.7%,提高了系统可靠性.     

A practical approach for testing timed deterministic finite state machines with single clock

Finite State Machines (FSMs) are widely used for verification and testing of many reactive systems and many methods are proposed for generating tests from FSMs with the guaranteed fault coverage. However, some systems can only be properly described when time constraints are considered, advocating the adoption of models with the notion of time. In this paper, a method for deriving conformance tests with the guaranteed fault coverage from a Timed FSM (TFSM) with a single clock is presented. Test derivation is based on a given fault domain that allows the derivation of test suites with reasonable length. More precisely, the fault domain includes every possible faulty TFSM implementation with the known largest time constraints boundaries and minimal duration of time guards. Given a deterministic possibly partial TFSM specification, a complete test suite that guarantees the detection of all faulty implementations with respect to the above fault domain is derived. Experiments with randomly generated timed FSMs are conducted to determine length of obtained test suites and assess the impact of varying the TFSM specification parameters on length of obtained test suites. Further, experiments with both untimed and timed machines are conducted and these experiments show that similar patterns for timed and untimed machines are obtained with respect to varying the number of states, inputs, and outputs of machines.     

长线列红外探测器非均匀性校正技术研究

实时非均匀性校正是红外应用领域的关键技术之一。随着制作材料和加工工艺水平的提高,目前长线列红外探测器像元读出通道越来越多,虽然单通道像元读出速率不是很高,可是合并像元读出速率相当高,非均匀性校正的速度设计成为此类红外系统应用的瓶颈性问题,结合以往的研究成果和目前电子器件的发展水平,对若干种解决方案进行了比较。利用FPGA器件并行性的特点,对以往FPGA校正方案进行了改进,实验结果表明,该改进设计方案是完全可行的。该设计思路不光可以应用到更高性能线列红外探测器的非均匀性校正设计中,而且可以移植到类似的信号处理系统中,具有很大的工程应用价值。     

一种可应用于小型光伏的MPPT技术

提出了一种基于FOCV方法应用在小型光伏系统中的新型太阳能电池MPPT技术。首先．将太阳能电池阵列改变为全串联、全并联或串并混联的组合方式,相同的环境下,这些阵列在理论上拥有相同的最大输出功率,但需要不同的负载与阻抗相匹配;其次,许多拥有不同阻值的负载电阻可以被选择连接到太阳能电池阵列中,使太阳能电池的输出功率最大化;最后,使用MCU测量每种模式的电压并使用FOCV方法来确定最大的功率状态。     

Correction of array failure using grey wolf optimizer hybridized with an interior point algorithm

We design a grey wolf optimizer hybridized with an interior point algorithm to correct a faulty antenna array. If a single sensor fails, the radiation power pattern of the entire array is disturbed in terms of sidelobe level (SLL) and null depth level (NDL), and nulls are damaged and shifted from their original locations. All these issues can be solved by designing a new fitness function to reduce the error between the preferred and expected radiation power patterns and the null limitations. The hybrid algorithm has been designed to control the array’s faulty radiation power pattern. Antenna arrays composed of 21 sensors are used in an example simulation scenario. The MATLAB simulation results confirm the good performance of the proposed method, compared with the existing methods in terms of SLL and NDL.     

软件测试性度量框架研究

针对当前软件测试性度量框架适用范围有限、无法扩展的问题,提出一个新的度量框架。分析软件测试性概念,使用层次分析法得到新的框架结构。总结框架扩展方法,将测试性特性和影响因素加入到框架以进行软件测试性度量。其稳定性保证了框架对任何软件都具有相同的测试性度量过程和计算方法,可扩展性使得框架能随着软件技术的发展不断完善,两者为框架的通用性提供了保证。