4Gb DDR3 DRAM芯片

三星电子公司开发出首款使用50nm制造工艺生产的4Gb DDR3 DRAM芯片。     

DDR DRAM削减膝上计算机功耗

看第一眼,你觉得PC100／133与DDRDRAM在省电方面似乎没有什么两样,但仔细分析以后,你会发现DDR是更好的选择。为了探索更高的性能和更低的功耗,膝上计算机的设计正开始从SDRAM（PC10O／133）转向双速率（Doub卜DataRate,DDR）的DDRDRAM。在采用新的DDR做设计时,有几个因素是系统工程师必须考虑的,其中主要的因素是功耗问题。影响设计和布局布线的新结构特点也必须加以考虑。同样重要的是对成本与性能特性的理解。DDR功率分析比较两种不同的存储器系统的功耗是很有意义的,其中一个采用PC133SDRAM,另～个采用266M…     

30nm级4Gb DDR3DRAM：DRAM

三星电子推出量产30nm级4GbitsDDR3DRAM基板的32GB内存模块。内存模组具有高性能、低功耗、大容量等特点,能够在1．35V的电压下达到1．866Mbps传输速度,     

德州仪器推出新一代3A DDR端接稳压器

日前,德州仪器(TI)宣布推出一款可满足DDR、DDR2、DDR3与DDR4等各种低功耗存储器终端电源管理要求的汲极/源极双数据速率(DDR)终端稳压器TPS51200.该简便易用的新型稳压器的陶瓷输出电容仅为20μF,比同类竞争解决方案的电容降低了近80%.     

DRAM市场稳步发展512M DDR Ⅱ渐成主流

对于DRAM供应商来说，2004年是一个不错的年头。来自市场调研公司iSuppli的调查报告显示，2004年全球DRAM芯片市场收入达到267亿美元，与去年同期相比增长56．2％。相对于前几年DRAM市场的大幅波动和剧烈震荡，2004年DRAM市场表现强劲，已经由买方市场转变为卖方市场。业界人士认为，促成这种变化的主要原因是DRAM供应商的产品多元化战略。     

BGA小型化封装技术DDR DRAM时代显异彩

DRAM产业标准组织电子设备工程联合委员会定义了两种不同型态的DRAM包装，分别为薄型小尺寸封装（TSOP）以及球型栅数组（BGA）封装技术。其中TSOP由于拥有已经量产的优势以及较低的成本结构，因此长久以来就成为封装技术的当然选择，BGA过去则大部分使用在一些特定应用上，尤其是需要小型化的应用中，将BGA封装技术应用在标准型的DRAM上并非必要，因此基本上大多还是使用常见且较大包装尺寸的TSOP。不过接下来当DDR DRAM逐渐占据绝对的市场占有率时，我们应该重新检讨采用新封装标准所带来的成本效益与效率优点。     

温度自适应性DRAM刷新时钟电路

动态存储器(DRAM)需要通过刷新来保持内部的数据.为降低存储器刷新过程的电路功耗,设计一种具有温度自适应特性的刷新控制电路.根据二极管的电流在阈值电压附近的温度特性,利用电容充放电的结构,提出一种具有温度自适应特性的刷新时钟电路,使存储器刷新频率随电路温度变化而变化,其趋势符合动态存储器的刷新要求.仿真实验结果表明,新的电路在保证DRAM信息得到及时刷新的前提下,有效地降低了其刷新过程中的功耗.     

注重DDR电路的信号完整性

目前很多高清数字机顶盒都采用了DDR存储器,DDR是Double Data Rate的缩写,意为双倍数据速率.普通的SDRAM只是在时钟的上升沿进行一次数据传输,而DDR SDRAM可以在时钟的上升及下降沿各进行一次数据传输,从而达到双倍数据传输速率的效果.     

三星将大批量生产30纳米DDR3DRAM内存芯片

三星电子近日称,30纳米DDR3DRAM内存芯片已经适合消费者使用,准备应用到产品中。2GBDDR3内存芯片耗电量比用50纳米生产技术制造的内存芯片的耗电量减少了30％,生产成本效率提高了一倍多。三星用于笔记本电脑、台式电脑和服务器的2GBDDR3内存芯片只使用1．5伏或1．35伏电源。     

BiCMOS circuit technology for high-speed DRAMs

A BiCMOS circuit technology featured by a novel bit-line sense amplifier has been developed. The bit-line sense amplifier is composed of a BiCMOS differential amplifier, the impedance-converting means featured by the CMOS current mirror circuit or the clocked CMOS inverter between the bit line and the base node of the BiCMOS differential amplifier, and a conventional CMOS flip-flop. This technology can reduce the access time to half that of a conventional CMOS DRAM access time. Applied to a 1-kb DRAM test chip, a new BiCMOS circuit technology was successfully verified. Furthermore, the sensitivity and area penalty of the new BiCMOS bit-line sense amplifier and future applications to megabit DRAMs are discussed     

Low-voltage, high-speed circuit designs for gigabit DRAMs

This paper describes several new circuit design techniques for low V_CC regions: 1) a charge-amplifying boosted sensing (CABS) scheme which amplifies the sensing voltage difference (ΔV_BL ) as well as the V_GS margin by boosting the sensing node voltage with a voltage dependent boosting capacitor and 2) an I/O current sense amplifier with a high gain using a cross-coupled current mirror control scheme and reduced temperature sensitivity using a simple temperature-compensation scheme. An experimental 16 Mb DRAM chip with the 0.18-μm twin-well, triple-metal CMOS process has been fabricated, and an access time from the row address strobe (t_RAC) of 28 ns at V_cc=1.5 V and T=25°C has been obtained     

A built-in Hamming code ECC circuit for DRAMs

An error checking and correcting (ECC) technique that checks multiple cell data simultaneously and allows fast column access is described. The ECC circuit is optimized with respect to the increase in the chip area and the access-time penalty, and can be applied to a 16-Mbit DRAM with 20% chip area increase and less access-time penalty. The soft error rate has been estimated to be about 100 times smaller than that of the basic horizontal-vertical parity-code ECC technique     

Low voltage circuit design techniques for battery-operated and/orgiga-scale DRAMs

This paper describes a charge-transferred well (CTW) sensing method for high-speed array circuit operation and a level-controllable local power line (LCL) structure for high-speed/low-power operation of peripheral logic circuits, aimed at low voltage operating and/or giga-scale DRAMs. The CTW method achieves 19% faster sensing and the LCL structure realizes 42% faster peripheral logic operation than the conventional scheme, at 1.2 V in 15 Mb-level devices. The LCL structure realizes a subthreshold leakage current reduction of three or four orders of magnitude in sleep mode, compared with a conventional hierarchical power line structure. A negative-voltage word line technique that overcomes the refresh degradation resulting from reduced storage charge (Q_s) at low voltage operation for improved reliability is also discussed. An experimental 1.2 V 16 Mb DRAM with a RAS access time of 49 ns has been successfully developed using these technologies and a 0.4-μm CMOS process. The chip size is 7.9×16.7 mm² and cell size is 1.35×2.8 μm²     

An on-chip ECC circuit for correcting soft errors in DRAMs withtrench capacitors

A modified error-correcting code that can correct up to two soft errors on each row (word line) in a dynamic random-access memory (DRAM) chip is proposed. Double-bit soft errors frequently occur in DRAM cells with trench capacitors, when charged alpha particles impinge on the intervening space between two vertical capacitors causing plasma shorts between them. The conventional on-chip error-correcting codes (ECCs) cannot correct such double-bit word-line soft errors, which significantly increase the uncorrectable error rate (UER). An ECC circuit that uses an augmented rectangular product code to detect and correct double-bit soft errors is presented. The proposed circuit automatically corrects the addressed bit if it is faulty, and then quickly locates the other faulty bit. A comprehensive study is made to estimate improvements in soft error rate (SER) and mean time to failure (MTTF). The ability of the circuit to correct soft errors in the presence of multiple-bit errors has also been analyzed by combinatorial enumeration     

An efficient back-bias generator with hybrid pumping circuit for1.5-V DRAMs

An efficient back-bias (V_bb) generator with a newly introduced hybrid pumping circuit (HPC) is described. This system attains a V_bb level of -1.44 V at V_cc=1.5 V, compared to a conventional system in which V_bb only reaches -0.6 V. HPC can pump without the threshold voltage (V_th) loss that conventional systems suffer. HPC is indispensable for 1.5-V DRAMs, because a V_bb level lower than -1.0 V is necessary to meet the limitations of the V_th, of the access transistor. HPC uses one NMOS and one PMOS pumping transistor. By adopting a triple-well structure at the pumping circuit area, the NMOS can be employed as a pumping transistor without minority carrier injection     

DDR SDRAM控制电路电源完整性研究

高速数字电路对电源分配系统的可靠性和复杂性提出了很高要求。以DDR SDRAM控制电路为例,介绍电源分配系统的基本概念。采用基于系统目标阻抗的算法,用SPECCTRAQuest软件对电路的电源分配系统进行完整性仿真分析与设计。实践表明该方法不但可以设计出满足要求的电源分配系统,还能大幅提高设计效率,减少系统复杂度。     

DDR3与FPGA接口的高速电路板信号完整性分析

由于芯片频率的提高,现今高速PCB设计的信号完整性问题的分析已经成为不可忽略的关键环节。以FPGA控制DDR3 SDRAM读写数据的高速PCB板为硬件平台,论述高速PCB设计中的反射、串扰等信号完整问题并以Cadence公司的SPECCTRAQuest仿真器作为仿真工具,提出并验证了抑制反射和串扰的方法。仿真结果表明,端接电阻可抑制反射,且不同端接方式以及驱动端频率不同,抑制反射的效果有所不同;改变布线间距及走线长度可抑制串扰。通过布线前和布线后的仿真来指导PCB的设计,保证了硬件平台的正常工作。     

Optimized sensing scheme of DRAMs

The half-V_cc sensing scheme of CMOS dynamic RAMs (DRAMs) has been analyzed. It has been found that fluctuations of the cell-plate bias must be taken into account since they can degrade the sense signal. An improvement is possible by connecting the bit lines to the cell plate and its half-V_cc generator during precharge. Optimum performance of the sense amplifier is achieved if the PMOS and NMOS latches are activated simultaneously. The advantages are: (1) the sensitivity is improved due to the elimination of the offset contribution caused by unmatched capacitive loads; (2) the sensing speed is enhanced due to faster sense signal amplification; and (3) the peak current is reduced since the NMOS latch does not lower the voltage level of both bit line and reference bit line