基于多采样率控制的伺服系统摩擦补偿研究

摩擦是造成伺服系统在低速、速度换向等条件下精度严重下降的强非线性因素之一。采用基于模型的摩擦补偿可以有效地预测摩擦力,并实现误差补偿。在高速、高加速度的条件下,换向时摩擦变化剧烈,且过渡时间较短,采用单采样率控制补偿器结构很难实现较好的补偿效果,因此提出一种基于多采样率的摩擦补偿器结构。该补偿器利用伺服系统多环、多采样率的结构特点和指令轨迹细化方法,在不改变系统控制器结构和稳定性的条件下,通过分离前馈补偿器和反馈控制器的采样周期,以实现更为精细的前馈摩擦补偿量计算。实验结果表明,多采样率摩擦补偿器结构能够充分利用伺服控制器的结构特点和摩擦模型的预测结果,而且避免了复杂控制器的设计过程,取得了更有效的摩擦误差补偿效果。     

Impact of stray inductances of the power loop on false trigger‐on in the zero‐voltage‐switching full‐bridge converter

Here, we propose an exhaustive theoretical investigation and experimental verification of the false trigger‐on phenomenon, which would lead to the interaction between the upper and lower devices during the switching transient, in the zero‐voltage‐switching (ZVS) full‐bridge converter. An equivalent model of the converter, which takes not only the parasitic capacitors of the metal–oxide–semiconductor field‐effect transistors into account but also the stray inductances of the main circuit, is presented. Based on the model, a comprehensive study of the false trigger‐on phenomenon is carried out. According to the analysis results, the stray inductances of the metal–oxide–semiconductor field‐effect transistors have negligible influence on the false trigger‐on phenomena since the soft‐switching is realized. The false trigger‐on phenomenon is induced by the stray inductances of the main circuit. Moreover, the arrangement of the switching sequence would cause significant discriminations in the false trigger‐on phenomena because of the specific working mode of the ZVS full‐bridge converter. According to the investigation results, optimization methods are presented to suppress the induced voltage. At last, the theoretical investigations are verified by tests of a ZVS full‐bridge converter. Copyright © 2016 John Wiley & Sons, Ltd.     

A design guideline of parasitic inductance for preventing oscillatory false triggering of fast switching GaN‐FET

Gallium nitride field‐effect transistors (GaN‐FETs) are attractive devices because of its low on‐state resistance and fast switching capability. However, they can suffer from false triggering caused by fast switching. Particularly, a disastrous oscillation of repetitive false triggering can occur after a turn‐off, which may deteriorate the reliability of power converters. To address this issue, we give a design guideline to prevent this phenomenon. We analyze a simple circuit model to derive the condition of occurrence of this phenomenon, which is then verified experimentally. Results show that the parasitic inductance of the gating circuit, L_g, and that of the decoupling circuit, L_d, should be designed so that the LC resonance frequency of L_g and the gate–source capacitance of the GaN‐FET does not coincide with that of L_d and the drain–source capacitance, respectively. © 2016 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Development of gate drive circuit for next‐generation ultrahigh‐speed switching devices

This paper describes a gate drive circuit which is capable of driving an ultrahigh‐speed switching device and of suppressing high‐frequency noise caused by its high dV/dt ratio of 104 V/μs order. SiC (silicon carbide)‐based power semiconductor devices are very promising as next‐generation ultrahigh‐speed switching devices. However, one of their application problems is how to drive them with less high‐frequency noise without sacrificing their ultrahigh‐speed operation capability. The paper proposes a new gate drive circuit specialized for such devices, which charges and discharges the input capacitance of the device by using an impulse voltage generated by inductors. This ultrahigh‐speed switching operation causes a high‐frequency common‐mode noise current in the gate drive circuit, which penetrates an isolated power‐supply transformer due to the parasitic capacitance between the primary and the secondary windings. In order to overcome this secondary problem, a toroidal multicore transformer is also proposed in the paper in order to reduce the parasitic capacitance drastically. By applying the former technique, the turn‐on time and turn‐off time of the power device were shortened by 50% and by 20%, compared with a conventional push‐pull gate drive circuit, respectively. In addition, the latter technique allows reduction of the peak common‐mode noise current to 25%, compared with the use of a conventional standard utility power‐supply transformer. © 2011 Wiley Periodicals, Inc. Electr Eng Jpn, 176(4): 52–60, 2011; Published online in Wiley Online Library ( wileyonlinelibrary.com ). DOI 10.1002/eej.21124     

Travelling wave pilot protection for LCC-HVDC transmission lines based on electronic transformers’ differential output characteristic

Considering travelling wave’s bandwidth which varies from several kilohertz to hundreds of kilohertz, traditional current and voltage transformers cannot transfer whole bandwidth of travelling wave. However, electronic transformers, including Rogowski coil based electronic current transformer and capacitance divided electronic voltage transformer, have much wider bandwidth (up to 500 kHz) which could transfer almost whole bandwidth of travelling wave without distortion. Besides, secondary side’s output of electronic transformer is the differential signal of primary side. So, the integration circuit can be omitted when using differential travelling wave signal directly in protection principle. Traditional travelling protection for high voltage direct current (HVDC) lines is highly affected by grounding resistance. And the backup protection, such as current differential protection, has long operation time. So the paper proposes a novel travelling wave pilot protection based on the differential output signal of electronic transformers. Differential voltage and current travelling wave have axisymmetric relationship when the fault occurs at forward direction. Conversely, differential voltage and current travelling wave almost overlap when the fault occurs at reverse direction. Considering fault direction identification results of two ends, fault section can be determined. Besides, according to amplitude ratio of fault line and normal line, fault line can be selected correctly. The simulation results in PSCAD/EMTDC prove the correctness, sensitivity and reliability.     

A novel efficiency‐enhancement topology: GaN high‐electron mobility transistors with waveform‐modulation structure composed of Schottky diodes

To improve the power‐added efficiency (PAE) of the gallium nitride (GaN) high‐electron mobility transistor (HEMT) in radio frequency applications, this paper studies the relationship between the nonlinearity of the gate capacitance and the PAE of the GaN HEMTs. The theoretical analysis and simulation results demonstrate that the nonlinearity of the gate capacitance modulates the signal phase at the GaN HEMT input and increases the average drain current, leading to increased power consumption and reduced PAE. Then, an efficiency‐enhancement topology for GaN HEMTs that employs the waveform‐modulation effect of Schottky diodes to reduce power consumption and improve efficiency is presented. The efficiency‐enhancement topology for a 4 × 100‐μm GaN HEMT with waveform‐modulation diodes is then fabricated. Results of load‐pull test demonstrate that the novel topology can increase the PAE of the 4 × 100‐μm GaN HEMT by more than 5% at 8 GHz. The novel efficiency‐enhancement topology for GaN HEMTs proposed in this paper will be suitable for applications that demand high‐efficiency GaN HEMTs or circuits.     

寄生电感对于功率MOSFET开关特性的影响

分散在MOSFET栅极、源极、漏极的寄生电感由于封装以及印制电路板（PCB）走线,改变了MOSFET的开关特性。通过仿真分析对比,指出MOSFET寄生电感存在如下特性：源极电感对栅极驱动形成负反馈,导致开关速度变慢,采用开尔文连接,可以将栅极回路与功率回路解耦,提高驱动速度;在米勒效应发生时刻需要合理地降低栅极电感来降低栅极驱动电流;漏极电感通过米勒电容影响MOSFET的开通速度,在关断时刻导致电压应力增加;在并联的回路当中,非对称的布局将导致MOSFET之间的动态不均流;当MOSFET在开关过程中,环路电感与MOSFET自身的结电容产生振荡时,可以在电路增加吸收电容减小环路电感,改变振荡特性。     

Algebraic multigrid Laplace solver for the extraction of capacitances of conductors in multi‐layer dielectrics

This paper describes the development of a robust multigrid, finite element‐based, Laplace solver for accurate capacitance extraction of conductors embedded in multi‐layer dielectric domains. An algebraic multigrid based on element interpolation is adopted and streamlined for the development of the proposed solver. In particular, a new, node‐based agglomeration scheme is proposed to speed up the process of agglomeration. Several attributes of this new method are investigated through the application of the Laplace solver to the calculation of the per‐unit‐length capacitance of configurations of parallel, uniform conductors embedded in multi‐layer dielectric substrates. These two‐dimensional configurations are commonly encountered as high‐speed interconnect structures for integrated electronic circuits. The proposed method is shown to be particularly robust and accurate for structures with very thin dielectric layers characterized by large variation in their electric permittivities. More specifically, it is demonstrated that for such geometries the proposed node‐based agglomeration systematically reduces the problem size and speeds up the iterative solution of the finite element matrix. Copyright © 2007 John Wiley & Sons, Ltd.     

Matching capacitance and transfer efficiency of four wireless power transfer systems via magnetic coupling resonance

Matching capacitance determines the resonance and resonant frequency for a given wireless power transfer (WPT) system. Theoretical solutions for matching capacitance are essential to designing and controlling a coupling system in resonant status and to ensuring that the system operates under high power transfer efficiency. This paper deduced all the analytical expressions of matching capacitance to achieve magnetic resonance for four classical circuitries when considering the coils' resistances. Our results showed that there are several kinds of capacitance matching methods for each circuitry to achieve resonance. Matching capacitances, different from those in the existing literatures, make the system really operate under the magnetic coupling resonance. In literatures, the capacitance at the receiver side compensated only the self‐inductance of the receiver coil and the system except series to series did not operate in the resonance state. Furthermore, the resonance conditions in applications were then given. Accordingly, the expressions of resonant WPT efficiency were presented. These expressions revealed how the underlying factors besides matching capacitance affect the power transfer efficiency, and provided easy access optimizing circuit parameters for high transfer efficiency. Four kinds of circuits were compared through theoretical analysis, calculations and experiments. Experimental results verified the theoretical solutions. Copyright © 2016 John Wiley & Sons, Ltd.     

可控三相电抗器IGBT电路实现过渡分析

对可控三相电抗器IGBT电路实现的过渡过程进行仿真分析。在实验电路起始参数的基础上,研究负载电容对过渡过程的影响,结果表明负载电容足够大时,过渡过程时间可降为零。各电抗器可控电容相等时,电抗器可控电容越大所对应的的负载电容临界值也越大,且两者之间的比例关系随电容增大呈变小趋势,这是由IGBT器件电容效应引起的。最后,分别分析了靠近电源端的可控电容和靠近负载端的可控电容对可控电抗器过渡过程的影响,结果表明靠近电源端的电抗器可控电容对过渡过程影响较大。     

A wide variable‐range CMOS–VCXO for IC

Recently, miniaturization, low power consumption, and high‐frequency stability have been required in crystal oscillators as a frequency source, because of the rapid development of mobile communications, typified by cellular phones. Usually, a VCXO (Voltage Controlled Crystal Oscillator) has been included in PLL. And it has been required that the VCXO should be implemented on a CMOS–IC chip. The oscillating frequency of a traditional VCXO has been controlled by capacitance variation of a varactor diode. But it is difficult to implement the varactor diode on an IC chip. In our previous study, we showed that a transistor VCXO utilizing the MOSFET's Miller capacitance of a variable capacitance circuit had a wide frequency variable range. On the other hand, in a CMOS–VCXO, the Miller capacitance has decreased. Therefore, a wide frequency variable range could not be obtained by utilizing the Miller capacitance in the CMOS–VCXO. In this paper, first, a variable capacitance circuit is realized in order to construct a wide‐variable‐range CMOS–VCXO for IC. The variable capacitance circuit is composed of a MOSFET as a voltage controlled resistance. Next, the CMOS–VCXO is constructed by the variable capacitance circuit and a CMOS crystal oscillator. As a result, we show that the CMOS–VCXO has a wide frequency variable range of about 400 ppm.© 1999 Scripta Technica, Electr Eng Jpn, 130(3): 49–56, 2000     

高压输电线路双端故障测距新算法

基于故障点电压幅值相等的双端故障定位方法,由于两端采样数据不同步会存在伪根判别问题。分析两端数据不同步时伪根产生的原因,并利用故障分量电压分布规律,提出基于故障分量不存在伪根判别问题的简单迭代定位方法,证明了该方法收敛性和惟一性。该方法采用线路分布参数模型,不受线路分布电容影响,计算简单。通过仿真验证该方案收敛速度快．不受过渡电阻、故障初始角、两端采样数据不同步等因素的影响,测距精度高。     

P‐channel logic 2 T eDRAM macro with high retention bit architecture

This study presents a novel approach which enhances the data retention capability of PMOS gain cell based embedded DRAM. The proposed circuit technique utilizes a parasitic capacitance between the cell storage node and the common n‐well body. During the write operation, an up‐down voltage transition to the n‐well increases the cell storage retention time without using any optional devices. It also results in much high immunity against the write “1” disturbance. Measured and simulated results from an 8192‐wordx8‐bit eDRAM macro implemented in a 0.13‐μm generic CMOS process exhibit 58% increased retention time and approximately 3.6 times stronger write disturbance immunity over the conventional design.     

Noncontact energy transfer system using immittance converter

Noncontact energy transfer systems are widely used in industrial material handling systems. This paper proposes a new noncontact energy transfer system using a tuned pickup coil and an immitance converter inductively coupled to a parallel transmission line excited by a high‐frequency constant‐current source. In a noncontact energy transfer system which supplies continuous energy to movers by electromagnetic induction, the efficiency is low owing to low excitation impedance because of the wide air gap of the magnetic core in the pickup coil. The excitation impedance can be increased by the resonance with a capacitor connected parallel to the pickup coil. The resonant pickup coil works as a high‐frequency constant‐current source for the load. We propose using an immittance converter to transform the high‐frequency constant‐current source into a high‐frequency constant‐voltage source. Then, the high‐frequency constant‐voltage source is rectified into a constant‐voltage dc source, and supplies power to an inverter for motor driving. In this paper, the configuration of this new noncontact energy transfer system and its characteristics are described. The experimental results and simulation waveforms are also described. © 2001 Scripta Technica, Electr Eng Jpn, 136(4): 58–64, 2001     

Input and reverse transfer capacitance measurement of MOS-gatedpower transistors under high current flow

The measurement principle of the input and reverse transfer capacitance is shown. Function, stability, and operation of the measurement circuits are discussed. The on-state capacitances of a power DMOS transistor were measured under high current conditions of up to 250 A. A strong nonlinear characteristic is observed     

Transient characteristics of a tapped‐winding capacitor motor

Tapped‐winding capacitor motors are widely used for fans in air conditioners as speed adjusting motors. In tapped‐winding capacitor motors, the burnout accidents of phase‐shifting capacitors have been seen on occasion. The cause of such accidents is considered to be the transient capacitor current. In this paper, equations for calculating transient characteristics are derived for three types of tapped‐winding capacitor motors. Based on these equations, transient characteristics are clarified in high‐ and low‐speed winding connections. Further, from the design viewpoint, the effects of the turn ratio and capacitance of the capacitor on the transient characteristics are examined and a procedure for choosing the winding ratio and capacitance of the capacitor is suggested. Using this method, the transient current is shown to decrease by about 40%. © 2002 Wiley Periodicals, Inc. Electr Eng Jpn, 141(4): 69–77, 2002; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.10063     

Relationship between current waveform just before current zero and interruption ability of high‐speed VCB

A high‐speed vacuum circuit breaker which forces the fault current to zero was investigated. The test circuit breaker consisted of a vacuum interrupter and a high‐frequency current source. A vacuum interrupter with an axial magnetic field electrode and a disk‐shaped electrode was tested. The arcing period of the high‐speed vacuum circuit breaker is much shorter than that of a conventional circuit breaker. The arc behavior of the test electrodes immediately after the contact separation was observed by a high‐speed video recorder. The relation between the current waveform just before the current zero point and the interruption ability was investigated experimentally by varying the high‐frequency current source. The results demonstrate the interruption ability and the arc behavior of the high‐speed vacuum circuit breaker. Effective current interruption is made possible by a low current period just before the current zero point, even though the arcing time is short and the arc is concentrated. © 2010 Wiley Periodicals, Inc. Electr Eng Jpn, 172(2): 20–27, 2010; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.20915     

计及模速差异与杂散电容的反向行波辨识

单端法是行波测距研究的热点,但第2个浪涌波头的辨识因非故障线路及故障对端母线的存在变得困难。为此藉助故障行波线模与零模波速的差异提出一种区分故障半程内外的辅助判据。反向行波虽能有效抑制相邻非故障线路行波折射的影响,但仅基于极性比较的方法并不能准确地辨识出第2个电压行波,故考虑电压行波在实际变电站母线杂散电容处的传播特性,即电压行波在杂散电容处的初始反射系数恒为负的结果而利用第2个反向行波相对极性进行波头辨识。理论分析和实际仿真结果表明,这种方法不受线路两端母线类型影响,对单端行波测距法的有效实施有非常现实的意义。     

Accurate prediction of the volume inversion impact on undoped Double Gate MOSFET capacitances

This paper demonstrates the capability of our previously published undoped Double‐Gate (DG) MOSFET explicit and analytical compact model to also forecast the effect of the volume inversion (VI) on the intrinsic capacitances. For that purpose, we present simulation results for these capacitances. We show now that the model presents an accurate dependence on the silicon layer thickness, consistent with two‐dimensional numerical simulations, for both thin and thick silicon films. As opposed to our previous work, here we test the capacitance model for three different film thicknesses and also show that the transition from VI regime to dual gate behaviour is well simulated. We demonstrate in this paper that even if the current drive and transconductance are enhanced in VI regime, our results show that intrinsic capacitances are higher as well, which may limit the high‐speed (delay time) behaviour of DG MOSFETs under VI regime. The good agreement between the numerical simulations and our model shows the high potential of our complete DG MOSFET model. Copyright © 2010 John Wiley & Sons, Ltd.