Analysis of a high frequency and wide bandwidth active polyphase filter based on CMOS inverters

An active polyphase filter capable of high frequency quadrature signal generation has been analyzed. The resistors of the classical passive polyphase filter have been replaced by transconductors, CMOS inverters (F. Tillman and H. Sjöland, Proceedings of the Norchip Conference (pp. 12–15), Nov. 2005; Analog Integrated Circuits and Signal Processing, 50(1) 7–12, 2007). A three-stage 0.13 μm CMOS active polyphase filter has been designed. Simulations with a differential input signal show a quadrature error less than 1° for the full stable input voltage range for frequencies from 6 GHz to 14 GHz. Phase errors in the differential input signal are suppressed at least three times at the output. Corner simulations at 10 GHz show a maximum phase error of 3° with both n- and pMOS slow, in all other cases the error is less than 0.75°. The three-stage filter consumes 34 mA from a 1.2 V supply. To investigate the robustness of the filter to changes in inverter delay, an inverter model was implemented in Verilog-A. Linear c _in and g _in were used, whereas g _m , c _out , and g _out were non-linear. It was found that the filter could tolerate substantial delays. Up to 40° phase shift resulted in less than 1.5° quadrature phase error at the output.     

A 2 GHz variable gain low noise amplifier in 0.18-μm CMOS

This paper describes a 2 GHz active variable gain low noise amplifier (VGLNA) in a 0.18-μm CMOS process. The VGLNA provides a 50-Ω input impedance and utilizes a tuned load to provide high selectivity. The VGLNA achieves a maximum small signal gain of 16.8 dB and a minimum gain of 4.6 dB with good input return loss. In the high gain and the low gain modes, the NFs are 0.83 dB and 2.8 dB, respectively. The VGLNA’s IIP3 in the high gain mode is 2.13 dBm. The LNA consumes approximately 4 mA of current from a 1.8-V power supply.     

10 GHz dual-conversion low-IF downconverter with microwave and analogue quadrature generators

A 10 GHz dual-conversion low-IF downconverter using 0.18-mum CMOS technology is demonstrated. The high-frequency quadrature RF and LO₁ signals are generated by broadside-coupled quadrature couplers while a two-section polyphase filter is utilised for the low-frequency LO₂ quadrature signal generation. As a result, the demonstrated downconverter achieves a conversion gain of 7 dB, IP_{1 dB} of -16 dBm, IIP₃ of -5 dBm and noise figure of 26 dB at a 1.8 V supply. The image-rejection ratio of the first/second image signal is 33/42 dB for IF frequency ranging from 10 to 60 MHz, respectively.     

System simulations of a 1.5 V SiGe 81–86 GHz E-band transmitter

This paper presents simulation results for a sliding-IF SiGe E-band transmitter circuit for the 81–86 GHz E-band. The circuit was designed in a SiGe process with f _T  = 200 GHz and uses a supply of 1.5 V. The low supply voltage eliminates the need for a dedicated transmitter voltage regulator. The carrier generation is based on a 28 GHz quadrature voltage oscillator (QVCO). Upconversion to 84 GHz is performed by first mixing with the QVCO signals, converting the signal from baseband to 28 GHz, and then mixing it with the 56 GHz QVCO second harmonic, present at the emitter nodes of the QVCO core devices. The second mixer is connected to a three-stage power amplifier utilizing capacitive cross-coupling to increase the gain, providing a saturated output power of +14 dBm with a 1 dB output compression point of +11 dBm. E-band radio links using higher order modulation, e.g. 64 QAM, are sensitive to I/Q phase errors. The presented design is based on a 28 GHz QVCO, the lower frequency reducing the phase error due to mismatch in active and passive devices. The I/Q mismatch can be further reduced by adjusting varactors connected to each QVCO output. The analog performance of the transmitter is based on ADS Momentum models of all inductors and transformers, and layout parasitic extracted views of the active parts. For the simulations with a 16 QAM modulated baseband input signal, however, the Momentum models were replaced with lumped equivalent models to ease simulator convergence. Constellation diagrams and error vector magnitude (EVM) were calculated in MATLAB using data from transient simulations. The EVM dependency on QVCO phase noise, I/Q imbalance and PA compression has been analyzed. For an average output power of 7.5 dBm, the design achieves 7.2% EVM for a 16 QAM signal with 1 GHz bandwidth. The current consumption of the transmitter, including the PA, equals 131 mA from a 1.5 V supply.     

An integrated 0.38–6 GHz, 9–12 GHz fully differential fractional-N frequency synthesizer for multi-standard reconfigurable MIMO communication application

A wide-band fully differential fractional-N frequency synthesizer for multi-standard application is presented. The single fully differential LC–VCO with 28.5 % tuning rang and a set of dividers, quadrature self-mixer are designed to accomplish the multi-frequency bands with the frequency band from 0.38 to 6 GHz and from 9.0 to 12 GHz. It covers several wireless standards. A novel high isolation multiplexer is presented to achieve the frequency band selection. This chip was implemented with 65 nm CMOS technology and the maximum consumption is 20.05 mA from 1.2 V power supply. It occupies an active area of 1.5 mm². The measured typical phase noise of the frequency synthesizer is ?114.6 dBc/Hz from 1 MHz offset for 4.85 GHz output.     

A CMOS dual-channel, 100-MHz to 1.1-GHz transmitter for cableapplications

A dual-channel wide-band transmitter for cable applications is presented that has more than a decade frequency coverage. The chip consists of two parallel transmitters that are both fully operational from 100 MHz up to 1.1 GHz. Using a single-ended current-mode output topology, the radio-frequency (RF) output signals are lossless combined by summing the output currents. The third-order harmonic of the oscillator signal is filtered by a wide-band polyphase filter. The complex filtering operation is mathematically described in this paper. The on-chip integrated oscillators have a measured 55-1200 MHz tuning range. Using the polyphase filter, a linear mixer topology, and a linear output driver, all distortion components are below -40 dBc. All intermodulation products of the two channels are smaller than -48 dBc. In this way, it is guaranteed that the parallel channels do not disturb the other channels in the frequency band even without any channel-specific filtering. Each channel delivers the designed -16-dBm RF output signal. The measured transmitter noise floor is situated at -139.8 dBc/Hz. The chip has been processed in a standard 0.5 μm CMOS technology     

A low-cost, wide-band DCO with an on-chip 3-D solenoid inductor in 0.13 μm digital CMOS

This paper presents a wide band, fine-resolution digitally controlled oscillator (DCO) with an on-chip 3-D solenoid inductor using the 0.13 μm digital CMOS process. The on-chip solenoid inductor is vertically constructed by using Metal and Via layers with a horizontal scalability. Compared to a spiral inductor, it has the advantage of occupying a small area and this is due to its 3-D structure. To control the frequency of the DCO, active capacitor and active inductor are tuned digitally. To cover the wide tuning range, a three-step coarse tuning scheme is used. In addition, the DCO gain needs to be calibrated digitally to compensate for gain variations. The DCO with solenoid inductor is fabricated in 0.13 μm process and the die area of the solenoid inductor is 0.013 mm². The DCO tuning range is about 52 % at 4.1 GHz, and the power consumption is 6.6 mW from a 1.2 V supply voltage. An effective frequency resolution is 0.14 kHz. The measured phase noise of the DCO output at 5.195 GHz is ?110.17 dBc/Hz at 1 MHz offset.     

A tunable and reconfigurable MMIC active filter in GaAs technology

The filter presented in this article is an active band-pass filter whose center frequency and bandwidth can be tuned. It is composed of channels inserted into a distributed structure, and the frequency agility is obtained by activating one or more of them. The concept is validated with measurements realized on a 3-channel prototype structure implemented in the United Monolithic Semiconductors (UMS) PPH25 GaAs technology from UMS. This filter is tunable throughout the X and Ku bands. This first prototype yields encouraging results: the center frequency can be tuned between 9.7 and 14 GHz, with an average gain of 10 dB throughout this range and a noise figure between 7 and 11 dB. The filter occupies 13.5 mm² of area and consumes 10.5 mA per active stage from a 4 V supplying voltage. It is designed for wideband and agile receivers.     

A 65 mW, 0.4–2.3 GHz Bandpass Filter for Satellite Receivers

A monolithic tunable bandpass filter for satellite receiver front-ends is presented. The center frequency of the bandpass filter can be tuned from 0.4 GHz to 2.3 GHz. The filter is constructed using four transconductor-C poly-phase filter sections and has a 50 dB variable gain range. At 20 dB attenuation and at 30 dB gain the measured 1 dB compression point is –21 dBm and –56 dBm, respectively. Measured input IP3 is –12 dBm. The noise figure is 15 dB at maximum gain. An on-chip I/Q oscillator tracks the center frequency and enables automatic tuning. The bandpass filter dissipates 65 mW with 5 Volt supply voltage and occupies 0.16 mm² chip area. The filter is realized in a standard 11 GHz f _t bipolar technology.     

An I/Q mixer with an integrated differential quadrature all-pass filter for on-chip quadrature LO signal generation

A down-conversion in-phase/quadrature (I/Q) mixer employing a folded-type topology, integrated with a passive differential quadrature all-pass filter (D-QAF), in order to realize the final down-conversion stage of a 60 GHz receiver architecture is presented in this work. Instead of employing conventional quadrature generation techniques such as a polyphase filter or a frequency divider for the local oscillator (LO) of the mixer, a passive D-QAF structure is employed. Fabricated in a 65 nm CMOS process, the mixer exhibits a voltage gain of 7-8 dB in an intermediate frequency (IF) band ranging from 10 MHz-1.75 GHz. A fixed LO frequency of 12 GHz is used to down-convert a radio frequency (RF) band of 10.25-13.75 GHz. The mixer displays a third order input referred intercept point (IIP₃) ranging from -8.75 to -7.37 dBm for a fixed IF frequency of 10 MHz and a minimum single-sideband noise figure (SSB-NF) of 11.3 dB. The mixer draws a current of 6 mA from a 1.2 V supply voltage dissipating a power of 7.2 mW.     

A high performance CNFET-based operational transconductance amplifier and its applications

High performance electronic systems face several challenges in driving innovative integrated circuits when the internal transistors are scaled down below 45 nm. Carbon nanotube field effect transistors (CNFETs) are considered as excellent candidates for building energy-efficient electronic systems in the near future, due to their unique characteristics such as ballistic transport, scalability, and better channel electrostatics. In this paper, a new high performance operational transconductance amplifier (OTA) based on 32 nm CNFET devices is presented. The proposed OTA maintains a highly linear wide continuous tuning range and a wide frequency response range, enabled by splitting the linear voltage-to-current conversion and tuning two different blocks. As an application, a universal second-order transconductance-capacitor (G _m  ? C) filter realized using the OTA is introduced. Simulation results show that the CNFET-based OTA offers very a low current consumption of 2.35 μA from a ± 0.9 V power supply, achieves a bandwidth of 9.5 MHz, and has an input dynamic range of ± 0.2 V.     

Characterization of a photonic active integrated antenna using a direct off-air transmission technique

This article presents a characterization study of a state-of-the-art 40 GHz mode-locked laser using a hybrid integrated microstrip patch antenna and bias-T circuit. A passive mode-locking range of 300 MHz is measured using this technique by tuning the gain and saturable absorber bias values for a maximum wireless distance of 15 cm. The passive mode-locking signal is detected by a direct off-air method from a photonic active integrated antenna. This signal can be used as a remote local oscillator to downconvert incoming signals as part of a bidirectional system for in-building/campus wide remote antenna units in next generation millimetre-wave radio-over-fibre systems.     

A 0.7 V 6.66–9.36 GHz wide tuning range CMOS LC VCO with small chip size

The circuit designs are based on TSMC 0.18 μm CMOS standard technology model. The designed circuit uses transformer coupling technology in order to decrease chip area and increase the Q value. The switched-capacitor topology array enables the voltage-controlled oscillator (VCO) to be tuned between 6.66 and 9.36 GHz with 4.9 mW power consumption at supply voltage of 0.7 V, and the tuning range of the circuit can reach 33.7%. The measured phase noise is ?110.5 dBc/Hz at 1 MHz offset from the carrier frequency of 7.113 GHz. The output power level is about ?1.22 dBm. The figure-of-merit and figure-of-merit-with-tuning range of the VCO are about ?180.7 and ?191.25 dBc/Hz, respectively. The chip area is 0.429 mm² excluding the pads. The presented ultra-wideband VCO leads to a better performance in terms of power consumption, tuning range, chip size and output power level for low supply voltage.     

GaAs active structures with applications to microwave wideband 90° phase shifters and bandstop filters

Lumped-element second-order active filters are presented which can either be tuned to an all-pass response and then especially used in 90° phase shifters, or tuned to a bandstop response. Their structures have been chosen so that they can be easily implemented in the microwave domain. Preliminary simulations have shown that the filter having the highest-frequency capabilities results in a 90^° phase shifter operating up to the (6 GHz, 1O GHz) band, and that its centre frequency can be tuned up to 15 GHz when it is used as a bandstop filter.     

A novel zero dead zone PFD and efficient CP for PLL applications

This paper presents a high dynamic range programmable gain amplifier (PGA) with linear-in-dB and digital to analog converter (DAC) gain control using a BiCMOS process. The proposed PGA is composed of a folded Gilbert variable gain amplifier cell, a DC offset cancellation circuitry, two inductorless fixed gain amplifiers with bandwidth extension, a symmetrical exponential voltage generator, a novel buffer amplifier with active inductive peaking for testing purposes and a 10 bit R-2R DAC. The linear-in-dB and DAC gain control scheme facilitate the analog baseband gain tuning accuracy and stability, which also provides an efficient way for digital baseband automatic gain control. The PGA chip is fabricated using 0.13 μm SiGe BiCMOS technology. With a power consumption of 80 mA@1.2 V supply voltage, the fabricated circuit exhibits a tunable gain range of ? 30–27 dB (DAC linear gain step guaranteed), a 3 dB bandwidth of around 3.5 GHz and a gain resolution of better than 0.07 dB.     

A 60 GHz receiver front-end with PLL based phase controlled LO generation for phased-arrays

This paper presents a front-end architecture for fully integrated 60 GHz phased array receivers. It employs LO-path beamforming using a phase controlled phase-locked loop (PC-PLL). To demonstrate the architecture a circuit is implemented featuring a two stage low noise amplifier, two cascaded active mixers, and a PC-PLL. The receiver downconverts the 60 GHz signal in two steps, using LO signals from the 20 GHz QVCO of the PLL. A differential 2nd-order harmonic is coupled from the sources of the current commutating pairs of the QVCO, feeding the LO-port of the first mixer and downconverting the 60 GHz RF signal to a 20 GHz intermediate frequency. Quadrature 20 GHz LO signals are then used in the second mixer to down-convert the IF signal to baseband. The PLL is locked to a relatively high reference frequency, 1.25 GHz, which reduces the size of the PLL loop filter and enables a compact layout. The measurements show an input return loss better than ?10 dB between 57.5 and 60.8 GHz, a 15 dB voltage gain, and a 9 dB noise figure. Two-tone measurements show ?12.5 dBm IIP3, 29 dBm IIP2, and ?24 dBm ICP1. The PC-PLL phase noise is ?105 dBc/Hz at 1 MHz offset from a 20 GHz carrier, and the phase of the received 60 GHz signal is digitally controllable with a resolution of 3.2°, covering the full 360° range with a phase error smaller than 1°. The chip consumes 80 mA from a 1.2 V supply, and measures 1,400 μm × 660 μm (900 μm × 500 μm excluding pads) including LNAs, mixers, and PC-PLL in a 90 nm RF CMOS process.     

A wideband receiver front-end using 1st and 3rd harmonics of the <Emphasis Type="Italic">N</Emphasis>-path filter response

Harmonic selectivity and inaccessibility to accurate low-power high frequency clock generator are two main imperfections in the tunable N-path filters. In this paper, conventional N-path filter and conventional harmonic rejection (HR) N-path architectures are analyzed, and related equations are derived and are verified by simulation results. Furthermore, a wideband tunable receiver front-end using HR N-path switching systems is proposed. Using third harmonic of filter response instead of fundamental harmonic, the required input clock frequency in the multi-phase clock generator is decreased by a factor of three. The receiver front-end benefits low and high frequency bands. At low frequency band (0.4–1.2 GHz) the first harmonic, and at high frequency band (1.2–3.3 GHz) the third harmonic of filter response are selected and are downconverted to the baseband frequency. The structure is designed and is simulated using CMOS-90 nm technology in schematic level. The total power consumption and \(S_{11}\) are \(<27.14\) mW and \(-13.5\) dB, respectively. Furthermore, NF at low and high frequency bands are 2.56 and 3.53 dB, respectively.     

Cascadable Current-Mode Biquad Filter and Quadrature Oscillator Using DO-CCCIIs and OTA

This article introduces a circuit which can function both as a quadrature oscillator and as a universal biquad filter (lowpass, highpass, bandpass). When the circuit functions as a universal biquad filter, the quality factor and pole frequency can be tuned orthogonally via the input bias currents. When it functions as a quadrature oscillator, the oscillation condition and oscillation frequency can be adjusted independently by the input bias currents. The proposed circuit can work as either a quadrature oscillator or a biquad filter without changing the circuit topology. The amplitude of the proposed oscillator can be independently controlled via the input bias currents. The proposed oscillator can be applied to provide amplitude modulated/amplitude shift keyed signals with the above-mentioned major advantages. The circuit is very simple, consisting of four dual-output second generation current controlled current conveyors (DO-CCCIIs), one operational transconductance amplifier (OTA), and two grounded capacitors. Without any external resistors and using only grounded elements, this circuit is therefore suitable for IC architecture. PSPICE simulation results are depicted here, and the given results agree well with the theoretical analysis. The power consumption is approximately 7.32 mW at ±2.5 V supply voltages.     

A 0.5–1 GHz single stage linear-in-decibel VGA with 80 dB gain range in 0.18 μm CMOS

Communication systems require a wide gain range. For example the code-division multiple access system (CDMA) requires more than 80 dB of gain range so that, many variable gain amplifiers (VGAs) must be used, resulting in high power consumption and low linearity because of VGA non-linearity factors. In this paper, a one-stage VGA in 0.18 μm technology is presented. The VGA based on the class AB power amplifier is designed and simulated for a high linearity and an 80 dB tuning range. For the linear-in-decibel tuning range, transistors in sub-threshold region is used. The current control circuit of the VGA changes gain continuously from ?68 to 18 dB at 0.5 GHz and ?60 to 20 dB at 1 GHz with gain error of less than 2 dB. The power consumption enjoys a highest value about 13.5 mW in the maximum gain and P1dB is also about ?3.4 dBm at 0.5 GHz and 2.2 dBm at 1 GHz.     

Multiband monolithic BiCMOS low-power low-IF WLAN receivers

This letter presents the design, implementation, and measurements of two monolithic low-IF receivers compliant with the main WLAN standards. The first receiver targets the three 5GHz U-NII bands, while the second allows dual-band operation in the 2GHz and 5GHz bands. Fabricated in a 47GHz-f/sub t/ BiCMOS technology, both consist of a low-noise preamplifier, two matched active singly-balanced mixers and two polyphase filters, used to generate quadrature LO signals and provide image-rejection. The single-band receiver exhibits 25 dB of conversion gain, 8.9 dB of NF and -19 dBm of P/sub 1 dB/, while consuming 19 mW. The dual-band receiver shows similar performances in the 5GHz band, and extends its operation in the 2GHz band, achieving 33.4dB of conversion gain, 4.1dB of NF and -26dBm of P/sub 1 dB/, while consuming 14.9mW.