基于运动矢量中心偏置的运动估计搜索策略

在对运动图像进行运动估计的时候,搜索策略的选择对运动估计的准确性、运动估计的速度影响重大。介绍一种基于运动矢量中心偏置的运动估计搜索策略,该搜索策略是根据运动矢量具有中心偏置分布的特点,以块误差函数最小作为调整搜索区域大小和位置的判断依据,从而实现准确的运动估计。详细叙述了算法的实现步骤,并通过实验比较,得出该算法在运算速度、信噪比方面的效果都较好。     

创新的高效方向性菱形-弧形快速块匹配运动估计算法

针对传统运动估计算法的缺点,本文提出了一种采用弧形、小十字、大菱形模板进行快速块匹配运动估计的新算法.该算法(NOADS)充分利用序列图像中运动矢量场中心偏置分布特性,使用小十字模板,进一步搜索根据情况自适应调整扩展为水平菱形或是垂直菱形模板,处理中心区域小运动矢量和静止运动矢量的搜索.使用大菱形-弧形模板处理大运动矢量的搜索.实验结果表明NOADS有效减少了搜索点数,提高了搜索速度,能同时适应于小运动块和大运动块的搜索,速度上比DS提高约20%,比3SS提高30% ～60%.     

一种SoC实现ABME的并行结构分析

自适应块大小运动估计(ABME)对于H.264/H.26L的高编码增益具有非常重要的作用,而其复杂的处理算法使其用于实时压缩编码受到很大的限制.本文提出一种在系统芯片(SoC)实现ABME的空间并行结构,其主要思想是将单个16(16宏块的匹配搜索分成并行16个4(4结构的处理单元,所有单元以相同步调同步搜索匹配块并计算每一步的SAD值,接着采用多个独立单元分别计算不同位置、不同数目的4(4子块所拼接成的块(16(8、8(16、8(8等等)对应的SAD及运动矢量,从而找出每种块结构所对应的最优匹配位置及匹配误差,编码器采用拉格朗日函数判据从中选择一种块结构作为编码时的运动估计单元.EDA软件仿真验证了本文算法的可行性及有效性.     

3DRS运动估计算法的FPGA实现

三维递归搜索(3-Dimension Recursive Search,3DRS)运动估计算法是帧率上变换(FRUC)处理系统的核心模块。基于3DRS算法采用双向运动估计的改进块匹配算法,在设计上使用块组的扫描处理方法大幅度减少系统的带宽开销,给出了系统硬件实现的架构和具体设计,并在FPGA上实现了3DRS的运动估计算法。验证结果表明该设计在FPGA上每秒钟可以处理60帧高清输入帧、15帧超高清输入帧。     

一种提高H.261编码性能的实现方法

研究表明采用最小均方误差或绝对误差准则的块匹配运动估值算法对H.261编码器来说不是最好的。本文提出了一种改进的块匹配运动估值算法。它所采用的准则不仅考虑了预测误差能量的大小,还考虑了运动矢量信息以及帧间预测误差的编码比特数目的多少.实验结果表明新的准则能够显著地改善H.261的编码性能。     

基于MPEG压缩域的运动对象检测方法

为了从MPEG压缩码流中准确的检测和提取运动对象,本文提出了一种时空域的运动对象检测算法。算法主要利用了MPEG码流中的运动矢量信息,首先对运动矢量进行时域平均和向量中值滤波的预处理,减少运动估计秒准确带来的运动矢量与实际对象运动带来的检测误差。然后建立时域上关于搜索块与参考块之间运动矢量夹角的概率模型,对于帧间预测宏块通过聂曼一皮尔迅准则进行运动判决。同时,对于P、B帧内的编码宏块,提出判决算法区分运动的帧内宏块和重现背景。实验证明,本文算法可以获得较为理想的检测效果。     

基于稠密矢量场及自适应补偿的帧率上变换

为了有效解决视频帧率上变换中物体边缘出现的模糊和块效应等问题,结合运动估计,优化了矢量化后处理和运动补偿算法.在基于块的运动估计中,结合运动的时空相关性优化块匹配算法,提高物体边缘运动矢量的准确性;通过基于像素块相关性的插值算法,获取像素矢量场,并保持物体结构完整性;在运动补偿时,结合矢量后处理的分类信息,自适应地进行加权插值计算,提高内插帧的质量.实验结果表明,与传统方法相比,该方法在主观和客观质量上都有较大的提升.     

基于Kalman预测的自适应De-interlace算法

本文提出一种基于Kalman预测的自适应De-interlace算法.它包括运动块检测、自适应的运动估计以及对运动块的运动补偿和对静止块的场复制等模块.其中,运动块检测用了连续的4场图像,能够更精确地实现运动检测;对检测到的运动块用Kalman滤波进行自适应地运动估计,并根据估计到的运动矢量进行运动补偿;对静止块,用场复制法进行De-interlace处理.该算法在de-interlace性能接近全搜索算法的前提下,运算量降低了三个数量级.     

基于运动连续性的遗帧率上变换算法

为了解决高清视频序列固有的运动模糊、残影等问题,同时提高低比特率通信的质量,提出了一种新的帧率上变换算法.该算法将遗传算法引入到运动估计中并结合现有运动估计算法进行了改进,使其充分利用视频在时间上和空间上的连续性,提高算法性能,同时减小算法的复杂度;对得到的运动矢量场进行了矢量细化处理,减小了块效应;并利用邻域运动矢量进行加权的重叠块运动补偿,提高内插块的精度.实验结果表明,与传统算法相比,该算法在主客观评估中都有较大的性能提升.     

H.264中快速运动估计算法及其架构

提出了一种新的可应用于H.264中的运动估计算法和架构.该算法改进多级顺序排除算法(MSEA),将不同模式的块分为相同数量的子块,去除流程分支使数据流规则而有利于硬件实现,使其适用于H.264的可变块大小与分数像素精度的运动补偿预测.实验证明,该算法在提高搜索效率的前提下仍能保持优良的性能.     

A VLSI architecture for variable block size video motion estimation

With the advent of new video standards such as MPEG-4 part-10 and H.264/H.26L, demands for advanced video coding, particularly in the area of variable block size video motion estimation (VBSME), are increasing. In this paper, we propose a new one-dimensional (1-D) very large-scale integration architecture for full-search VBSME (FSVBSME). The VBS sum of absolute differences (SAD) computation is performed by re-using the results of smaller sub-block computations. These are distributed and combined by incorporating a shuffling mechanism within each processing element. Whereas a conventional 1-D architecture can process only one motion vector (MV), this new architecture can process up to 41 MV sub-blocks (within a macroblock) in the same number of clock cycles.     

Parallelization of motion compensation algorithm based on reconfigurable video array processor

The new encoding tools of high efficiency video coding (HEVC) make the interpolation operation more complex in motion compensation (MC) for better video compression, but impose higher requirements on the computational efficiency and control logic of the hardware architecture. The reconfigurable array processor can take into consideration both the computational efficiency and flexible switching of algorithms very well. Through mining the data dependency and parallelism among interpolation operation, this paper presents a parallelization method based on the dynamic reconfigurable array processor proposed by the project team. The number of pixels loaded from the external memory is reduced significantly, by multiplexing the common data in the previous reference block and the current reference block. Flexible switching of variable block operation is realized by using dynamic reconfiguration mechanism. A 16 x 16 processor element (PE)'s array is used to dynamically process a 4 x 4 - 64 x 64 block size. The experimental results show that, the reference block update speed is increased by 39.9%. In the case of an array size of 16 PEs, the number of pixels processed in parallel reaches 16.     

A distributed adaptive block matching algorithm: Dis-ABMA

In the context of motion estimation for video sequences processing, variable block size algorithms, like the Adaptive Block Matching Algorithm (ABMA), have been proposed to match better “objects in motion” compared to the classical BMA. However, the variable block size grid derivation and the related motion estimation relies on a regularization process which implies heavy iterative and inter-dependent computations. Though the parallelization of the BMA is straightforward, the ABMA needs a deeper analysis before its implementation in a distributed environment: this is the goal of this paper. We first designed a modelization of the motion estimation of ABMA. This model can lead to several different distributed versions. A specific distributed model, with one master and several slaves, is then described. An implementation of this model has been realized and experimentations demonstrate a linear speedup with respect to the number of processors.     

Hardware Efficient Double Diamond Search Block Matching Algorithm for Fast Video Motion Estimation

Application of video in multimedia communication has become feasible due to efficient block matching algorithm (BMA) based motion estimation (ME) and motion compensation (MC) methods, that facilitate high data compression. To sustain visual quality of video, large amount of computation is involved in ME which can be reduced by fast search BMA and making fast search faster by various means like predicting initial search center (ISC) and early search termination. But more challenging work is to design an architecture which performs computation hungry search process in fewer clock cycles which will actually make fast search rapid for real time encoding. Implementations are available for matching multiple macroblocks in single clock cycle, but bottleneck is accessing macroblocks from memory while following sequential irregular search patterns of most of fast search algorithms. This paper proposes a novel, Hardware Efficient Double Diamond Search (HEDDS) algorithm which reaches far in search window more rapidly to identify best match and minimizes number of iterations of search pattern and hence diminish required clock cycles to read macroblocks from memory. From implementation perspective, HEDDS is up to 7.5 % to 33 % faster than existing BMAs and also offers reasonably good quality of encoding. With variable block size, HEDDS demonstrate average BD-PSNR improvement of 0.381, 0.088, 0.87 and 0.233 dB at BD-bitrate drop of 12.994 %, 2.499 %, 25.599 %, 6.887 % in comparison of HS, HMDS, LDPS and UMHS correspondingly. Proposed HEDDS architecture can process 259 HD frames per second in average case for fixed block size which is promising figure for real time encoding on devices having inadequate computational resources.     

A Low Cost Architecture for Variable Block Size Motion Estimation

Variable block size motion estimation is adopted in MPEG-4 AVC/H.264. This paper presents a new VLSI and FPGA architecture using full search block matching algorithm and online arithmetic. Several ways for data refreshing are described. There is not any increment in the number of clock cycles to process all sub-block formats. Only 54K gates are used, allowing to implement this architecture in devices with low hardware requirements. Moreover, low power consumption is obtained. A qualitative analysis of other designs is reported. Early termination of SAD calculation is analysed. Real-time video processing can be achieved for HDTV using early termination or increasing the parallelism.     

H.264标准半像素精度运动估计的硬件结构设计

设计了一种实时的基于可变块的半像素精度运动估计模块,包括半像素插值模块和半像素搜索模块,插值模块采用6阶FIR滤波器进行插值,搜索模块采用分级搜索算法.此模块应用在H.264标准便携视频设备的编码部分,用Verilog语言编写,采用Xilinx公司XC4VSX25的FPGA芯片作为硬件实现的运算核心.     

Bit-by-Bit Pipelined and Hybrid-Grained 2D Architecture for Motion Estimation of H.264/AVC

In H.264/AVC, the motion estimation (ME) routine supports variable block size and involves highly parallel sum of absolute difference (SAD) computations. In this study, we introduce a bit serial hybrid-grained processing element (PE) based 2D architecture that has both early termination and intensive data reuse capabilities. PEs operate on most significant bit-first arithmetic for early termination and the 2D architecture enables on-chip data reuse between neighboring PEs in a bit-by-bit pipelined fashion. Hybrid-grained PEs reduce the hardware overhead of conventional adder tree structures used for implementing the variable block size ME. Our design reduces the gate count by 7x compared to its ASIC counterpart, operates at a comparable frequency while sustaining 30 fps and 60 fps; and outperforms bit parallel and bit serial architectures in terms of throughput and performance per gate for various video formats.     

Towards an H.264/AVC HW/SW Integrated Solution: An Efficient VBSME Architecture

This paper presents an efficient real-time variable block size motion estimation architecture. The proposed architecture provides motion vectors for each 16 $times$ 16 block and its 40 sub-blocks. The proposed architecture is a single-instruction multiple-data architecture integrated with embedded SRAMs on one chip. The architecture has been prototyped using Xilinx Virtex-4 XC4VSX35-10 field-programmable gate array. It processes 30-CIF fps using 71-MHz clock frequency. Its maximum clock frequency is 187.7 MHz and the maximum throughput is 20 4CIF fps. The prototyped architecture has 175 k gates and 18 kbits embedded SRAM.      

Improved motion estimation time using a combination of dynamic reference frame selection and residue-based mode decision

Motion estimation using multiple reference frames is widely used as the basis for recent video coding standards (eg. H.264/AVC) to achieve increased coding efficiency. However, this increases the complexity of the encoding process. In this paper, a new technique for efficient motion estimation is proposed. A combination of multiple reference frame selection and image residue-based mode selection is used to improve motion estimation time. By dynamic selection of an initial reference frame in advance, the number of reference frames to be considered is reduced. In addition, from examination of the residue between the current block and reconstructed blocks in preceding frames, variable block size mode decisions are made. Modified initial motion vector estimation and early stop condition detection are also adopted to speed up the motion estimation procedure. Experimental results compare the performance of the proposed algorithm with a state of the art motion estimation algorithm and demonstrate significantly reduced motion estimation time while maintaining PSNR performance.