A low-power microcontroller having a 0.5-/spl mu/A standby current on-chip regulator with dual-reference scheme

We present a microcontroller having a 0.5-/spl mu/A standby current on-chip regulator. To break through the area overhead problem which a conventional regulator scheme suffers from to achieve small standby current, we propose a dual-reference scheme in which one voltage reference circuit is provided for active mode and another voltage reference circuit is provided for standby mode. For the voltage reference circuit for standby mode, a resistor-free circuit was used to achieve small current consumption without occupying large area. The microcontroller was fabricated in a 0.18-/spl mu/m CMOS process. The implementation and measurement results show that the dual-reference scheme achieves 0.5-/spl mu/A current consumption of the regulator in standby mode with 50% smaller area than the conventional scheme. The measured standby current of the whole chip was 2.0 /spl mu/A.     

A 23-ns 4-Mb CMOS SRAM with 0.2-μA standby current

A 4-Mb CMOS SRAM having 0.2-μA standby current at a supply voltage of 3 V has been developed. Current-mirror/PMOS cross-coupled cascade sense-amplifier circuits have achieved the fast address access time of 23 ns. A new noise-immune data-latch circuit has attained power-reduction characteristics at a low operating cycle time without access delay. A 0.5-μm CMOS, four-level poly, two-level metal technology with a polysilicon PMOS load memory cell, yielded a small cell area of 17 μm² and the very small standby current. A quadruple-array, word-decoder architecture allowed a small chip area of 122 mm²     

A 0.8-μm CMOS two-dimensional programmable mixed-signalfocal-plane array processor with on-chip binary imaging and instructionsstorage

This paper presents a CMOS chip for the parallel acquisition and concurrent analog processing of two-dimensional (2-D) binary images. Its processing function is determined by a reduced set of 19 analog coefficients whose values are programmable with 7-b accuracy. The internal programming signals are analog, but the external control interface is fully digital. On-chip nonlinear digital-to-analog converters (DAC's) map digitally coded weight values into analog control signals, using feedback to predistort their transfer characteristics in accordance to the response of the analog programming circuitry. This strategy cancels out the nonlinear dependence of the analog circuitry with the programming signal and reduces the influence of interchip technological parameters random fluctuations. The chip includes a small digital RAM memory to store eight sets of processing parameters in the periphery of the cell array and four 2-D binary images spatially distributed over the processing array. It also includes the necessary control circuitry to realize the stored instructions in any order and also to realize programmable logic operations among images. The chip architecture is based on the cellular neural/nonlinear network universal machine (CNN-UM). It has been fabricated in a 0.8-μm single-poly double-metal technology and features 2-μs operation speed (time required to process an image) and around 7-b accuracy in the analog processing operations     

A two-unit standby power plant with imperfect switching

The reliability and MTTF of a complex system consisting of two generators connected in standby redundancy are evaluated. The object of the system is to supply power generated by a generator from a power-house to critical consumers connected by imperfect cables and switches. The reliability and MTTF have been evaluated by Boolean function technique.     

An 18-μA standby current 1.8-V, 200-MHz microprocessor withself-substrate-biased data-retention mode

A low-standby-current 1.8-V, 200-MHz microprocessor has been fabricated with a 0.2-μm, five-metal, dual-oxide-thickness, CMOS technology and two power down modes (i.e., a standby mode and a data-retention mode). The microprocessor uses a switched substrate-impedance scheme to bias substrates in the standby mode while maintaining a 200-MHz operating speed. Data-retention capability during the standby mode is also maintained. This mode achieves 46.5-μA standby current. The microprocessor also offers a battery-backup capability in a self-substrate-biased data-retention mode. This makes it possible to apply a deep substrate bias without increasing the gate-induced drain leakage current or p-n junction current. The current consumption is only 17.8 μA when operating off a 1-V supply in the data-retention mode     

A 10-/spl mu/W standby power 256K CMOS SRAM

A 32K/spl times/8-bit CMOS static RAM using titanium polycide technology has been developed. The RAM has a standby power of 10 /spl mu/W, an active power of 175 mW, and an access time of 55 ns. The standby power has been achieved by an optimization of polysilicon resistors in a memory cell. A digit line circuit controlled by three internal clocks contributes to reduction of active power. The cell size has been reduced to 89.5 /spl mu/m/SUP 2/ by using both a buried isolation and a polycide GND line. Furthermore a simplified address-transition detection circuit and a single data bus configuration result in a small layout area, thus offering a 40.7 mm/SUP 2/ die size.     

A robust self-calibrating transmission scheme for on-chip networks

Systems-on-Chip (SoC) design involves several challenges, stemming from the extreme miniaturization of the physical features and from the large number of devices and wires on a chip. Since most SoCs are used within embedded systems, specific concerns are increasingly related to correct, reliable, and robust operation. We believe that in the future most SoCs will be assembled by using large-scale macro-cells and interconnected by means of on-chip networks. We examine some physical properties of on-chip interconnect busses, with the goal of achieving fast, reliable, and low-energy communication. These objectives are reached by dynamically scaling down the voltage swing, while ensuring data integrity-in spite of the decreased signal to noise ratio-by means of encoding and retransmission schemes. In particular, we describe a closed-loop voltage swing controller that samples the error retransmission rate to determine the operational voltage swing. We present a control policy which achieves our goals with minimal complexity; such simplicity is demonstrated by implementing the policy in a synthesizable controller. Such a controller is an embodiment of a self-calibrating circuit that compensates for significant manufacturing parameter deviations and environmental variations. Experimental results show that energy savings amount up to 42%, while at the same time meeting performance requirements.     

Statistical analysis of large on-chip power grid networks by variational reduction scheme

One of the most critical challenges in today's CMOS VLSI design is the lack of predictability in chip performance at design stage. One of the process variabilities comes from the voltage drop variations in on-chip power distribution networks. In this paper, we present a novel analysis approach for computing voltage drops of large power grid networks under process variations. The new algorithm is very efficient and scalable for huge networks with a large number of variational variables. This approach, called variational extended truncated balanced realization (varETBR), is based on model order reduction techniques to reduce the circuit matrices before the variational simulation. It performs the parameterized reduction on the original system using variation-bearing subspaces. After the reduction, Monte Carlo based statistical simulation is performed on the reduced system and the statistical responses of the original system are obtained thereafter. varETBR calculates variational response Grammians by Monte Carlo based numerical integration considering both system and input source variations in generating the projection subspace. varETBR is very scalable for the number of variables and flexible for different variational distributions and ranges as demonstrated in experimental results. Experimental results, on a number of IBM benchmark circuits up to 1.6 million nodes, show that the varETBR can be 1900X faster than the Monte Carlo method and is much more scalable than one of the recently proposed approaches.     

A new contactless smart card IC using an on-chip antenna and anasynchronous microcontroller

This paper describes a new generation of contactless smart card chip which integrates an on-chip coil connected to a power reception system and an emitter/receiver module compatible with the ISO 14443 standard, together with an asynchronous quasi-delay insensitive (QDI) 8-bit microcontroller. Beyond the contactless smart card application field, this new chip demonstrates that system-on-chip integrating power reception and management, radio-frequency communication, and signal processing is feasible. It associates analog/digital parts as well as synchronous/asynchronous logics and has been fabricated in a CMOS six metal layers 0.25-μm technology from STMicroelectronics     

A novel 4K static RAM with submilliwatt standby power

A 4K static RAM has been developed which uses NMOS technology to attain power dissipation levels comparable to those of CMOS 4K RAM's. Because NMOS technology is used for this part, it exhibits speed compatible with current NMOS microprocessors. The device is based on a self-refreshing dynamic memory cell with asynchronous on-chip refresh which is invisible to the user. This cell lays out in only 1400 µm²which allows a chip size of 5.2 mm × 2.9 mm. As is common with 4K CMOS static RAM's, a read or write cycle is initiated from the edge of a chip enable (CE) signal. The input buffer for this signal employs a novel design which dissipates power only during transitions. These circuits are described and experimental data on the performance of the RAM are given.     

Short-channel-effect-suppressed sub-0.1-μm grooved-gate MOSFET'swith W gate

Grooved-gate Si MOSFET's with tungsten gates are fabricated using conventional manufacturing technologies, and their short-channel-effect-free characteristics are verified down to a source and drain separation of around 0.1 μm. Phase shift lithography followed by a side-wall oxide film formation technique achieves a spacing of less than 0.2 μm between adjacent elevated polysilicons, subsequently resulting in a sub-0.1-μm source and drain separation in the substrate. Short-channel effects, such as threshold voltage roll-off and punchthrough, are found to be completely suppressed. From device simulations, the potential barrier formed at each grooved-gate corner is considered to be responsible for the suppression of the short-channel effects     

A 1.5-V-100-μW ΔΣ modulator with 12-b dynamic rangeusing the switched-opamp technique

The design and implementation of a very low supply voltage/low power ΔΣ modulator is presented. It is based on the switched-opamp technique, which allows low voltage operation with a standard process and without voltage multiplication. The design methodology is illustrated with a second-order single-loop ΔΣ modulator. The chip is implemented in a 0.7-μm CMOS process with standard threshold voltages. The power supply is 1.5 V and the power dissipation is only 100 μW. The measured dynamic range in the speech bandwidth of 300-3400 Hz is 12 b. The total harmonic distortion (THD) is lower than -72 dB     

A precision low-power PCM channel filter with on-chip power supply regulation

A single chip PCM channel filter with improved overall performance characteristics is described. The most important characteristics are power dissipation, idle channel noise, and power supply rejection. The filter described uses switched capacitor techniques and contains two fifth-order low-pass filters, a 50/60 Hz rejection filter, internal anti-alias filters, and a 600 ohm line driver. The filter is implemented in a two layer NMOS silicon gate technology. Experimental results are presented.     

A hybrid current/voltage mode on-chip signaling scheme with adaptive bandwidth capability

This brief describes an adaptive bandwidth bus architecture based on hybrid current/voltage mode repeaters for long global RC interconnect static busses that achieves high-data rates while minimizing the static power dissipation associated with current-mode (CM) signaling. An experimental adaptive bandwidth bus test chip fabricated in AMI 1.6-/spl mu/m Bulk CMOS indicates a reduction in power dissipation of approximately 62% over CM sensing and an increase in maximum data rate of 40% over voltage-mode signaling.     

A precise on-chip voltage generator for a gigascale DRAM with anegative word-line scheme

A precise on-chip voltage generator for gigascale DRAM's with a negative word-line scheme is described. It combines a charge-pump regulator and a series-pass regulator, and it also includes a positive and negative offset voltage generator that uses a bandgap generator with a differential amplifier. The proposed circuit was experimentally evaluated with a test device fabricated using a 0.3-μm process. The simulation results show that the series-pass regulator suppresses the noise on a word-line low voltage (negative) to below 30 mV for the word-line transient and V_BB bouncing. A dc-voltage error of less than 6% without trimming is confirmed for the positive and negative offset voltage generator through the test device. These results show that the described scheme can be used in future low-voltage gigascale DRAM's     

2.05-μm wavelength InGaAs-InGaAs distributed-feedbackmultiquantum-well lasers with 10-mW output power

Single-mode operation beyond 2.05-μm wavelength has been achieved in InGaAs-InGaAs distributed-feedback (DFB) laser with four quantum wells. The continuous-wave output power is 10.5 mW at a drive current of 200 mA and 25°C, The tuning range of the wavelength is between 2.051-2.056 μm with a temperature tuning rate of +0.125 nm/°C     

一种单片机控制的铅酸蓄电池充电电源

为了有效地提升铅酸蓄电池的使用寿命,同时实现对充电过程的监控,设计出一种用单片机控制的36 V铅酸蓄电池充电电源。本电路采用反激式拓扑,连续电流工作模式,电源管理IC设计在电源的副边,由ELAN公司的EM78P258N单片机模拟,是用可编程器件模拟电源管理IC,实现智能电源低成本化的一次成功尝试,通过对单片机的软件设计实现了充电电源的状态显示、充电时间控制、报警、过温保护、过压保护、过流保护等功能。本充电器真正的实现了铅酸蓄电池的三段式充电过程,其最高输出功率可达90 W,效率约85%,成本不到20元,具有很高的市场竞争力。     

A common-gate switched 0.9-W class-E power amplifier with 41% PAEin 0.25-μm CMOS

A power amplifier for wireless applications has been implemented in a standard 0.25-μm CMOS technology. The power amplifier employs class-E topology to exploit its soft-switching property for high efficiency. The finite dc-feed inductance in the class-E load network allows the load resistance to be larger for the same output power and supply voltage than that for an RF choke. The common-gate switching scheme increases the maximum allowable supply voltage by almost twice from the value for a simple switching scheme. By employing these design techniques, the power amplifier can deliver 0.9-W output power to 50-Ω load at 900 MHz with 41% power-added efficiency (PAE) from a 1.8-V supply without stressing the active devices     

A high-speed ultra-low power 64K CMOS EPROM with on-chip test functions

A 100 ns 8K /spl times/ 8 CMOS EPROM has been developed. Internal clock signals generated by address transition detection are used to reduce power consumption. As a result, power dissipation is less than 5 mW/MHz in the active mode, and less than 1 /spl mu/W in both the standby mode and the active quiescent mode (chip enabled, but no address transitions sensed). Three special test features incorporated in the design can be used to reduce the time required for final test and reliability screening.     

A 200 mW, 1 Msample/s, 16-b pipelined A/D converter with on-chip32-b microcontroller

This paper describes the design and implementation of a fully monolithic 16-b, 1 Msample/s, low-power A/D converter (ADC). An on-chip 32-b custom microcontroller calibrates and corrects the pipeline linearity to within 0.75 LSB integral nonlinearity (INL) and 0.6 LSB differential nonlinearity (DNL). High speed and low power are achieved using a pipelined architecture. Errors resulting from capacitor mismatches, finite op-amp open loop gain, charge injection and comparator offset are removed through self-calibration. Coefficients determined during calibration are stored on chip, digitally correcting the pipeline ADC in real time during normal conversion, Full-scale errors are removed through self-calibration and an-chip multiplication. Linearity errors due to capacitor voltage coefficients are reduced using a curve fit algorithm and on-chip ROM. Digital cross-talk errors resulting from the microcontroller running at a rate of ten times the analog sampling rate have prevented implementations of fully monolithic converters of this performance class in the past. Mismatches in cross-talk due to different digital timing between calibration and correction lead to linearity errors at critical correction points. Experimental analysis and circuit techniques which overcome these problems are presented