High frequency performance of Si/sub 1-x/Ge/sub x//Si/sub 1-y/Ge/sub y//Si/sub 1-x/Ge/sub x/ HBTs

The results of a theoretical study of the performance of high speed SiGe HBTs is presented. The study includes a group of SiGe HBTs in which the Ge concentration in the base is 20% higher than that in the emitter and collector (i.e. y=x+0.2). It is shown that the composition dependences of f/sub T/ and the F/sub max/ are non-monotonic. As the Ge composition in the emitter and collector layers is increased, f/sub T/ and f/sub max/ first decrease, then remain constant and finally increase to attain their highest values.<>     

Noise performance of Si/Si/sub 1-x/Ge/sub x/ FETs

Noise characteristics are evaluated for SiGe/Si based n-channel MODFETs and p-channel MOSFETs. The analysis is based on a self-consistent solution of Schrodinger and Poisson's equations. The model predicts a superior minimum noise figure for an n-channel MODFET at 77 K. P-channel MOSFETs behave similar to n-channel devices operating at 300 K. Minimum noise figure decreases with increasing quantum well (QW) width for both n- and p-channel devices. However, the p-channel devices are less sensitive to QW width variation. Minimum noise temperature behaves similarly. As observed, a range of doped epilayer thickness exists where minimum noise figure is a minimum for both n- and p-channel FETs.<>     

Study of nickel silicide contact on Si/Si/sub 1-x/Ge/sub x/

The properties of nickel silicide formed by depositing nickel on Si/p/sup +/-Si/sub 1-x/Ge/sub x/ layer are compared with that of nickel germanosilicide on p/sup +/-Si/sub 1-x/Ge/sub x/ layer formed by depositing Ni directly on p/sup +/-Si/sub 1-x/Ge/sub x/ layer without silicon consuming layer. After thermal annealing, nickel silicide on Si/p/sup +/-Si/sub 1-x/Ge/sub x/ layer shows lower sheet resistance and specific contact resistivity than that of nickel germanosilicide on p/sup +/-Si/sub 1-x/Ge/sub x/ layer. In addition, small junction leakage current is also observed for nickel silicide on a Si/p/sup +/-Si/sub 1-x/Ge/sub x//n-Si diode. In summary, with a Si consuming layer on top of the Si/sub 1-x/Ge/sub x/, the nickel silicide contact formed demonstrated improved electrical and materials characteristics as compared with the nickel germanosilicide contact which was formed directly on the Si/sub 1-x/Ge/sub x/ layer.     

Properties of Si/sub 3/N/sub 4//Si/sub x/Ge/sub 1-x/ metal-insulator-semiconductor capacitors

The density of fast interface states was studied in Si/sub 3/N/sub 4//Si/sub 0.8/Ge/sub 0.2/ metal-insulator-semiconductor (MIS) capacitors. The interface state density does not appear to be strongly affected by the presence of a thin Si interlayer between the nitride and SiGe alloy. This is in contrast to the results when SiO/sub 2/ is used as the insulator material in similar structures.<>     

Waveguided electro-optical intensity modulation in a Si/Ge/sub x/Si/sub 1-x//Si heterojunction bipolar transistor

Optical phase-and-amplitude modulation at 1.55 mu m in an electro-optic guided-wave Si/Ge/sub 0.2/Si/sub 0.8//Si HBT is investigated using computer-aided modelling and simulation. At an injection of 10/sup 19/ electrons per cm/sup 3/, an intensity modulation of 10 dB is predicted for an active length of 390 mu m.<>     

Double heterojunction bipolar transistor in Al/sub x/Ga/sub 1-x/As/GaAs/sub 1-y/Sb/sub y/ system

Double heterojunction bipolar transistors based on the Al/sub x/Ga/sub 1-x/As/GaAs/sub 1-y/Sb/sub y/ system are examined. The base layer consists of narrow band gap GaAs/sub 1-y/Sb/sub y/ and the emitter and collector consist of wider band gap Al/sub x/Ga/sub 1-x/As. Preliminary experimental results show that AlGaAs/GaAsSb/GaAs DHBTs exhibit a current gain of five and a maximum collector current density of 5*10/sup 4/ A/cm/sup 2/.<>     

Effect on ion implanted germanium profile on the characteristics of Si/sub 1-x/Ge/sub x//Si heterojunction bipolar transistors

An optimum profile for Ge ion implantation in SiGe/Si heterojunction bipolar transistors is determined by using a two-dimensional simulator code for advanced semiconductor devices. The simulation code is based on a two-dimensional drift-diffusion model for heterostructure degenerate semiconductors with nonparabolicity included in the energy band structure. The model allows accurate simulations of carrier transport in short base devices. The simulation results indicate that for high current gain the Ge profile maximum must be close to the base-collector junction, and that the unavoidable tail of the implanted germanium in the collector region does not deteriorate the gain.<>     

Turn-on voltage investigation of GaAs-based bipolar transistors with Ga/sub 1-x/In/sub x/As/sub 1-y/N/sub y/ base layers

The fundamental lower limit on the turn on voltage of GaAs-based bipolar transistors is first established, then reduced with the use of a novel low energy-gap base material, Ga/sub 1-x/In/sub x/As/sub 1-y/N/sub y/. InGaP/GaInAsN DHBTs (x/spl sim/3y/spl sim/0.01) with high p-type doping levels (/spl sim/3/spl times/10/sup 19/ cm/sup -3/) and dc current gain (/spl beta//sub max//spl sim/68 at 234 /spl Omega///spl square/) are demonstrated. A reduction in the turn-on voltage over a wide range of practical base sheet resistance values (100 to 400 /spl Omega///spl square/) is established relative to both GaAs BJTs and conventional InGaP/GaAs HBTs with optimized base-emitter interfaces-over 25 mV in heavily doped, high dc current gain samples. The potential to engineer turn-on voltages comparable to Si- or InP-based bipolar devices on a GaAs platform is enabled by the use of lattice matched Ga/sub 1-x/In/sub x/As/sub 1-y/N/sub y/ alloys, which can simultaneously reduce the energy-gap and balance the lattice constant of the base layer when x/spl sim/3y.     

On the threshold Voltage of strained-Si-Si/sub 1-x/Ge/sub x/ MOSFETs

The threshold voltage shifts (/spl Delta/V/sub t(SS)/ relative to V/sub t/ of Si-control devices) in strained-Si-Si/sub 1-x/Ge/sub x/ (SS) CMOS devices are carefully examined in terms of the shifted two-dimensional energy subbands and the modified effective conduction- and valance-band densities of states. Increased electron affinity as well as bandgap narrowing in the SS layer are shown to be the predominant components of /spl Delta/V/sub t(SS)/, whereas the density-of-state terms tend to be relatively small but not insignificant. The study reveals, for both n-channel and p-channel SS MOSFETs, important physical insights on the varied surface potential at threshold, defined by energy quantization as well as the strain, and on the shifted flat-band voltage that is also part of /spl Delta/V/sub t(SS)/. Models for /spl Delta/V/sub t(SS)/ dependent on the Ge content (x), with comparisons to published data, are presented and used to show that redesign of channel doping in the SS nMOSFET to increase the significantly reduced V/sub tn(SS)/ for off-state current control tends to substantively diminish the inherent SS CMOS relative speed enhancement, e.g., by more than 40% for x=0.20. Interestingly, the SS pMOSFET model predicts small increases in the magnitude of V/sub tp(SS)/.     

Very-low-threshold, strained In/sub y/Ga/sub 1-y/As-GaAs quantum-well lasers defined by impurity-induced disordering

Strained In/sub y/Ga/sub 1-y/As-GaAs quantum-well (InGaAs-QW) stripe geometry lasers ( lambda approximately 9050 AA) were fabricated by impurity-induced disordering (IID) through self-aligned Si-Zn diffusion. Lasers exhibit very low threshold (I/sub th/=3.0 mA at room-temperature continuous operation) and good uniformity (>90% with I/sub th/<8 mA, >70% with I/sub th/=4+or-1 mA). The moderate blue shift of the lasing wavelength (250 A or 40 meV) suggests that the strained InGaAs-QW active layer can survive long-time high-temperature thermal annealing (850 degrees C, 8 h) required for Si diffusion.<>     

Effect of different type intermediate layers on band structure and gain of Ga/sub 1-x/In/sub x/N/sub y/As/sub 1-y/-GaAs quantum well lasers

Based on the band-anticrossing model, the effect of the strain-compensated layer and the strain-mediated layer on the band structure, the gain, and the differential gain of GaInNAs-GaAs quantum well lasers have been investigated. Different band-filling mechanisms have been illustrated. Compared to the GaInNAs-GaAs single quantum well with the same wavelength, the introduction of the strain-compensated layer and the strain-mediated layer increases the transparency carrier density. However, these multilayer structures help to suppress the degradation of the differential gain.     

Scalability of the Si/sub 1-x/Ge/sub x/ source/drain technology for the 45-nm technology node and beyond

The authors present a study on the layout dependence of the silicon-germanium source/drain (Si/sub 1-x/Ge/sub x/ S/D) technology. Experimental results on Si/sub 1-x/Ge/sub x/ S/D transistors with various active-area sizes and polylengths are combined with stress simulations. Two technologically important configurations are investigated: the nested transistor, where a polygate is surrounded by other gates, and isolated transistors, where the active area is completely surrounded by isolation oxide. The channel stress, caused by epitaxial Si/sub 1-x/Ge/sub x/ is reduced substantially when the active area is decreased from a large size towards typical values for advanced CMOS technology nodes. Nested transistors with longer gate lengths are more sensitive towards layout scaling than shorter gates. Increasing recess depth and germanium concentration gives larger channel stress, but does not change layout sensitivity. Increased lateral etching leads to higher stress, as well as to reduced layout sensitivity. In small-size transistors, there exists an optimal recess depth, beyond which the stress in the channel will not increase further. For isolated transistor structures, the interaction between Si/sub 1-x/Ge/sub x/ and the isolating oxide can even lead to stress reduction when the recess depth is increased. When technology advances, active-area dimensions will be scaled together with gate lengths and widths. For typical sizes of advanced silicon CMOS Si/sub 1-x/Ge/sub x/ S/D transistors, simulations indicate that the channel stress can be maintained in future technology nodes.     

Characteristics of In/sub x/Al/sub 1-x/N-GaN high-electron mobility field-effect transistor

GaN-based field effect transistors commonly include an Al/sub x/Ga/sub 1-x/N barrier layer for confinement of a two-dimensional electron gas (2DEG) in the barrier/GaN interface. Some of the limitations of the Al/sub x/Ga/sub 1-x/N-GaN heterostructure can be, in principle, avoided by the use of In/sub x/Al/sub 1-x/N as an alternative barrier, which adds flexibility to the engineering of the polarization-induced charges by using tensile or compressive strain through varying the value of x. Here, the implementation and electrical characterization of an In/sub x/Al/sub 1-x/-GaN high electron mobility transistor with Indium content ranging from x=0.04 to x=0.15 is described. The measured 2DEG carrier concentration in the In/sub 0.04/Al/sub 0.96/N-GaN heterostructure reach 4/spl times/10/sup 13/ cm/sup -2/ at room temperature, and Hall mobility is 480 and 750 cm/sup 2//V /spl middot/ s at 300 and 10 K, respectively. The increase of Indium content in the barrier results in a shift of the transistor threshold voltage and of the peak transconductance toward positive gate values, as well as a decrease in the drain current. This is consistent with the reduction in polarization difference between GaN and In/sub x/Al/sub 1-x/N. Devices with a gate length of 0.7 /spl mu/m exhibit f/sub t/ and f/sub max/ values of 13 and 11 GHz, respectively.     

High-performance self-aligned SiGeC HBT with selectively grown Si/sub 1-x-y/Ge/sub x/C/sub y/ base by UHV/CVD

Si/sub 1-x-y/Ge/sub x/C/sub y/ selective epitaxial growth (SEG) was performed by cold-wall, ultrahigh-vacuum chemical vapor deposition, and the effects of incorporating C on the crystallinity of Si/sub 1-x-y/Ge/sub x/C/sub y/ layers and the performance of a self-aligned SiGeC heterojunction bipolar transistor (HBT) were evaluated. A Si/sub 1-x-y/Ge/sub x/C/sub y/ layer with good crystallinity was obtained by optimizing the growth conditions. Device performance was significantly improved by incorporating C, as a result of applying Si/sub 1-x-y/Ge/sub x/C/sub y/ SEG to form the base of a self-aligned HBT. Fluctuations in device performance were suppressed by alleviating the lattice strain. Furthermore, since the B out diffusion could be suppressed by incorporating C, the cutoff frequency was able to be increased with almost the same base resistance. A maximum oscillation frequency of 174 GHz and an emitter coupled logic gate-delay time of 5.65 ps were obtained at a C content of 0.4%, which shows promise for future ultrahigh-speed communication systems.     

A novel dynamic threshold Voltage MOSFET (DTMOS) using heterostructure channel of Si/sub 1-y/C/sub y/ interlayer

We have demonstrated the fabrication of dynamic threshold voltage MOSFET (DTMOS) using the Si/sub 1-y/C/sub y/(y=0.005) incorporation interlayer channel. Compare to conventional Si-DTMOS, the introduction of the Si/sub 1-y/C/sub y/ interlayer for this device is realized by super-steep-retrograde (SSR) channel profiles due to the retardation of boron diffusion. A low surface channel impurity with heavily doped substrate can be achieved simultaneously. This novel Si/sub 1-y/C/sub y/ channel heterostructure MOSFET exhibits higher transconductance and turn on current.     

Theoretical investigation of excitonic gain in ZnO--Mg/sub x/Zn/sub 1-x/O strained quantum wells

Free-excitonic gain of wurtzite ZnO--Mg/sub x/Zn/sub 1-x/O quantum wells(QWs) is studied theoretically. The valence band structure of ZnO--Mg/sub x/Zn/sub 1-x/O QWs with the consideration of biaxial strain and exciton-phonon interaction is calculated based on a 6/spl times/6 Hamiltonian. From the available experimental data, the band offset ratio and conduction band deformation potential of ZnO--Mg/sub x/Zn/sub 1-x/O QWs are found to be 60/40 and -6.8eV, respectively. The influence of biaxial strain on the peak free-excitonic gain of ZnO--Mg/sub x/Zn/sub 1-x/O QWs for various well-width and mole fraction of Mg is also investigated.     

The study of relaxation in asymmetrically strained Si1−x Ge x Si superlattices

Asymmetrically strained Si/SiGe superlattices consisting of 12 nm Si/4 nm Si_0.65Ge_0.35 have been grown in Si(001) by molecular beam epitaxy (MBE) and studied as a function of thermal treatments. Results indicate that initially, the interdiffusion is very rapid and non-linear, and at later annealing stages a steady-state interdiffusion is attained. Raman spectroscopy has been used to determine the Ge content and the strain independently, and to show that in the very early annealing stages, strain relaxation occurs predominantly by interdiffusion. This is supported by transmission electron microscopy (TEM) which indicates that less than 10% of the initial strain relaxation is caused by dislocation formation. In addition, a low temperature relaxation has been observed which may be related to misoriented SiGe crystallites at the superlattice/substrate interface, and increased in size with annealing at 631‡ C.     

Investigations of high-performance GaAs solar cells grown on Ge-Si/sub 1-x/Ge/sub x/-Si substrates

High-performance p/sup +//n GaAs solar cells were grown and processed on compositionally graded Ge-Si/sub 1-x/Ge/sub x/-Si (SiGe) substrates. Total area efficiencies of 18.1% under the AM1.5-G spectrum were measured for 0.0444 cm/sup 2/ solar cells. This high efficiency is attributed to the very high open-circuit voltages (980 mV (AM0) and 973 mV (AM1.5-G)) that were achieved by the reduction in threading dislocation density enabled by the SiGe buffers, and thus reduced carrier recombination losses. This is the highest independently confirmed efficiency and open-circuit voltage for a GaAs solar cell grown on a Si-based substrate to date. Larger area solar cells were also studied in order to examine the impact of device area on GaAs-on-SiGe solar cell performance; we found that an increase in device area from 0.36 to 4.0 cm/sup 2/ did not degrade the measured performance characteristics for cells processed on identical substrates. Moreover, the device performance uniformity for large area heteroepitaxial cells is consistent with that of homoepitaxial cells; thus, device growth and processing on SiGe substrates did not introduce added performance variations. These results demonstrate that using SiGe interlayers to produce "virtual" Ge substrates may provide a robust method for scaleable integration of high performance III-V photovoltaics devices with large area Si wafers.     

Strain interactions between dislocation arrays in epitaxial Si x Ge1-x /Si heterostructures

Lattice disregistry that exists in epitaxial overgrowths is often accommodated by interfacial dislocation arrays. The transition between strain accommodation by uniform interfacial shear and by interfacial dislocations is fairly sharp and thought to be controlled by energy minimization considerations. In this paper we demonstrate an extension of the Frank-van der Merwe approach by incorporating the continuum methodology of Eshelby to the analysis of strain interactions between arrays of interfacial dislocations in a bi-layered epitaxial film. Numerical examples are given for a Si/Si _x Ge_1-x /Si heterostructure. The importance of such an analysis to the study of defect propagation through strained layer superlattices is briefly discussed.