Neuron MOS binary-logic integrated circuits. I. Design fundamentalsand soft-hardware-logic circuit implementation

Described are the fundamental design principles for binary-logic circuits using a highly functional device called the neuron MOS transistor (νMOS), a single MOS transistor simulating the function of biological neurons. To facilitate logic design employing this transistor, a graphical technique called the floating-gate potential diagram has been developed. It is shown that any Boolean functions can be generated using a common circuit configuration of two-stage νMOS inverters. One of the most striking features of νMOS binary-logic application is the realization of a so-called soft hardware logic circuit. The circuit can be made to represent any logic function (AND, OR, NAND, NOR, exclusive-NOR, exclusive-OR, etc.) by adjusting external control signals without any modifications in its hardware configuration. The circuit allows real-time reconfigurable systems to be built. Test circuits were fabricated by a double-polysilicon CMOS process and their operation was experimentally verified     

CMOS logic elements with increased failure resistance to single-event upsets

Two-phase submicron CMOS logic elements with a design standard of 0.18 μm are analyzed that are based on two symmetric signal transfer and conversion logical channels (phases). The basic elements of two-phase CMOS logic are 2- and 4-transistor CMOS converters that form two-phase inverters, NAND elements, and D and RS triggers. Two-phase CMOS inverters based on 2-transistor converters with transversely connected inputs and elements based on these inverters, NAND elements and D and RS triggers also with transversely connected constituent elements, are the best ones with respect to the set of parameters, including the failure resistance to single-event upsets (with respect to the value of the critical switching charge), size, and switching time. The values of the critical switching charges of the elements of two-phase CMOS logic under exposure to individual nuclear particles that induce ionization currents with fall-time constants (diffusion component) from 0.3 ns to 2.0 ns are determined.     

Impact of three-dimensional transistor on the pattern area reduction for ULSI

The impact of three-dimensional transistors, double-gate transistor, trench-isolated transistor (TIS) (using sidewall gate)/FinFET, and surrounding gate transistor (SGT) on the pattern area reduction for ultra-large-scale integration (ULSI) has been described. The pattern area of the gate logic, such as NAND or NOR, with the double-gate transistor, TIS/FinFET or SGT can be reduced to 58, 47, 48%, respectively, compared with the conventional planar case using the same feature size, F. The pattern area of the tapered buffer circuit with the double-gate transistor, TIS/FinFET or SGT can be reduced to 58, 20, 48%, respectively. These three-dimensional transistors can be adapted to ULSI such as application specific integrated circuit (ASIC), microprocessor (MPU), dynamic random access memory (DRAM), and embedded DRAM. The smallest pattern area may be realized with TIS/FinFET or SGT of 47-48% for ASIC, with TIS/FinFET of 42% for MPU, with SGT of 65% for DRAM and with TIS/FinFET or SGT for embedded DRAM. For designing the circuit with TIS/FinFET the design of the trench depth (2F for gate logic, 12F for tapered buffer) is the key issue. The design of the cell library for SGT is a task for the future.     

CMOS logic circuit optimum design for radiation tolerance

CMOS logic circuit optimum design for radiation tolerance has been investigated, based on NMOS and PMOS transistor parameter shift data due to radiation effects. The DC noise immunity for the three-input NAND has been found to be 36% greater than for the three-input NOR. The gate area for the optimised NAND is about three times smaller than that for the optimised NOR.     

Dual material gate silicon on insulator junctionless MOSFET for low power mixed signal circuits

In this research paper, demonstrates, the logic performance of n and p channel complementary metal oxide semiconductor (CMOS) circuits implemented with dual material gate silicon on insulator junctionless transistor (DMG SOI JLT). The logic performance of a CMOS circuit is evaluated in terms of static power dissipation, voltage transfer characteristic, propagation delay and noise margin. The gate capacitance is less as compared to gate capacitance of DMG SOI transistor in saturation. The power dissipation for CMOS inverter of DMG SOI JLT is improved by 25% as compared to DMG SOI transistor. The DMG SOI JLT common source amplifier has 1.25 times amplification as that of DMG SOI transistor. The noise margin of DMG SOI JLT CMOS inverter is improved by 23% as compared to the DMG SOI transistor CMOS inverter. The NAND gate static power dissipation of DMG SOI JLT is found improved imperically as compared to DMG SOI transistor for various channel length. The improvement obtained is 53% for 20nm, 46% for 30nm and 34% for 40nm respectively. Static power dissipation of DMG SOI JLT inverter is reduced by 3% as compared to junction transistor inverter at channel length of 30nm.     

Design of an FPGA Logic Element for Implementing Asynchronous NULL Convention Logic Circuits

Two versions of a reconfigurable logic element are developed for use in constructing afield-programmable gate array NULL convention logic (NCL) field-programmable gate array (FPGA): one with extra embedded registration capability, which requires additional area, and one without. Both versions can be configured as any of the 27 fundamental NCL gates, including resettable and inverting variations, and both can utilize embedded registration for gates with three or fewer inputs; however, only the version with the additional embedded registration capability can utilize embedded registration with four-input gates. These two approaches are compared with each other and with an existing approach, showing that both versions developed herein yield a more area efficient NCL circuit implementation, compared to the previous work. The two FPGA logic elements are simulated at the transistor level using the 1.8-V, 180-nm TSMC CMOS process.     

A flexible logic circuit based on a MOS-NDR transistor in standard CMOS technology

A MOS-NDR (negative differential resistance) transistor which is composed of four n-channel metaloxide-semiconductor field effect transistors (nMOSFETs) is fabricated in standard 0.35 μm CMOS technology.This device exhibits NDR similar to conventional NDR devices such as the compound material based RTD (resonant tunneling diode) in current-voltage characteristics.At the same time it can realize a modulation effect by the third terminal.Based on the MOS-NDR transistor,a flexible logic circuit is realized in this work,which can transfer from the NAND gate to the NOR gate by suitably changing the threshold voltage of the MOS-NDR transistor.It turns out that MOSNDR based circuits have the advantages of improved circuit compaction and reduced process complexity due to using the standard IC design and fabrication procedure.     

Three-dimensional CMOS IC's Fabricated by using beam recrystallization

A three-dimensional (3-D) CMOS integrated circuit with a structure, in which one type of transistor is fabricated directly above a transistor of the opposite type with separate gates and an insulator in between, has successfully been fabricated by using laser beam recrystallization. Seven-stage ring oscillators fabricated in the 3-D structure have a propagation delay of 8.2 ns. In the present experiment, a double-layer of silicon-nitride and phospho-silicate-glass (PSG) film has been used as an intermediate insulating layer between the top and the bottom devices. This CMOS structure and the process technology we have developed here can be the basis for realizing a multilayered 3-D device composed of vertically stacked transistors with separate gates and an insulating layer in between.     

Simulation of the local effect of nuclear particles on 65-nm CMOS elements of two-phase logics

The influence of capacitive couplings of the buses connecting differential parts of two-phase CMOS logic elements with a 65-nm design rule on the failure sensitivity of elements due to the effect of separate nuclear particles is simulated. The sensitivity characteristics of two-phase inverters, NAND elements, trigger cells, and controlling elements of RS and D triggers is determined. The effects of the separate nuclear particle were simulated by current pulses with the rise time constant of 10 ps and fall time constants of 30 ps and 300 ps. The admissible values of capacitances of inputs of differential parts of two-phase CMOS logic elements of 0.3...0.7 fF are established depending on the element type and its logic state. The critical charges for two-phase logic elements are 32?C88 fC, which is better by a factor of 10?C15 than for elements with the conventional CMOS circuit technology with the same 65-nm design rule.     

A three-dimensional CMOS design methodology

A technology-updatable design methodology for three-dimensional (3-D) CMOS circuits has been developed. Four levels of abstraction have been implemented with topographical congruence: 1) technology level, 2) mask level, 3) transistor level, and 4) logic level. A novel transistor level symbolic representation is introduced which emphasizes the three-dimensional nature of the circuits. A number of design examples is presented.     

Design of Diode Type Un-Cooled Infrared Focal Plane Array Readout Circuit

The diode infrared focal plane array uses the silicon diodes as a sensitive device for infrared signal measurement. By the infrared radiation, the infrared focal plane can produces small voltage signals. For the traditional readout circuit structures are designed to process current signals, they cannot be applied to it. In this paper,a new readout circuit for the diode un-cooled infrared focal plane array is developed. The principle of detector array signal readout and small signal amplification is given in detail. The readout circuit is designed and simulated by using the Central Semiconductor Manufacturing Corporation (CSMC) 0.5 μm complementary metal-oxide-semiconductor transistor (CMOS) technology library. Cadence Spectre simulation results show that the scheme can be applied to the CMOS readout integrated circuit (ROIC) with a larger array, such as 320×240 size array.     

Placement algorithm for the optimal synthesized design of CMOS logic cells

A systematic placement algorithm is described for the design of CMOS logic cells. Unlike the other placement algorithms that apply only to NAND/NOR circuits or that are very time consuming, the proposed algorithm applies to any kind of CMOS circuit, and has no restriction as to the NAND/NOR circuits. Furthercmore, it applies to both planar and non-planar circuits. In addition, since a very efficient graph-theoretic approach is used as a constructive algorithm which generates a near optimal initial placement combined with an iterative approach by simulated annealing, an optimum result can be obtained in less time. The layout style of a transistor chain is used which, in conjunction with the optimal synthesized design approach using switching network logic, constitutes a systematic method for the design automation of high-speed VLSI circuits.     

CMOS Majority Element Based on NAND Logic with Reduced Sensitivity to Single Ionizing Particles

Russian Microelectronics - The results of modeling the elements of a triple majority gate based on the CMOS NAND logic elements are presented. Modeling is carried out using the 3D TCAD of physical...     

Technology mapping for high-performance static CMOS and passtransistor logic designs

Two new techniques for mapping circuits are proposed in this paper. The first method, called the odd-level transistor replacement (OTR) method, has a goal that is similar to that of technology mapping, but without the restriction of a fixed library size and maps a circuit to a virtual library of complex static CMOS gates. The second technique, the static CMOS/pass transistor logic (PTL) method, uses a mix of static CMOS and PTL to realize the circuit and utilizes the relation between PTL and binary decision diagrams. The methods are very efficient and can handle all of the ISCAS'85 benchmark circuits in minutes. A comparison of the results with traditional technology mapping using SIS on different libraries shows an average delay reduction above 18% for OTR, and an average delay reduction above 35% for the static CMOS/PTL method, with significant savings in the area     

SET logic driving capability and its enhancement in 3-D integrated SET–CMOS circuit

The driving capability of a single-electron transistor (SET) circuit is sensitive to the load and interconnects. We discuss about improving the performance of a SET logic in hybrid SET–CMOS circuit by parameter variation and circuit architecture along with its simulation results. With an intention of studying the SET logic drivability in a SET-only circuit, we examined a circuit composed of 2¹³ SET inverters with its interconnect effect in a 3-D CMOS IC. The schematic of the simulation is based on fabrication model of this large circuit along with interlayer and coupling capacitances of its metallization. The simulation results for delay, bandwidth and power validate the efficiency of a SET circuit.     

Parallel Adder Design with Reduced Circuit Complexity Using Resonant Tunneling Transistors and Threshold Logic

Quantum-effect devices utilizing resonant tunneling are promising candidates for future nano-scale integration. Originating from the technological progress of semiconductor technology, circuit architectures with reduced complexity are investigated by exploiting the negative-differential resistance of resonant tunneling devices. In this paper a resonant tunneling device threshold logic family based on the Monostable-Bistable Transition Logic Element (MOBILE) is proposed and applied to different parallel adder designs, such as ripple carry and binary carry lookahead adders. The basic device is a resonant tunneling transistor (RTT) composed of a resonant tunneling diode monolithically integrated on the drain contact layer of a heterostructure field effect transistor. On the circuit level the key components are a programmable NAND/NOR logic gate, threshold logic gates, and parallel counters. The special properties of MOBILE logic gates are considered by a bit-level pipelined circuit style. Experimental results are presented for the NAND/NOR logic gate.     

CMOS NAND and NOR Schmitt circuits

Original solutions of m-input NAND and NOR logic circuits with hysteresis in the transfer characteristics are proposed. Multiple inputs are done similarly to standard NAND and NOR logic circuits. The logic circuits proposed in this paper consist of 2m + 1 paris of enhancement CMOS transistors. The hysteresis voltage depends on supply voltage and transistor geometry. The proposed solutions always guarantee hysteresis, even with very large process variations. The noise immunity is typically greater than 50% of supply voltage. Analysis using simple device models together with computer simulations and experimental results is given.     

Top-down pass-transistor logic design

The pass-transistor based cell library and synthesis tool are constructed, for the first time, to clarify the potential of top-down pass-transistor logic. The entire scheme is called LEAP (Lean Integration with Pass-Transistors). The feature of a pass-transistor based cell is its multiplexer function and the open-drain structure. This cell has the flexibility of transistor level circuit design and compatibility with conventional cell based design. An extremely simple cell library with only seven cells combined with a synthesis tool called “circuit inventor” is compared with the conventional CMOS library that has over 60 cells combined with the state-of-the-art logic synthesis. The results show that the area, delay, and power dissipation are improved by LEAP and that the value-cost ratio is improved by a factor of three. This demonstrates that LEAP has the potential to achieve a quantum leap in value of LSI's while reducing the cost. Key issues which have to be cleared before pass transistor logic is used as the generic logic scheme replacing CMOS are also discussed     

A gallium arsenide SDFL gate array with on-chip RAM

A GaAs gate array has been fabricated featuring 432 SDFL cells, 32 interface I/O buffer cells, and four 4 × 4 bit static RAM's. Each Schottky diode field-effect transistor logic (SDFL) cell can be programmed with 3 options as an unbuffered or buffered NOR gate, or as a dual OR/NAND gate. The interface I/O cell can be programmed for ECL, TTL, CMOS, and SDFL logic families. Each 16 bit RAM is fully decoded using depletion mode MESFET's with SDFL circuit approach. The chip size is 147 mils × 185 mils, and the total power dissipation of the whole chip is less than 3 W. Testing of the cell array has given yields of 70 percent for the 101-stage ring oscillators and about 90 percent for the I/O buffers, memory cells, and 25-stage ring oscillators in a wafer. The best speed performance of the unbuffered SDFL gate is 150 ps for fan-out and fan-in of 1 and the load of 100 µm of interconnect. The average power of the SDFL gate is 1.5 mW. The results demonstrated the feasibility of the GaAs SDFL for fast gate array and memory applications.     

基于组合逻辑电路实现方法的探究

为缩短理论与实践的距离,提高灵活应用数字元器件的能力,提出了组合逻辑电路设计的第五步.组合逻辑电路设计通常有四步,设计完成画出符合功能要求的逻辑图,一般是把其转换成TrL与非门形式的逻辑图.第五步研究用多少个、何种逻辑门、译码器、数据选择器,怎样实现组合逻辑电路.实践证明,只要把逻辑电路与选择实现功能器件相互对应输入输...