Low-voltage low-power superior-order curvature-corrected voltage reference

A new superior-order curvature-corrected voltage reference will be presented. In order to improve the temperature behavior of the circuit, a double differential structure will be used, implementing the linear and the superior-order curvature corrections. An original ComplemenTary with Absolute Temperature voltage generator will be proposed, using exclusively MOS transistors biased in weak inversion for a low power operation of the voltage reference, having two great advantages: an important reducing of the circuit silicon area and an improved accuracy (matched resistors being replaced by matched MOS active devices). The superior-order curvature-correction will be implemented by taking the difference between two gate-source voltages of subthreshold-operated MOS transistors, biased at drain currents having different temperature dependencies: PTAT (ProporTional with Absolute Temperature) and square PTAT. In order to obtain a low-voltage operation of the circuit, the classical MOS transistor, which implements the elementary voltage reference, could be replaced by a Dynamic Threshold MOS transistor. The SPICE simulations confirm the theoretical estimated results, showing a temperature coefficient under 6 ppm/K for an extended input range 223 K < T < 333 K and for a supply voltage of 1.8 V and a current consumption of about 1 μA.     

MOS voltage reference based on polysilicon gate work function difference

A voltage reference in CMOS technology is based upon transistor pairs of the same type except for the opposite doping type of their polysilicon gates. At identical drain currents, the gate voltage difference, close to the silicon bandgap, is 1.2 V/spl plusmn/0.06 V. Circuits for a positive and for a negative voltage reference are presented. Digital voltage tuning improves accuracy. Temperature compensation is provided by proper choice of current ratio or by means of an auxiliary circuit. Voltage drift is about 300 ppm//spl deg/C without compensation, and can be reduced to /spl plusmn/30 ppm//spl deg/C. The circuits work with a supply voltage of 2-10 V and draw a current that is less than 1 /spl mu/A.     

CMOS voltage reference based on threshold voltage and thermal voltage

A fully CMOS based voltage reference circuit is presented in this paper. The voltage reference circuit uses the difference between gate-to-source voltages of two MOSFETs operating in the weak-inversion region to generate the voltage with positive temperature coefficient. The reference voltage can be obtained by combining this voltage difference and the extracted threshold voltage of a saturated MOSFET which has a negative temperature coefficient. This circuit, implemented in a standard 0.35-μm CMOS process, provides a nominal reference voltage of 1.361 V at 2-V supply voltage. Experimental results show that the temperature coefficient is 36.7 ppm/°C in the range from −20 to 100°C. It occupies 0.039 mm² of active area and dissipates 82 μW at room temperature. With a 0.5-μF load capacitor, the measured noise density at 100 Hz and 100 kHz is 3.6 and 2 5 \textnV/?{\textHz} , 2 5\,{\text{nV}}/\sqrt {\text{Hz}} , respectively.     

A temperature-stabilized SOI voltage reference based on thresholdvoltage difference between enhancement and depletion NMOSFET's

A temperature-stabilized silicon-on-insulator (SOI) voltage reference is presented. It is based on the threshold voltage difference between enhancement and depletion SOI NMOSFETs that have the same channel doping concentration but of opposite type. The circuit has been realized on a SIMOX wafer using an n⁺-poly gate and a LOCOS isolation process. The threshold voltages of the enhancement and depletion SOI NMOSFETs show almost the same temperature dependence when a suitable back-gate bias is applied. Experimental results show a temperature coefficient of 33.8 p.p.m./°C over the temperature range of -50 to 75°C. The variation of threshold voltage difference with temperature is small, and this circuit becomes more advantageous as the front-gate oxide is scaled down or the bias current is reduced     

CMOS bandgap voltage reference circuit for supply voltages down to 0.6 V

A CMOS bandgap voltage reference (BVR) circuit is proposed that operates at power supply voltages down to 0.6 V. The BVR is designed in a commercially available 0.13 /spl mu/m digital CMOS technology. No analogue process options are required.     

基于汽车环境的带隙基准电压源的设计

比较了传统带运算放大器的带隙基准电压源电路与采用曲率补偿技术的改进电路,设计了一种适合汽车电子使用的带隙基准电压源,该设计电路基于上海贝岭2μm 40V bipolar工艺,采用一阶曲率补偿技术,充分考虑了汽车空间有限,温差大,噪声多的环境特点,没有使用运放,避免其复杂的结构以及所引起的失调,因此降低了电路成本并改善性能,设计中还引入了启动电路,大大降低了附加功耗.用Cadence Spectre对电路仿真,结果表明,电路温度特性好,抗干扰能力强,有较高的电源抑制比(PSRR),达到预期指标.     

A low-voltage low-power voltage reference based on subthreshold MOSFETs

In this work, a new low-voltage low-power CMOS voltage reference independent of temperature is presented. It is based on subthreshold MOSFETs and on compensating a PTAT-based variable with the gate-source voltage of a subthreshold MOSFET. The circuit, designed with a standard 1.2-/spl mu/m CMOS technology, exhibits an average voltage of about 295 mV with an average temperature coefficient of 119 ppm//spl deg/C in the range -25 to +125/spl deg/C. A brief study of gate-source voltage behavior with respect to temperature in subthreshold MOSFETs is also reported.     

An ultra-low-power CMOS voltage reference generator based on body bias technique

A CMOS voltage reference, based on body bias technique, has been proposed and simulated using SMIC 0.18 μm CMOS technology in this paper. The proposed circuit can achieve a temperature coefficient of 19.4 ppm/°C in a temperature range from −20 °C to 80 °C, and a line sensitivity of 0.024 mV/V in a supply voltage range from 0.85 V to 2.5 V, without the use of resistors and any other special devices such as thick gate oxides MOSFETs with higher threshold voltage. The supply current at the maximum supply voltage and at 27 °C is 214 nA. The power supply rejection ratio without any filtering capacitor at 10 Hz and 10 kHz are −88.2 dB and −36 dB, respectively.     

基于LDO电压调整器的带隙基准电压源设计

设计一款应用于电压调整器（LDO）的带隙基准电压源。电压基准是模拟电路设计必不可缺少的一个单元模块,带隙基准电压源为LDO提供一个精确的参考电压,是LDO系统设计关键模块之一。本文设计的带隙基准电压源采用0.5μm标准的CMOS工艺实现。为了提高电压抑制性,采用了低压共源共栅的电流镜结构,并且在基准内部设计了一个运算放大器,合理的运放设计进一步提高了电源抑制性。基于Cadence的Spectre进行前仿真验证,结果表明该带隙基准电压源具有较低的变化率、较小的温漂系数和较高的电源抑制比,其对抗电源变化和温度变化特性较好。     

基于LDO稳压器的带隙基准电压源的设计

基准模块是LDO线性稳压器的核心部分,它是影响稳压器精度的关键因素之一。本文针对LDO线性稳压器对基准模块一方面有较高的精度要求,另一方面又有较低静态电流要求的矛盾设计了一款简单实用的电压基准电路。仿真结果表明该电路在-40~140℃的温度系数为7.7′10-6℃,低频时的电源抑制比可达-76dB,基准源电路的供电电压范围为2~4.5V。     

表面栅BSIT的栅源低击穿问题研究

通过对DX0231型BSIT栅源低击穿问题的分析,讨论了设计、材料、环境、设备等因素对表面栅BSIT栅源击穿的影响,指出了提高栅源击穿的努力方向。     

基于视觉的AGV两轮差速转向最优控制研究

简要地介绍了基于机器视觉导向的AGV两轮差速转向的原理和组成,并对计算机控制系统设计,图像信息识别等AGV控制问题进行了阐述.提出了一种采用最优控制方法对两轮差速转向进行控制.仿真和实验结果表明,采用最优控制方法对两轮差速转向进行控制,样车运行过程稳定,路径跟踪可靠,控制性能良好.     

基准电压源设计

分析了基准电压源两个误差:温度误差、运算放大器失调.详细分析了解决运算放大器失调、温度补偿的方法;设计出产生多个基准电压源;同时给出带负载等问题的解决方法,并指出今后的发展趋势.     

Modeling and analysis of common-mode voltages generated in medium voltage PWM-CSI drives

Common-mode voltages appear in pulse-width modulated current-source inverters (PWM-CSIs) drives due to the operating principles of the input rectifier and the output inverter. This paper presents the modeling and analysis of a medium voltage current-source inverter drive, using the Matlab software. Simulated results of the model are in close agreement with experimental waveforms obtained from an industrial AC drive, which shows overvoltages of up to 100%, generating important insulation stresses at the motor stator terminals.     

一种中心值精确可调的高性能带隙基准电压源

不同的集成电路制造工艺,对平衡温度时的带隙基准电压值有影响.为此,本文提出了通过改变带隙基准电压输出级电路结构的方法,实现了在基准电路内部可精确调整基准电压中心值,以满足在不同工艺条件下电路系统对基准电压中心值的精度要求.本芯片根据CSMC公司0.50μm CMOS混合信号工艺模型设计并进行流片.测试结果表明,本文提出的方法能调整基准电压中心值.利用这种方法,可以实现带隙基准电压中心值宽范围的可调,使基准电压的输出完全符合系统所需.     

一种高精度带隙基准电压源电路设计

针对传统CMOS带隙电压基准源电路电源电压较高,基准电压输出范围有限等问题,通过增加启动电路,并采用共源共栅结构的PTAT电流产生电路,设计了一种高精度、低温漂、与电源无关的具有稳定电压输出特性的带隙电压源.基于0.5μm高压BiCMOS工艺对电路进行了仿真,结果表明,在-40℃～85℃范围内,该带隙基准电路的温度系数为7ppm/℃,室温下的带隙基准电压为1.215 V.     

CMOS带隙基准电压源的设计

许多模拟电路需要性能较好的带隙基准电压源,如ADC,DAC等.对工艺、电源电压、负载变化不敏感的带隙基准电压源在模拟电路中得到了广泛的应用.现详细分析并说明了设计这样的带隙基准电压源电路需要考虑的问题.