Low-voltage low-power superior-order curvature-corrected voltage reference

A new superior-order curvature-corrected voltage reference will be presented. In order to improve the temperature behavior of the circuit, a double differential structure will be used, implementing the linear and the superior-order curvature corrections. An original ComplemenTary with Absolute Temperature voltage generator will be proposed, using exclusively MOS transistors biased in weak inversion for a low power operation of the voltage reference, having two great advantages: an important reducing of the circuit silicon area and an improved accuracy (matched resistors being replaced by matched MOS active devices). The superior-order curvature-correction will be implemented by taking the difference between two gate-source voltages of subthreshold-operated MOS transistors, biased at drain currents having different temperature dependencies: PTAT (ProporTional with Absolute Temperature) and square PTAT. In order to obtain a low-voltage operation of the circuit, the classical MOS transistor, which implements the elementary voltage reference, could be replaced by a Dynamic Threshold MOS transistor. The SPICE simulations confirm the theoretical estimated results, showing a temperature coefficient under 6 ppm/K for an extended input range 223 K < T < 333 K and for a supply voltage of 1.8 V and a current consumption of about 1 μA.     

CMOS voltage reference based on threshold voltage and thermal voltage

A fully CMOS based voltage reference circuit is presented in this paper. The voltage reference circuit uses the difference between gate-to-source voltages of two MOSFETs operating in the weak-inversion region to generate the voltage with positive temperature coefficient. The reference voltage can be obtained by combining this voltage difference and the extracted threshold voltage of a saturated MOSFET which has a negative temperature coefficient. This circuit, implemented in a standard 0.35-μm CMOS process, provides a nominal reference voltage of 1.361 V at 2-V supply voltage. Experimental results show that the temperature coefficient is 36.7 ppm/°C in the range from −20 to 100°C. It occupies 0.039 mm² of active area and dissipates 82 μW at room temperature. With a 0.5-μF load capacitor, the measured noise density at 100 Hz and 100 kHz is 3.6 and 2 5 \textnV/?{\textHz} , 2 5\,{\text{nV}}/\sqrt {\text{Hz}} , respectively.     

Spatial Localization of Carrier Traps in 4H-SiC MOSFET Devices Using Thermally Stimulated Current

Carrier traps in 4H-SiC metal–oxide–semiconductor (MOS) capacitor and transistor devices were studied using the thermally stimulated current (TSC) method. TSC spectra from p-type MOS capacitors and n-channel MOS field-effect transistors (MOSFETs) indicated the presence of oxide traps with peak emission around 55 K. An additional peak near 80 K was observed due to acceptor activation and hole traps near the interface. The physical location of the traps in the devices was deduced using a localized electric field approach. The density of hole traps contributing to the 80-K peak was separated from the acceptor trap density using a gamma-ray irradiation method. As a result, hole trap density of N _t,hole = 2.08 × 10¹⁵ cm⁻³ at 2 MV/cm gate field and N _t,hole = 2.5 × 10¹⁶ cm⁻³ at 4.5 MV/cm gate field was extracted from the 80-K TSC spectra. Measurements of the source-body n ⁺–p junction suggested the presence of implantation damage in the space-charge region, as well as defect states near the n ⁺ SiC substrate.     

Interband Cascade Lasers with Wavelengths Spanning 3.2–4.2 <Emphasis Type="Italic">μ</Emphasis>m

We report a detailed experimental investigation of five interband cascade lasers with five active stages each and emitting at wavelengths between 3.2 μm and 4.2 μm at room temperature. Pulsed threshold current densities as low as 394 A/cm² and voltage efficiencies as high as 76% are obtained at 300 K. The low pulsed threshold power densities (0.9–1.6 kW/cm² at 300 K) imply that ambient-temperature cw operation should be possible over the entire spectral band once optimized narrow ridges can be fabricated.     

A 1.8-V 0.7 ppm/°C high order temperature-compensated CMOS current reference

A high order curvature compensation technique for current reference generator which exploits the I–V characteristic of MOS to achieve I _SC (T ^m ) (m ≥ 2) is described. I _SC (T ^m ) is a self-compensated current which corrects its negative three-order TC (Temperature Coefficient) and linear TC by itself. Then, I (T ²) is achieved also by exploiting the I–V characteristic of MOS, for correcting the other negative high order parts of I _SC (T ^m ). This circuit operates on a 1.8 V power supply and is compatible with a standard n-well 0.5-μm digital CMOS process. The circuit realizes a temperature coefficient of 0.7 ppm/°C, a deviation of the simulated output current of 0.011% from −20°C to + 150°C and 97.5 dB PSRR through HSPICE simulation.     

Thermoelectric Properties of <Emphasis Type="Italic">In Situ</Emphasis> Formed Bi<Subscript>0.85</Subscript>Sb<Subscript>0.15</Subscript>/Bi-Rich Particles Composite

A Bi-15 at.%Sb alloy, homogenized by equal channel angular extrusion (ECAE) at T = 523 K, has been treated just above its solidus temperature, causing segregation of a secondary Bi-rich phase at the grain boundaries. This process results in an in situ composite. The thermoelectric properties of the composite have been measured in the range of 5 K < T < 300 K. The results are compared with those of the homogeneous alloy. The presence of a Bi-rich phase improves the Seebeck coefficient at T < 50 K, and enhances the electrical conductivity by a factor of 1.4 at T = 300 K up to a factor of 3.4 at T = 50 K; unfortunately, the thermal conductivity also increases by about 50% in the same temperature range. As a result, the figure of merit, Z, is slightly suppressed above T = 110 K, but increases at lower temperatures, reaching a peak value of 4.2 × 10⁻³ K⁻¹ at T = 90 K. The power factor considerably increases over the whole temperature range, rendering this material suitable as the n-type leg of a cryogenic thermoelectric generator for cold energy recovery in a liquefied natural gas plant.     

Evaluation of MOS structures processed on 4H–SiC layers grown by PVT epitaxy

MOS capacitors have been fabricated on 4H–SiC epilayers grown by physical vapor transport (PVT) epitaxy. The properties were compared with those on similar structures based on chemical vapor deposition (CVD) layers. Capacitance–voltage (C–V) and conductance measurements (G–V) were performed in the frequency range of 1 kHz to 1 MHz and also at temperatures up to 475 K. Detailed investigations of the PVT structures indicate a stable behaviour of the interface traps from room temperature up to 475 K. The amount of positive oxide charge Q_O is 6.83 × 10⁹ cm⁻² at room temperature and decreases with temperature increase. This suggests that the processed devices are temperature stable. The density of interface states D_it obtained by Nicollian–Brews conductance method is lower in the structure based on the PVT grown sample.     

Synthesis and Electrical Properties of γ-Na<Subscript><Emphasis Type="Italic">x</Emphasis></Subscript>Co<Subscript>2</Subscript>O<Subscript>4</Subscript> via a Citrate Sol–Gel Method with Polyethylene Glycol 400

In this work, a citrate sol–gel method (Sol–Gel) with polyethylene glycol 400 (Sol-Gel-PEG400) was developed to prepare γ-Na _x Co₂O₄ by using sodium and cobalt nitrates as the raw materials, citric acid as a complexing agent, and PEG400 as a dispersant. At 800°C, single-phase γ-Na _x Co₂O₄ crystals were obtained using Sol-Gel-PEG400. With the addition of 1 vol.% PEG400, smaller, flaky particles exhibited a well-tiled structure along the plane direction of the flaky particles. Moreover, polycrystalline sintered bulk γ-Na _x Co₂O₄ with more highly oriented crystals and greater compact density was fabricated using the Sol-Gel-PEG400 synthesized powders compared with the powders synthesized by citrate Sol–Gel. The electrical conductivity (σ) values of Sol-Gel-PEG400 samples were higher than those of Sol–Gel samples between 400 K and 900 K. The σ value of Sol-Gel-PEG400 increased to 3.13 × 10⁴ Sm⁻¹ at 400 K and to 1.84 × 10⁴ Sm⁻¹ at 900 K. Between 400 K and 850 K, the Seebeck coefficient (α) values of Sol-Gel-PEG400 samples were slightly lower than those of Sol–Gel samples. Near 900 K, the α values of these two methods were nearly equal, at 164 μV K⁻¹. Between 400 K and 900 K, the power factor (P) of Sol-Gel-PEG400 was evidently larger than that of Sol–Gel.     

Characterization of HgCdTe MWIR Back-Illuminated Electron-Initiated Avalanche Photodiodes

This article reports new characterization data for large-area (250 μm ×  250 μm) back-illuminated planar n-on-p HgCdTe electron-initiated avalanche photodiodes (e-APDs). These e-APDs were fabricated in p-type HgCdTe films grown by liquid-phase epitaxy (LPE) on CdZnTe substrates. We previously reported that these arrays exhibit gain that increases exponentially with reverse bias voltage, with gain-versus-bias curves that are quite uniform from element to element, and with a maximum gain of 648 at −11.7 V at 160 K for a cutoff wavelength of 4.06 μm. Here we report new data on these planar e-APDs. Data from a third LPE film with a longer cutoff wavelength (4.29 μm at 160 K) supports the exponential dependence of gain on cutoff wavelength, for the same bias voltage, that we reported for the first two films (with cutoffs of 3.54 μm and 4.06 μm at 160 K), in agreement with Beck’s empirical model for gain versus voltage and cutoff wavelength in HgCdTe e-APDs. Our lowest gain-normalized current density at 80 K and zero field-of-view is 0.3 μA/cm² at −10.0 V for a cutoff of 4.23 μm at 80 K. We report data for the temperature dependence of gain over 80 K to 200 K. We report, for the first time, the dependence of measured gain on junction area for widely spaced circular diodes with radii of 20 μm to 175 μm. We interpret the variation of measured gain with junction area in terms of an edge-enhanced electric field, and fit the data with a two-gain model having a lower interior gain and a higher edge gain. We report data for the excess noise factor F(M) near unity for gains up to 150 at 196 K. We describe the abrupt breakdown phenomenon seen in most of our devices at high reverse bias.     

Magnetron Deposition of In Situ Thermoelectric Mg2Ge Thin Films

Thin films of the semiconducting compound Mg₂Ge were deposited by magnetron cosputtering from source targets of high-purity Mg and Ge onto glass substrates at temperatures T _s = 300°C to 700°C. X-ray diffraction shows that the Mg₂Ge compound begins to form at a substrate temperature T _s ≈ 300°C. Films deposited at T _s = 400°C to 600°C are single-phase Mg₂Ge and have strong x-ray peaks. At higher T _s the films tend to be dominated by a Ge-rich phase primarily due to the loss of magnesium vapor from the condensing film.␣At optimum deposition temperatures, 550°C to 600°C, films have an electrical conductivity σ _600 K = 20 Ω⁻¹ cm⁻¹ to 40 Ω⁻¹ cm⁻¹ and a Seebeck coefficient α = 300 μV K⁻¹ to 450 μV K⁻¹ over a broad temperature range of 200 K to 600 K.     

Electron scattering by acceptor centers in <Emphasis Type="Italic">p</Emphasis>-Ag<Subscript>2</Subscript>Te at low temperatures

Resonant electron scattering in p-Ag₂Te at acceptor concentrations N _a < 4.2 × 10¹⁶ cm⁻³ has been observed in the temperature range of 50–80 K. The contribution of the resonant scattering to the temperature dependences of the conductivity σ(T) and thermopower α₀(T) has been calculated. It is shown that this contribution exceeds that of charge carrier scattering by acoustic phonons.     

A Theoretical Model for the HgCdTe Electron Avalanche Photodiode

A ballistic model is presented for electron avalanche multiplication in the conduction band of HgCdTe, based upon the concept of an optical phonon limited mean free path for the electron, λ _e. The model predicts avalanche gain as a function of applied bias voltage V, and a threshold voltage for impact ionization V _th. Impact ionization probabilities are calculated analytically using a simplified band structure model for HgCdTe and used to estimate values for the threshold energy for impact ionization. A simple ballistic model is developed to correlate the relationship between electron energy and applied bias voltage, based upon the relevant electron scattering mechanisms in HgCdTe. A comparison with published gain–voltage data suggests that the process is limited by optical phonon scattering, and the relationship between electron energy and applied bias voltage, for a uniform electric field F = V/W, across a diode depletion width W, is given by E = α(E)V, where α(E) = [λ _e(E)/W]. For high electron energies λ _e(E) is independent of E and α(E) depends only on the dielectric parameters of the material. Using this simple model it is easy to predict electron avalanche gain versus voltage for any parametric combination of diode geometry, bandgap, and operating temperature.     

A High-Order Temperature-Compensated Subthreshold Voltage Reference Using Channel Length Modulation Compensation Technique

The paper presents a novel high-order temperature-compensated subthreshold voltage reference that utilizes temperature characteristics of the gate-to-source voltage of subthreshold MOS transistor. The proposed high-order temperature-compensated voltage reference has been designed using two CMOS voltage references and a current subtraction circuit to achieve a low temperature coefficient over a wide temperature range. The proposed circuit offers an output reference voltage of 250.8 mV, line sensitivity of 0.0674%/V and temperature coefficient of 37.4 ppm/°C for the temperature range varying from???20 \(\mathrm{^\circ{\rm C} }\) to 140 °C at nominal conditions. The power supply rejection ratio is obtained as???46.02 dB at a frequency of 100 Hz and???41.91 dB at a frequency of 1 MHz. The proposed circuit shows an output noise of 1.86 \(\mathrm{\mu V}/\surd \mathrm{Hz}\) at 100 Hz and 259.72 \(\mathrm{nV}/\surd \mathrm{Hz}\) at 1 MHz. The proposed circuit has been designed in BSIM3V3 180 nm CMOS technology using Cadence tool. The corner analysis of the proposed circuit has also been performed to show its performance in extreme conditions. The proposed circuit occupies a small chip area of 51 \(\upmu\)m?×?75.3 \(\upmu\)m.

     

Thermoelectric Properties of the Narrow-Gap Intermetallic Compound Ga<Subscript>2</Subscript>Ru: Effect of Re Substitution for Ru Atoms

In this paper, the effect of hole doping on the thermoelectric properties of the binary narrow-gap semiconducting intermetallic compound Ga₂Ru in the temperature range from 373 K to 973 K was investigated. We synthesized sintered pellets by spark plasma sintering (SPS) after arc-melting and succeeded in preparing crack-free samples. The maximum dimensionless figure of merit ZT _max was 0.50 at 773 K for the sintered Ga₂Ru alloy. The temperature dependence of the electrical resistivity and its magnitude at 373 K dramatically changed from negative (~11,000 μΩcm) to positive (~200 μΩcm) upon hole doping by the substitution of Re for Ru atoms. Also, the Seebeck coefficient at 373 K changed from 300 μV/K to 75 μV/K. These changes were identified by the increase in carrier concentrations observed by Hall- effect measurements. In particular, large power factors (2.0 mW/m K² to 3.0 mW/m K²) were obtained over a wide temperature range from 373 K to 973 K upon Re substitution. The lattice thermal conductivity beneficially decreased with increasing Re concentration as a result of an alloying effect.     

Accurate Simulation of Temperature-Dependent Dark Current in HgCdTe Infrared Detectors Assisted by Analytical Modeling

Resistance–voltage curves of n ⁺-on-p Hg_1−x Cd _x Te infrared photodiodes were measured in the temperature range of 60 K to 120 K. Characteristics obtained experimentally were fitted by an improved simultaneous-mode nonlinear fitting process. Based on the extracted parameters, an efficient numerical sim- ulation approach has been developed by inserting trap-assisted and band-to-band tunneling models into continuity equations as generation–recombination processes. Simulated dark-current characteristics were found to be in good agreement with the experimental data, demonstrating the validity of the nonlinear fitting process. Our work presents an efficient method for dark-current simulations over a wide range of temperatures and bias voltages, which is important for investigating mechanisms of carrier transport across the HgCdTe junction.     

Nonequilibrium Operation of Arsenic Diffused Long-Wavelength Infrared HgCdTe Photodiodes

We demonstrated a device with a unique planar architecture using a novel approach for obtaining low arsenic doping concentrations in long-wavelength (LW) HgCdTe on CdZnTe substrates. HgCdTe materials were grown by molecular beam epitaxy (MBE). We fabricated a p-on-n structure that we term P ⁺/π/N ⁺ where the symbol “π” is to indicate a drastically reduced extrinsic p-type carrier concentration (on the order of mid 10¹⁵ cm⁻³); P ⁺ and N ⁺ denote a higher doping density, as well as a higher energy gap, than the photosensitive base π-region. Fabricated devices indicated that Auger suppression is seen in the P ⁺/π/N ⁺ architecture at temperatures above 130 K and we obtained a saturation current on the order of 3 mA on 250-μm-diameter devices at 300 K with Auger suppression. Data shows that about a 50% reduction in dark current is achieved at 300 K due to Auger suppression. The onset of Auger suppression voltage is 450 mV at 300 K and 100 mV at 130 K. Results indicate that a reduction of the series resistance could reduce this further. A principal challenge was to obtain low p-type doping levels in the π-region. This issue was overcome using a novel deep diffusion process, thereby demonstrating successfully low-doped p-type HgCdTe in MBE-grown material. Near-classical spectral responses were obtained at 250 K and at 100 K with cut-off wavelengths of 7.4 μm and 10.4 μm, respectively. At 100 K, the measured non-antireflection-coated quantum efficiency was 0.57 at 0.1 V under backside illumination. Received November 7, 2007; accepted March 19, 2008     

Thermoelectric Properties of Ag-doped Mg<Subscript>2</Subscript>Ge Thin Films Prepared by Magnetron Sputtering

Silver doped p-type Mg₂Ge thin films were grown in situ at 773 K using magnetron co-sputtering from individual high-purity Mg and Ge targets. A sacrificial base layer of silver of various thicknesses from 4 nm to 20 nm was initially deposited onto the substrate to supply Ag atoms, which entered the growing Mg₂Ge films by thermal diffusion. The addition of silver during film growth led to increased grain size and surface microroughness. The carrier concentration increased from 1.9 × 10¹⁸ cm⁻³ for undoped films to 8.8 × 10¹⁸ cm⁻³ for the most heavily doped films, but it did not reach saturation. Measurements in the temperature range of T = 200–650 K showed a positive Seebeck coefficient for all the films, with maximum values at temperatures between 400 K and 500 K. The highest Seebeck coefficient of the undoped film was 400 μV K⁻¹, while it was 280 μV K⁻¹ for the most heavily doped film at ∼400 K. The electrical conductivity increased with silver doping by a factor of approximately 10. The temperature effects on power factors for the undoped and lightly doped films were very limited, while the effects for the heavily doped films were substantial. The power factor of the heavily doped films reached a non-optimum value of ∼10⁻⁵ W cm⁻¹ K⁻² at 700 K.     

Influence of samarium on the thermoelectric figure of merit of Sm<Subscript><Emphasis Type="Italic">x</Emphasis></Subscript>Pb<Subscript>1 − <Emphasis Type="Italic">x</Emphasis></Subscript>Te alloys

The temperature and concentration dependences of the electrical (conductivity σ, the Hall coefficient R), thermoelectric (thermovoltage α), and thermal (thermal conductivity K _tot) characteristics of Sm _x Pb_{1 − x} Te alloys (x = 0, 0.02, 0.04, 0.08) are studied in the temperature range 100–500 K. Using the data for σ, α, and K _tot, the thermoelectric power α²σ, figure of merit Z, and efficiency δ are calculated. It is established that at room-temperature α²σ and Z peak at the hole concentration p ≈ 1.2 × 10¹⁸ cm⁻³.     

Circular and linear enhancement-mode 6H-SiC MOSFETs for high temperature applications

Direct current measurements are performed up to 673K at circular and linear (shown in parenthesis) enhancement-mode metal oxide semiconductor field effect transistors (MOSFETs). These devices are fabricated on a p-type 6H-SiC epitaxial layer with a doping concentration N_A ≈ 1 × 10¹⁶ cm⁻¹. The n⁺ source/drain regions and the p⁺ regions for the channel stops are achieved by ion implantation of nitrogen and aluminum, respectively. Both MOSFET geometries show excellent output characteristics with a good saturation behavior even at elevated temperatures. The inversion layer mobility μ_n extracted in the linear region is 38 cm²·V⁻¹·s⁻¹ (35 cm²·V⁻¹·s⁻¹) and reveals a weak dependence on temperature with a maximum of 46 cm²·V⁻¹·s⁻¹ (42 cm²·V⁻¹·s⁻¹) at about 473K. Regarding the transfer characteristics, the drain current I_D can be well modulated by the gate-source voltage V_GS resulting in an I_on/L_off-ratio of 10⁸ (10⁸) at 303K and 10⁵ (10⁶) at 673K. In the subthreshold regime, I_D can be pinched off well below 10 pA with a subthreshold swing of 150 mV/decade (155 mV/decade) at room temperature. The threshold voltage V_T as a function of temperature shows two linear sections with negative temperature coefficients of −6.8 mV·K⁻¹ (−6.8 mV·K⁻¹) from 303 to 423K and −2.5 mV·K⁻¹ (−2.0 mV·K⁻¹) from 423 to 673K. By measuring V_T as a function of bulk-source voltage V_BS at different temperatures, N_A can be directly estimated at a transistor and gives 9.6 × 10¹⁵ cm⁻³ (9.8 × 10¹⁵ cm⁻³). The measured bulk Fermi potential Φ_f of the p-type epitaxial layer deviates less than 10% from the calculated value at a given temperature.     

Measurement and Calculation of the Absolute Thermoelectric Power of Rhodium and Iridium

The thermoelectric power of Rh and Ir was redetermined between 100 K and 1400 K. It varies almost linearly from +1.7 μV K⁻¹ to −3.8 μV K⁻¹ for Rh and from +1.5 μV K⁻¹ to −2.2 μV K⁻¹ for Ir. The diffusive part of the thermopower could be calculated from the density of states. It is approximately equal to the temperature dependence of the electrochemical potential of the electrons divided by the electronic charge. This is attributed to the approximate establishment of local equilibrium between electrons and lattice atoms above 400 K—a condition not fulfilled in the phonon-drag regime below 300 K.