Measurement of threshold voltages of thin-film accumulation-modePMOS/SOI transistors

Accumulation-mode PMOS transistors on SOI (silicon on insulator) are characterized by several conduction mechanisms. Measurements of the threshold voltage corresponding to each of them are presented for the first time. An intuitive physical interpretation of their dependence on the front- and back-gate voltages is also given     

Three-dimensional analytic modelling of front and back gate threshold voltages for small geometry fully depleted SOI MOSFET’s

New 3-D analytical models of front and back gate threshold voltages for fully depleted SOI MOSFET’s have been described here. The present models take into account the contributions of all the three paths of conduction such as front gate oxide-silicon, back gate oxide-silicon and side wall oxide-silicon interfaces in mesa isolated structure of such MOSFET’s. In order to do this, 3-D Poisson’s equation has been solved analytically with suitable boundary conditions to obtain an explicit expression of electrostatic potential within fully depleted SOI film with uniform doping concentration. With the help of this expression, the compact and closed form formulae of front and back gate threshold voltages under various conditions have been established. In addition to this, the closed form expressions of biasing counterparts of front and back threshold voltages i.e. respective back and front gate biases have also been reported in order to decide required operational modes of both interfaces of the device. The calculated results of the threshold voltages have been validated with available numerical data.     

Manufacturability of 20-nm ultrathin body fully depleted SOI devices with FUSI metal gates

Ultrathin body (UTB) fully depleted silicon-on-insulator (FDSOI) devices show great performance due to undoped channels and excellent electrostatic control. Very high drive currents and good off-state leakage, ideal subthreshold slope, and small drain-induced barrier lowering (DIBL) have been reported with devices as short as 20 nm. The ultrathin channel enables high device performance, but it imposes a new set of problems. The control of the silicon thickness has become the dominant source of device variations. Selective epitaxial growth has become a necessity to achieve high performance and reliable contacts to UTB FDSOI devices. This work discusses silicon thickness control, selective epitaxial growth, and the mid-gap gate module needed for fully depleted devices. Very good control of short channel effect is shown and drive current fluctuations are discussed.     

Fully depleted SOI CMOS logic gates for low-voltage applications

Approaches are discussed to the design of low-voltage, low-power VLSI circuits based on SOI nanotransistors. Computer simulations are run to analyze the switching performance of NOT, 2NAND, and 2NOR gates implemented in CMOS technology with fully depleted SOI nanotransistors of different design parameters. The delay and switching power are investigated as functions of supply voltage over a range lying below 1 V, for different values of back-gate bias. The possibility is investigated of operating the transistors of a logic gate in subthreshold mode. This approach is shown to provide a significant reduction in switching power under the right conditions.     

An analytical model for fully depleted single gate SOI MOS transistors including lattice temperature effects

An analytical model for fully depleted SOI MOSFETs is presented. Major small geometry effects such as carrier velocity saturation, mobility degradation, channel length modulation, and drain induced barrier lowering are included. Device self heating due to low thermal conductivity of a buried oxide layer is included in carrier mobility modelling. Thermal effects are also included in threshold voltage expression. Source, drain, and channel resistance effects are also included. Modelled results are then compared to available measured data and are shown to be in very good agreement.     

A modified two dimensional analytical model for short-channel fully depleted SOI MESFET's

Analytical modeling of channel potential of SOI MESFET can be obtained by solving Poisson's equation to derive an expression for channel potential. Superposition method is an accurate technique for solving Poisson's equation, in which the solution of the 2-D Poisson's equation is represented as the sum of the 1-D Poisson's equation and a 2-D Laplace's equation solutions. In the existing models applying this method, the authors tried to solve 2-D Laplace's equation by using approximations [1] or modifying the boundary conditions [2] producing inaccurate results. In this report, a new methodology is applied to develop a modified analytical model for the channel potential of fully depleted SOI MESFET's, in which the drawbacks of the previous models are significantly eliminated. Using this model, the subthreshold performance of the device including channel potential, threshold voltage, drain current, and subthreshold swing under various conditions have been studied, plotted, and compared with TCAD simulation and experimental results. It is concluded the proposed model has been improved in term of accuracy compared to other existing models.     

A physically based compact device model for fully depleted andnearly fully depleted SOI MOSFET

A compact submicrometer Fully Depleted Silicon-On-Insulator (FDSOI) and Nearly FDSOI MOSFET device model suitable for analog as well as digital application has been proposed. It is an all region model. In developing this model care has been taken in retaining the basic functional form of physical models while improving the model accuracy and computational efficiency. In addition to the commonly included effects in the FDSOI MOSFET model, we have given careful consideration to parasitic source/drain resistance, Drain Induced Conductivity Enhancement (DICE) effect, floating body effect, self-heating and model continuity. A single parameter set is used for a large set of device dimensions except threshold voltage and parasitic source/drain resistance due to silicon film thickness variations. The accuracy of the model is validated with experimental data using NMOS FDSOI devices and found to be in good agreement     

X-band fully depleted SOI Amplifier with adaptive bias control

A 10-GHz amplifier with an adaptive bias control circuit is realized using fully depleted SOI CMOS technology. The effective gate bias of the amplifier MOSFET adjusts itself based on the power level of the input signal. Measured results showed reduction of overall power consumption and wider range of output power near its peak efficiency. At absence of the signal, the amplifier can be automatically switched to a standby mode with approximately 85% reduction of power consumption. Power saving is also demonstrated for pulsed signal modulated at 10 MHz.     

Modeling for floating body effects in fully depleted SOI MOSFETs

A model based on SOI MOSFET and BJT device theories is developed to describe the current kink and breakdown phenomena in thin-film SOI MOSFET drain-source current-voltage characteristics operated in strong inversion. The modulation of MOSFET current by raised floating body potential is discussed to provide an insight for understanding the suppression of current kink in fully depleted thin-film SOI devices. The proposed analytical model successfully simulates the drain current-voltage characteristics of thin-film SOI n-MOSFETs fabricated on SIMOX wafers     

Thin-film SOI CMOS transistors with p+-polysilicon gates

A comparison is given of the use of p⁺-polysilicon and n⁺-polysilicon as the gate material for high-performance CMOS processes in fully depleted, thin SOI (silicon on insulator) films. Experimental devices on Simox substrates are compared with numerical simulations. It is found that n-channel transistors with p-poly gates require lower channel doping levels than their n-poly counterparts, leading to higher gains and easier control of the threshold voltage. The lower electric fields in the p-poly transistor also result in improved drain breakdown characteristics. Control of the subthreshold and punch-through characteristics of the p-poly device requires the use of very thin films when there is significant fixed positive charge at the interface with the buried oxide     

Silicon-on-insulator nanotransistors with two independent gates

The results of numerical simulation of electrical characteristics of silicon-on-insulator MOSFET nanotransistors with two independent gates are reported. The cases of grounded and floating bases with the surface recombination of charge carriers either disregarded or taken into account are considered. It is shown that, at specified design parameters (gate length 50–100 nm, thickness of silicon layer 25–50 nm), one can vary the transistor’s threshold voltage by 0.45 V, reduce the transistor current in the off state by seven orders of magnitude, and decrease the subthreshold slope of the gate characteristics to 60 mV/decade by varying the voltage applied to the second gate. Suppression of the short-channel effects in the transistors under consideration depends on a number of parameters (listed in order of decreasing effect): the gate material, the lifetime of charge carriers (for floating or grounded base), the thickness of the top silicon layer, the voltage applied to the additional gate, and the channel length.     

Experimental investigation of ESD design window for fully depleted SOI N-MOSFETs

In this article, the impact in FDSOI technology, of ground plane and buried oxide (BOX) size on the robustness and on the NMOS triggering voltage (Vt1) is shown. We show experimentally that firstly thin BOX devices are more robust than thick BOX devices and secondly with a higher Vt1, thin BOX device purposes a larger range to trigger ESD network and to optimize design.     

High threshold voltages in small geometry mos transistors due to edge contamination

A new type of high threshold problem in small geometry MOS transistors is identified and characterized. The origin of the problem lies in processing irregularities which produce a contamination charge only at the edges of the gate oxide region. Such contamination is introduced by an inadequate rinsing procedure after gate oxide definition. This type of an edge contamination is shown both experimentally and theoretically to create a change in the threshold voltage, transconductance and the shape of the I_D-V_GS transfer curve. The I_D-V_GS transfer characteristics for such a condition is derived theoretically using a Fourier series expansion method to solve Poisson's equation for the surface potential. This is then used to determine the variation in threshold voltage across the width of the gate and subsequently to predict the transfer characteristic. Comparison of experimental and theoretical results shows excellent agreement.     

Two-dimensional analytical modeling of fully depleted DMG SOI MOSFET and evidence for diminished SCEs

A two-dimensional (2-D) analytical model for the surface potential variation along the channel in fully depleted dual-material gate silicon-on-insulator MOSFETs is developed to investigate the short-channel effects (SCEs). Our model includes the effects of the source/drain and body doping concentrations, the lengths of the gate metals and their work functions, applied drain and substrate biases, the thickness of the gate and buried oxide and also the silicon thin film. We demonstrate that the surface potential in the channel region exhibits a step function that ensures the screening of the drain potential variation by the gate near the drain resulting in suppressed SCEs like the hot-carrier effect and drain-induced barrier-lowering (DIBL). The model is extended to find an expression for the threshold voltage in the submicrometer regime, which predicts a desirable "rollup" in the threshold voltage with decreasing channel lengths. The accuracy of the results obtained using our analytical model is verified using 2-D numerical simulations.     

Floating body effects model for fault simulation of fully depleted CMOS/SOI circuits

The possibility to perform realistic fault simulations for Silicon-On-Insulator circuits is investigated. A simple but complete fault simulation model (fsm) for a technology specific effect is described. The effect considered known as kink effect is typical for partially depleted devices but can occur in the presence of a floating body or in the sub-threshold region even in fully depleted devices causing wrong performances. The model proposed here comprises of only a single additional transistor with a controlled body current. It is not a real physical transistor but just one to describe the electrical behaviour of the device when the critical kink-effect situation occurs and for this reason does not increase the simulation time. From the comparison with device characterization measurements on a 1 μm technology device a good matching with the fsm was found.     

Physical subthreshold MOSFET modeling applied to viable design ofdeep-submicrometer fully depleted SOI low-voltage CMOS technology

An insightful study of the subthreshold characteristics of deep-submicrometer fully depleted SOI MOSFET's, based on two-dimensional numerical (PISCES) device simulations, shows that the gate swing and off-state current are governed by gate bias-dependent source/drain charge sharing, which controls back-channel as well as front-channel conduction. The insight from this study guides the development of a physical, two-dimensional analytic model for the subthreshold current and charge, which is linked to our strong-inversion formalism in SOISPICE for circuit simulation. The model is verified by PISCES simulations of scaled devices. The utility of the model in SOISPICE is demonstrated by using it to define a viable design for deep-submicrometer fully depleted SOI CMOS technology based on simulated speed and static power in low-voltage digital circuits     

Threshold voltage model for deep-submicron fully depleted SOI MOSFETs with back gate substrate induced surface potential effects

A simple analytical threshold voltage model for short-channel fully depleted SOI MOSFETs has been derived. The model is based on the analytical solution of the two-dimensional potential distribution in the silicon film (front silicon), which is taken as the sum of the long-channel solution to the Poisson's equation and the short-channel solution to the Laplace equation, and the solution of the Poisson's equation in the silicon substrate (back silicon). The proposed model accounts for the effects of the back gate substrate induced surface potential at the buried oxide-substrate interface which contributed an additional 15–30% reduction in the threshold voltage for the devices used in this work. Conditions on the back gate supply voltage range are determined upon which the surface potential at the buried oxide-substrate interface is accumulated, depleted, or inverted. The short-channel associated drain induced barrier lowering effects are also included in the model. The model predications are in close agreement with PISCES simulation results. The equivalence between the present model and previously reported models is proven. The proposed model is suitable for use in circuit simulation tools such as Spice.     

Analytical modeling of drain current and RF performance for double-gate fully depleted nanoscale SOI MOSFETs

A new 2D analytical drain current model is presented for symmetric double-gate fully depleted nanoscale SOI MOSFETs. Investigation of device parameters like transconductance for double-gate fully depleted nanoscale SOI MOSFETs is also carried out. Finally this work is concluded by modeling the cut-off frequency, which is one of the main figures of merit for analog/RF performance for double-gate fully depleted nanoscale SOI MOSFETs. The results of the modeling are compared with those obtained by a 2D ATLAS device simulator to verify the accuracy of the proposed model.     

Strain and channel engineering for fully depleted SOI MOSFETs towards the 32 nm technology node

In this paper, we review different CMOS technologies used at CEA-LETI to improve hole and electron velocity for the 32 nm technology node Fully Depleted Silicon-On-Insulator (FDSOI) MOSFETs. The orientation, the strain and the material of the channel are the key parameters that have been tuned and optimized. Tensile strained SOI (sSOI) for nMOS and compressive Ge for pMOS are found to be promising channels for CMOS integration. They provide a 2 times (7.5 times) mobility improvement for electrons (holes), giving rise to well-balanced drain currents for n and pMOS. They also allow a tuning of the threshold voltage. The gate length and width scalabity of these technologies are also addressed. In particular, we detail the excellent performance of strained Si_0.6Ge_0.4 and sSOI down to 30 nm gate length. We also discuss the specifics of short channel transport in these channels: the role of the carrier mobility, the limiting scattering phenomena and the ballistic transport.     

A simple analytical model for the front and back gate threshold voltages of a fully-depleted asymmetric SOI MOSFET

A simple analytical model for deriving the front and the back gate threshold voltages of a short-channel fully-depleted SOI MOSFET is presented. Taking into account the lateral variations of the front and the back surface potentials, we obtain two-dimensional potential distributions in the fully depleted silicon body, the front oxide layer, and the back oxide layer. From the obtained two- dimensional potential in the silicon body, the minimum values of both front and back surface potentials are derived and used to describe both front and back gate threshold voltages as closed-form expressions in terms of various device geometry parameters and applied bias voltages. Obtained results are found to be in good agreement with the numerically simulated results.