一种CMOS锯齿波发生器的实现

文章提出了一种用CMOS工艺实现的锯齿波发生器集成电路。对锯齿波的有关性能进行了模拟，同时，与通常的锯齿波发生器进行了对比。     

一种应用于超宽带（UWB）的CMOS五次微分高斯脉冲发生器

A CMOS fifth-derivative Gaussian pulse generator is presented for ultra-wideband （UWB） applications. The design exhibits low power consumption, low circuit complexity, and a precise pulse shape to inherently comply with the FCC spectrum mask for indoor UWB applications without the need for a filter. The pulse generator is implemented with a 1.8-V, 0.18-μm CMOS process. The small core chip size of the pulse generator is only 217 ×121 #m2 because of its all digital circuit design. The measured fifth-derivative Gaussian pulse has a peak-to-peak amplitude of 158 mV and a pulse width of 800 ps. The average power dissipation is 0.6 mW with a pulse repetition frequency of 50 MHz.     

一种CMOS双沿触发器的设计

基于CMOS传输门，分析了单、双沿触发器的逻辑结构，分析了一种晶体管数较少的CMOS双沿触发器，并用PSPICE程序进行了模拟，结果表明这种双沿触发器具有完整的逻辑功能，且具有结构简单，延迟时间短和数据处理能力高的优点，另外，与传统的单沿触发器相比，其功耗大约减少了61%。     

一种超宽带脉冲信号发生器的设计

介绍一种利用并联阶跃恢复二极管(SRD)产生超宽带窄脉冲信号的微带结构电路,该电路可产生宽度为1ns、重复周期为100MHz的窄脉冲信号,其峰值电压达10.44V。文章分析讨论了电路原理与设计方法,并重点研究了偏置电路与匹配电路的设计问题。测量结果显示该电路所产生的脉冲信号具有良好的波形,并且脉冲拖尾的振荡起伏很小,是一种适合于超宽带通信系统的窄脉冲信号形成电路。     

一种基于射频三极管的高斯脉冲发生器的设计

对一种电路简单、成本低廉且易于集成的高斯脉冲发生器进行了分析与设计。该发生器是通过一个微分电路将触发信号转变为含有正、负脉冲信号来驱动射频三极管的“开”与“关”，并通过电容的充、放电形成窄脉冲。测试结果显示该脉冲发生器能产生峰值电压为1．8V，脉冲宽度为0．8ns的高斯脉冲波形，并与仿真结果吻合较好。该电路非常适合于MIC。     

一种UWB雷达脉冲信号发生器的设计

介绍了UWB雷达的人体生命探测系统的工作原理,比较了几种窄脉冲产生方法的优缺点,详细分析了雪崩三极管原理,利用雪崩三极管的雪崩特性实现了超宽带雷达窄脉冲的产生。通过研究分析典型的脉冲产生电路,给出了产生人体生命探测系统的脉冲信号发生器的电路,最后由实验仿真结果可得,电路可生成脉宽为皮秒级的双极性脉冲,脉冲的峰-峰值达2...     

一种超宽带脉冲发生器的设计与仿真

利用双极型晶体管的雪崩特性设计了双管并联的超宽带（Ultra-Wideband，UWB）脉冲发生器，通过添加电感使电路的等效负载增加，在维持脉冲宽度基本不变的情况下使输出脉冲的幅度增加到原来的2．5倍。对电路中各元件参数的选取进行详细的分析说明，给出了参数值与脉冲各项性能的关系。仿真得到的UWB脉冲信号幅度为-38．299V，脉冲宽度约为663．265ps，上升时间459．184ps，下降时间约为969．388ps。     

一种短脉冲宽度的CW信号发生器的设计

本文设计了一种CW脉冲信号发生电路,具有频率稳定性高,上升及下降时间短的特点,适合于产生填充波形极少的CW脉冲。同时还具有每次发射起始相位均相同的特点。试验结果显示,电路达到了指标要求。     

一种低静态功耗的CMOS集成稳压器的实现

提出了一种静态功耗很低的CMOS集成稳压器的实现方法，详细分析了他的工作原理，并给出了具体电路、仿真波形以及分析数据。     

一种脉冲力矩电流发生器的EDA设计

介绍了利用EDA软件对一种脉冲力矩电流发生器的电路设计和仿真分析,获得了详细的设计数据;根据设计结果,组装了实验电路。实际测试参数与EDA仿真非常吻合,验证了EDA设计结果的正确性。     

一种CMOS静态双沿触发器的设计

提出一种ＣＭＯＳ静态双沿触发器结构,以单个锁存器构成记忆单元,而由一特殊的时钟模块产生控制信号,使锁存器在时钟上升和下降沿处瞬时导通,从而形成双沿触发的功能,最小的实现方案只用１４个管子,模拟证明其工作频率可达３００ＭＨｚ以上。     

Logical effort based dynamic power estimation and optimization of static CMOS circuits

This paper introduces a simple and yet accurate closed-form expression to estimate the switching power dissipation of static CMOS gates. The developed model depends on normalizing a gate switching power to that of the unit standard inverter and it accounts for the effect of internodal capacitances. For different loads, gates, sizes and processes, the developed model shows a good agreement with Hspice simulations using BSIM3v3 and BSIM4 models for UMC 0.13 μm and Predictive high-k 45 nm processes, respectively. The average error introduced by the model for the considered scenarios is about 3.1%. Depending on the normalized switching power model, two power optimization techniques have been proposed in this paper. The first deals with transistor sizing problem and presents a scheme to size transistors according to a specific design goal. The second technique relies on the joint transistor sizing and supply voltage scaling for reducing the switching power dissipation under specific delay requirements. This technique exhibits superiority over the first for the considered technology processes: UMC 0.13 μm and the Predictive high-k 45 nm.     

A novel low temperature integration of hybrid CMOS devices on flexible substrates

In this work we demonstrate a novel integration approach to fabricate CMOS circuits on plastic substrates (poly-ethylene naphthalate, PEN). We use pentacene and amorphous silicon (a-Si:H) thin-film transistors (TFTs) as p-channel and n-channel devices, respectively. The maximum processing temperature for n-channel TFTs is 180 °C and 120 °C for the p-channel TFTs. CMOS circuits demonstrated in this work include inverters, NAND, and NOR gates. Carrier mobilities for nMOS and pMOS after the CMOS integration process flow are 0.75 and 0.05 cm²/V s, respectively. Threshold voltages (V_t) are 1.14 V for nMOS and −1.89 V for pMOS. The voltage transfer curve of the CMOS inverter showed a gain of 16. Correct logic operation of integrated flexible NAND and NOR CMOS gates is also demonstrated. In addition, we show that the pMOS gate dielectric is likely failing after electrical stress.     

冒险共振现象及其在CMOS电路最大功耗估计中的应用

随着集成电路工艺的不断提高，CMOS电路规模不断增大，功耗成为集成电路设计主要指标之一。文章首先以多位比较器为例，阐述了存在于部分多位电路功能块中的冒险共振现象；然后给出其在VLSI电路最大功耗估计中的应用。ISCAS85电路集实验结果证实了文章思路的有效性。     

一种曲率补偿CMOS带隙基准源

介绍了一种可提供1.438 V基准电压的曲率补偿带隙基准源.采用一种极其简单有效的方法,直接实现曲率补偿.该电路采用双金属双多晶硅0.6 μm CMOS工艺制造,用于驱动一个10位20 MS/s A/D转换器.仿真结果显示,该带隙基准源在室温5 V电源电压下,仅耗用64 μA电流;0～80°C范围内,温度系数为13.7 ppm/K, 电源电压抑制比为64.7 dB.     

Delay and Power Expressions for a CMOS Inverter Driving a Resistive-Capacitive Load

A delay and power model of a CMOS inverter driving aresistive-capacitive load is presented. The model is derivedfrom Sakurais alpha-power law and exhibits good accuracy. Themodel can be used to design and analyze those CMOS invertersthat drive a large RC load when considering bothspeed and power. Expressions are provided for estimating thepropagation delay and transition time which exhibit less than27% discrepancy from SPICE for a wide variety of RCloads. Expressions are also provided for modeling the short-circuitpower dissipation of a CMOS inverter driving a resistive-capacitiveinterconnect line which are accurate to within 15% of SPICEfor most practical loads.     

一种BTL低静态功耗CMOS音频功率放大器的设计

对AB类CMOS音频功率放大系统中的核心运放单元电路结构,即基于共漏与共源并联组合的功率级放大电路进行了改进与优化设计a基于CSMC0.6 μm CMOS工艺的仿真结果表明,在5 V电源电压下,静态电流仅为1.59 mA.BTL模式驱动4 Ω的负载,当1 kHz频率点的总谐波失真小于0.1%时,获得的最大输出功率可以达到2 W,电源转换效率为60.7%.     

双栅氧CMOS工艺研究

双栅氧工艺(dual gate oxide)在高压CMOS流程中得到了广泛的应用,此项工艺可以把薄栅氧器件和厚栅氧器件集成在同一个芯片上.文章介绍了常用的两种双栅氧工艺步骤并分析了它们的优劣.在此基础上,提出了一种实现双栅氧工艺的方法.