一种14位400MS/S分段型电流舵DAC的设计

基于TSMC O.25μm CMOS工艺,采用分段开关电流结构,设计了一种基于2.5 V电源电压的14位400MS/s D/A转换器.该D/A转换器内置高精度带隙基准源、高速开关驱动电路和改进的Cascode单位电流源电路,以提高性能.D/A转换器的积分非线性(INL)和微分非线性(DNL)均小于0.5 LSB.在400 MHz采样频率、199.8 MHz输出信号频率时,其无杂散动态范围(SFDR)达到85.4 dB.     

一种16位600 MS/s电流舵D/A转换器的设计

基于0.18 μm CMOS工艺,设计了一种16位600 MS/s电流舵D/A转换器。该D/A转换器为1.8 V/3.3 V双电源供电,采用并行输入、差分电流输出的四分段(5+4+3+4)电流舵结构。采用灵敏放大器型锁存器可以精确锁存数据,避免出现误码;由恒定负载产生电路和互补交叉点调整电路组成的同步与开关驱动电路,降低了负载效应引起的谐波失真,同时减小了输出毛刺;低失真电流开关消除了差分开关对共源节点处寄生电容对D/A转换器动态性能的影响。Spectre仿真验证结果表明,当采样频率为625 MHz,输入信号频率为240 MHz时,该D/A转换器的SFDR为78.5 dBc。     

电流模式算法型A/D转换器的电路结构研究

提出了一种基于电流模式的算法型A/D转换器电路结构,分析说明了其基本原理和具体实现方法;构造了一个6位50 MSPS算法型A/D转换器,给出了在OrCAD/PSpice 10.5下的仿真结果,得出用电流模式电路设计高速A/D转换器有优势的结论.     

10-bit 10Ms/S流水线A/D转换器的设计

在现有流水线A/D转换器设计的基础上,应用电荷泵改进了MOS模拟开关的性能,运用宽带运算放大器提高了电路速度,引入底极板采样和数字校正技术来提高精度,采用动态比较器实现较低的功耗.设计实现了一个10-bit 10Ms/S流水线A/D转换器,并以TSMC 0.35 CMOS工艺的Bsim 3v3模型用HSPICE对电路的性能进行仿真验证,结果表明其各项性能均达到预期的设计要求.     

一种超高速10位D/A转换器的设计

设计了一种超高速差分电流舵10位D/A转换器.该D/A转换器电路由8路分时复用器、5-31"温度计"译码器、快速转换电流开关和恒流源阵列等单元组成,采用0.35 μm SiGe BiCMOS标准工艺制造.该10位D/A转换器的数据更新率达到1 GSPS.介绍了电路实现原理和各单元的结构及设计思想,给出了电路仿真结果,并对实际电路进行了测试和分析.结果表明,该10位D/A转换器具有精度高、速度快、通用性强等优点.     

一种8通道12位逐次逼近式A/D转换器的设计

设计实现了一个8通道12位逐次逼近式A/D转换器。A/D转换器内部集成了多路复用器和并行到串行转换寄存器、复合型D/A转换器,实现数字位的串行输出。整体电路采用HSPICE进行仿真,转换速率为133 ksps(千次采样每秒),转换时间为7.5μs。通过低功耗设计,工作电流降低为2.8 mA。芯片基于0.6μm BiCMOS工艺完成版图设计,版图面积为2.5 mm×2.2 mm。     

高速电流舵D/A转换器技术发展动态

综合论述了高速电流舵结构D/A转换器设计中的多项关键技术。以近年发表的高速电流舵结构D/A转换器的论文和公开的专利为基础,以电流舵结构D/A转换器设计中所遇到的多种非理想因素为依据,分类介绍了每种关键技术的原理、特点,并给出评价,提出了这些技术在电路级实现时需要考虑的因素。     

8通道14位60MHz电流舵型D/A转换器

以电流舵型D/A转换器为核心,设计了一个8通道14位60MHz D/A转换器。采用三段电流源(5+4+5)结构的核心D/A转换器单元,有效地保证了转换器的精度和速度;利用电荷泵锁相环进行时钟倍频和多组时钟信号的相位同步,确保电路动态性能;通过输入级引入失调来获得具有迟滞特性的低压差分信号(LVDS)接收器,实现了840 Mb/s高频数据接口功能。电路采用CMOS工艺,在60MHz时钟频率,2MHz模拟输出频率下,功耗小于1 W,无杂散动态范围大于72dB。     

一种12位400 MHz电流开关型D/A转换器的设计

基于TSMC 0.25μm工艺、采用电流开关结构,设计了一个3.3 V 12位400 M采样率的D/A转换器。在电路中,设计了一种新的电压限幅结构,从而使其具有较好的动态性能。该D/A转换器在1 MHz输入信号下,无杂散动态范围(SFDR)达到83.75 dB;在12.5 MHz输入信号下,可获得70 dB的SFDR;在不同温度和工艺corner下,仿真得到的电路性能也都能达到上述指标。     

电潜泵测试仪的电流信号发生器设计

根据电潜泵测试仪的需要,提出一种基于TLV5637数模转换器的电流信号发生器电路设计方法。采用AT89C51模拟SPI通信访问TLV5637,将仪器采集到的数字信号转换为模拟电压信号,再通过电流环电路把模拟电压信号转化成电流信号。详细描述了硬件和软件的具体实现方案,其中包括微控制器与D/A转换器的接口连接与通信,电流环电路和软件基本代码。经过多次实验,结果表明该电流信号发生器能够准确产生所需的电流信号,完全满足仪器的要求并具有很高的精度和通用性。     

一种12位50 MHz电流舵结构D/A转换器的设计

设计了一种12位50 MHz BiCMOS D／A转换器，权衡面积和性能的关系，提出了4 8分段式的电流舵结构，并对所设计的电路进行了仿真，取得了很好的仿真结果。     

一种用于高精度D/A转换器的数字校准技术

介绍了一种用于400MSPS16位高精度电流舵D/A转换器的数字静态校准技术。该校准技术利用地址产生器、钟控比较器、SAR寄存器和校准DAC,构成逐次逼近式校准环路。利用该校准环路,可以自动完成高7位电流源阵列单元的校准,从而极大地提高电流源的匹配性。采用该校准技术的16位电流舵D/A转换器的DNL大于±0.5LSB,达到了真正的16位精度。     

基于滑模变结构的间接矩阵变换器—异步电机控制系统研究

传统的交直交变频调速系统由于带有中间直流环节大电容或大电感,使得它体积大。间接矩阵变换器中间直流环节没有大储能元件,增加了它的紧凑性,而且间接矩阵变换器正弦电流传入,正弦电压输出,该变换器整流级与逆变级协调控制,可以实现零电流换流。滑模变结构是一种非线性的控制方法,将其应用到矢量控制系统中,可以减少对系统参数的依赖性。仿真结果表明基于变结构的间接矩阵变换器驱动异步电机矢量控制系统能够获得良好的动静态性能。     

用于电流舵数模转换器中的静态校准技术

本文设计了一种静态校准技术,应用在一款14bits,100Msps的电流舵数模转换器(Digital - Analog Converter,DAC)中, 通过外加校准DAC,校准高位平均电流至低位平均电流,提高了整体DAC的静态性能,并能大大减小电流源阵列的面积,从而减小系统性失配误差。在文章最后给出了校准前后的仿真对比,证明了方法的可行性。     

A near-infrared heart rate measurement IC with very low cutoff frequency using current steering technique

A near-infrared heart-rate measurement IC that processes the photoplethysmographic signal was designed using a 0.35-/spl mu/m CMOS technology. The IC consists of a current-to-voltage (I-V) converter, a buffer, a sample-and-hold circuit, a second-order continuous-time low-pass filter (CT-LPF), a comparator, and a timing circuit that is used to pulse the external light-emitting diode with a very low duty cycle to reduce its power consumption. The current steering technique is employed in the design of the CT-LPF to meet the requirement for very low cutoff frequency. The circuit operates from a 3-V lithium battery, occupies a core area of 0.46 mm/sup 2/ and has a power consumption of 4.5 mW. The measurement results corroborate with simulation results and show that the CT-LPF can achieve a cutoff frequency of as low as 0.25 Hz. This demonstrates the feasibility of current steering technique in the design of filter for low-frequency application.     

Low-Power Approaches to High-Speed Current-Steering Digital-to-Analog Converters in 0.18-μm CMOS

This paper will discuss a number of circuit approaches which lower the power consumed by a current steering digital-to-analog converter while maintaining both DC and AC performance levels. An example design provides 14-bit resolution and 200 MSPS conversion rate in a one-poly four-metal (1P4M) 0.18-mum CMOS process. The inclusion of optional 3.3-V compatible devices allows operation over a supply range from 1.7 to 3.6 V. A power dissipation/conversion rate figure of merit of as low as 0.17 mW/MSPS was achieved for 1.8-V operation and as low as 0.28 mW/MSPS at 3.3 V. A measured single-tone SFDR of 70 dB is achieved at a 50-MHz output frequency, with a two-tone IMD of -75 dBc at 71 MHz output.     

基于巨磁致电阻电流检测机理的电流驱动同步整流器

本文将一种基于巨磁致电阻(Giant Magneto Resistive--GMR)的电流检测技术应用于同步整流技术中.该技术可以克服传统电流驱动同步整流器中电流检测器件损耗较大、不能测直流、漏感大、不能工作于高频等缺点.本文内容包括GMR电流检测技术原理和性能分析,GMR电流检测电流驱动同步整流正激变换器的实验研究.研究结果表明,该变换器工作性能理想,在轻载情况下效率有较大幅度的提高,说明GMR是一种可以实际应用的电流检测技术.     

A fixed-frequency modified series-resonant converter: analysis,design, and experimental results

It is shown that a fixed-frequency modified (LCL-type) series-resonant converter operates in five different modes with variations in the load current and the supply voltage. The converter is analyzed using the state-space approach for these operating modes. Both the general solutions and the steady-state solutions are obtained. Based on the analysis, design curves are obtained and a simple design procedure is illustrated using a design example. Detailed experimental results obtained from a MOSFET-based 500 W converter are presented to verify the analysis. It is shown that using a proper design, the converter operates only in modes 2 and 3, ensuring a lagging power factor mode of operation for very wide variations in the load and supply voltage     

Design of a laminated current cell relocation 12-bit CMOS D/A converter with a high output impedance technique and a merged switching logic

A compact and low power 12-bit 300 MS/s current steering CMOS D/A converter is presented. The architecture of the D/A converter is based on the current steering 6 + 6 segmented type with a laminated current cell relocation technique. In order to improve the linearity and glitch noise, a high output impedance analog current cell is designed. Furthermore, for the purpose of reducing the chip area and power dissipation, a noble merged switching logic and a compact layout technique are proposed. To verify its performance, the chip was fabricated with 0.13 μm thick-gate 1-poly 6-metal N-well Samsung CMOS technology. The effective chip area is 0.26 mm² (510 × 510 μm) with a power consumption of 100 mW. The measured INL and DNL are within ±3LSB and ±1LSB, respectively. The measured SFDR is about 70 dB, when the input frequency is 1 MHz at a clock frequency of 300 MHz.     

An 8-ns 1-Mbit ECL BiCMOS SRAM with double-latch ECL-to-CMOS-level converters

The design and performance of a high-speed 1 M*1-bit SRAM with ECL I/O are described. The 6.5*16.5-mm/sup 2/ chip was fabricated with a 0.8- mu m BiCMOS process technology. A modified double-word-line (MDWL) structure and a bit-line peripheral circuitry with normally-on bit-line equalization circuit are used to achieve high-speed read operation. The read speed is further enhanced by a novel ECL-to-CMOS-level converter with a double-latch configuration. The converter dissipates no DC current and contributes to low power consumption together with an automatic power-saving function, utilizing the address transition detection (ATD) technique. The access time is typically 8 ns, and the active power is 500 mW at 50 MHz.<>