2 GHz$rm Q$-Enhanced Active Filter With Low Passband Distortion and High Dynamic Range

A tunable$ Q$-enhanced filter with low passband distortion is presented. The$ Q$of the on-chip spiral inductors that form the filter resonators is enhanced by using a cross-coupled differential pair which is degenerated by a second LC tank. This technique allows for frequency dependent compensation of inductor losses and ensures that the$ Q$-enhanced LC resonators have a frequency behaviour close to the ideal in the passband of the filter. The circuit allows DC voltage control of$ Q$-enhancement. The filter centered at 2.0 GHz with a 130 MHz bandwidth is tunable in frequency by 3%, exhibits a$-hbox6.6~dBm$1-dB compression point and a 15 dB noise figure while consuming 17 mW of DC power. The circuit was fabricated in 0.18-$muhbox m$CMOS and the performance was verified experimentally.     

A superheterodyne receiver front-end with on-chip automatically Q-tuned notch filters

A superheterodyne receiver front-end with on-chip automatically Q-tuned notch filters is proposed. The front-end includes a differential LNA and a Gilbert down-converter, where each block is coupled with an on-chip image-rejection notch filter to get high image-rejection ratio. Each notch filter is formed by one on-chip LC network and one negative-resistance cross-coupled pair to compensate for the loss of the LC network. The current through the cross-coupled pairs is automatically adjusted by an automatic Q tuning circuit so that the loss of the notch filter is perfectly compensated to achieve a deepest notch. The automatic Q tuning circuit is an analog?Cdigital mixed signal circuit, and successive approximation register algorithm is used to search for the optimum current value. The superheterodyne receiver front-end has been implemented in 0.18???m CMOS. Experimental results show that the circuit could achieve an image rejection ratio of 75?dB with 105?MHz IF Frequency. The LNA draws 5.86?mA current, and the down-converter draws 1.27?mA current while two image-rejection filters and the master VCO totally draw 363???A current, all from a 1.8?V power supply.     

Design issues in CMOS differential LC oscillators

An analysis of phase noise in differential cross-coupled inductance-capacitance (LC) oscillators is presented. The effect of tail current and tank power dissipation on the voltage amplitude is shown. Various noise sources in the complementary cross-coupled pair are identified, and their effect on phase noise is analyzed. The predictions are in good agreement with measurements over a large range of tail currents and supply voltages. A 1.8 GHz LC oscillator with a phase noise of -121 dBc/Hz at 600 kHz is demonstrated, dissipating 6 mW of power using on-chip spiral inductors     

A 0.7-7 GHz wideband reconfigurable receiver RF front-end in CMOS

In this paper,a 0.7-7 GHz wideband RF receiver front-end SoC is designed using the CMOS process.The front-end is composed of two main blocks:a single-ended wideband low noise amplifier (LNA) and an inphase/quadrature (I/Q) voltage-driven passive mixer with IF amplifiers.Based on a self-biased resistive negative feedback topology,the LNA adopts shunt-peaking inductors and a gate inductor to boost the bandwidth.The passive down-conversion mixer includes two parts:passive switches and IF amplifiers.The measurement results show that the front-end works well at different LO frequencies,and this chip is reconfigurable among 0.7 to 7 GHz by tuning the LO frequency.The measured results under 2.5-GHz LO frequency show that the front-end SoC achieves a maximum conversion gain of 26 dB,a minimum noise figure (NF) of 3.2 dB,with an IF bandwidth of greater than 500 MHz.The chip area is 1.67 × 1.08 mm2.     

Low-power single-to-differential LNA at S-band based on optimised transformer topology and integrated ESD

A single-ended to differential low-power low-noise amplifier (LNA) designed and implemented in 0.18 mum CMOS technology is presented. The device takes advantage of a current reuse strategy by stacking two common-source differential transistor pair stages for minimum current dissipation, together with the design of optimised high Q differential transformers and inductors in order to minimise the impact of parasitics. The fully integrated, including ESD protection diodes, 2.1 GHz LNA consumes 1.1 mW at 1.2 V supply voltage and presents 29.8 dB gain, 4.5 dB noise figure, -21.1 dBm 1 dB compression point, -11.6 dBm input third-order intercept point and -12.3 dB input return loss performance.     

Implementation of a CMOS LNA plus mixer for GPS applications withno external components

A fully differential 0.35-μm CMOS LNA plus mixer, for GPS applications, using no external component apart from an input balun, has been realized. The LNA makes use of an inductively degenerated input stage and a resonant LC load, featuring 12% frequency tuning, accomplished by a MOS varactor. The mixer is a Gilbert cell type in which an NMOS and a PMOS differential pair, shunt together, realize the input stage. This topology allows one to save power for given mixer gain and linearity. The front-end measured performances are: 40-dB gain, 3.8-dB NF, -25.5-dBm IIP3, 1.3-GHz input frequency, 140-MHz output frequency, with 8 mA from a 2.8-V supply     

一款基于65nm CMOS工艺的高效率50GHz 压控振荡器及其电感耦合效应的研究

A 50 GHz cross-coupled voltage controlled oscillator(VCO) considering the coupling effect of inductors based on a 65 nm standard complementary metal oxide semiconductor(CMOS) technology is reported.A pair of inductors has been fabricated,measured and analyzed to characterize the coupling effects of adjacent inductors. The results are then implemented to accurately evaluate the VCO’s LC tank.By optimizing the tank voltage swing and the buffer’s operation region,the VCO achieves a maximum efficiency of 11.4%by generating an average output power of 2.5 dBm while only consuming 19.7 mW(including buffers).The VCO exhibits a phase noise of—87 dBc/Hz at 1 MHz offset,leading to a figure of merit(FoM) of-167.5 dB/Hz and a tuning range of 3.8%(from 48.98 to 50.88 GHz).     

A 0.1–20 GHz Low-Power Self-Biased Resistive-Feedback LNA in 90 nm Digital CMOS

In this letter, a 0.1–20 GHz low-power low noise amplifier (LNA) is presented. A novel self-biased resistive- feedback topology is proposed. Two inductors inside the feedback loop and a shunt-peaking inductor are exploited to extend the bandwidth. A PMOSFET with inductive degeneration is chosen as the load to boost the gain while maintaining low noise figure (NF) at high frequencies. A source-degeneration inductor is also introduced at the input transistor to ensure good input matching and stability over the entire bandwidth. All inductors are small due to the presence of feedback. The LNA was fabricated using a digital 90 nm CMOS process with 12.7 dB peak power gain, 3.3 dB minimum NF, and ${- 1}~{rm dBm}$ peak input-referred third-order intercept point (IIP3). With 12.6 mW power consumption and 0.12 ${rm mm}^{2}$ active area, this wideband LNA may replace distributed amplifiers (DAs) in many applications.      

Tunable LNA filter design using coupled-inductor Q-enhancement

A tunable LNA filter using Q-enhanced inductors is designed in 0.25 μm BiCMOS Qubic4x technology. The design employs the inductor degenerated LNA, acting as a transconductance which converts the input voltage to output current which drives the second-order Q-enhanced filter. The filter also uses a special technique based on coupled-inductor negative resistance generator to make the quality factor and the center frequency tunable. The overall gain of the LNA filter is about 19.5 dB and the minimum noise figure is 6.4 dB. The center frequency is 942.5 MHz with a 42 MHz (3 dB) bandwidth.     

Switched inductor dual-band CMOS cross-coupled VCO

This letter proposes a high-performance CMOS dual-band voltage-controlled oscillator (VCO). The VCO consists of two cross-coupled VCOs coupled by a pair of switched inductors or LC resonators to vary the resonator’s inductance. A pair of nMOSFET is used to switch high- and low-frequency bands. The VCO operates at the high-band using low resonator’s inductance and the VCO operates at the low-band using large inductance. The proposed VCO has been implemented with the TSMC 0.18 μm 1P6M CMOS technology and it can generate differential signals in the frequency range of 5.6–6.66 GHz and 4.13–4.75 and it also has comparable high output voltage swings at both low and high-frequency bands. The die area of the dual-band VCO is 0.84 × 1.1 mm². At the supply voltage of 0.75 V, the high (low)-band figure of merit is ?193.6 (?192.3) dBc/Hz.     

一种采用LC谐振电路的高频差分有源电感

提出了一种采用LC并联谐振电路的新型差分有源电感,实现了宽的工作频带、高的Q值、较大的电感值和可调谐功能.采用无源电感和MOS晶体管可变电容构成LC谐振电路,减小了等效串联电阻和等效并联电容,在增大电感值、Q值的同时,扩大了工作频带.仿真结果表明,在2～7.6 GHz频率范围内,该新型差分有源电感的电感值大于26 nH...     

伪工作点与超宽带CMOS LC VCO设计

为了拓宽CMOS LC VCO的频率覆盖范围,很多工作都集中在扩展LC谐振回路中的电容覆盖.但通过对该VCO在调频状态下的分析表明,除了LC乘积的覆盖范围,在改变输出频率时维持交叉耦合MOS管的工作状态稳定也是获得宽带振荡器的条件之一.固定尺寸的交叉耦合MOS管结构不能满足后一个条件.将交叉耦合MOS管结构分为可开关调节的若干段可以有效地解决上述问题.通过VHF超宽频带CMOS LC VCO的具体设计表明,新电路结构可以获得突破性的频率覆盖.     

Design of integrated low noise amplifiers (LNA) using embedded passives in organic substrates

The noise figure of a low noise amplifier (LNA) is a function of the quality factor of its inductors. The lack of high-Q inductors in silicon has prevented the development of completely integrated complementary metal oxide semiconductor (CMOS) LNAs for high sensitivity applications like global system for mobile communications (GSM) (1.9 GHz) and wideband code-division multiple-access (W-CDMA) (2.1GHz). Recent developments in the design of high-Q inductors (embedded in low cost integrated circuit (IC) packages) have made single-package integration of RF front-ends feasible. These embedded passives provide a viable alternative to using discrete elements or low-Q on-chip passives, for achieving completely integrated solutions. Compared to on-chip inductors with low Q values and discrete passives with fixed Q/sub s/, the use of these embedded passives also leads to the development of the passive Q as a new variable in circuit design. However, higher Q values also result in new tradeoffs, particularly with respect to device size. This paper presents a novel optimization strategy for the design of completely integrated CMOS LNAs using embedded passives. The tradeoff of higher inductor size for higher Q has been adopted into the LNA design methodology. The paper also presents design issues involved in the use of multiple embedded components in the packaging substrate, particularly with reference to mutual coupling between the passives and reference ground layout.     

A 2-dB noise figure 900-MHz differential CMOS LNA

This paper proposes a new circuit topology for RF CMOS low noise amplifier (LNA). Since pMOS devices are approaching the performances of nMOS devices in scaled technologies, the idea is to realize the input stage shunting an inductively degenerated nMOS stage with a pMOS one. In this way, due to the inherent current reuse, the performances can be improved using the same power consumption. Since the devices of an inductively degenerated input stage are working in moderate inversion (at least at moderate power dissipation), prior to the stage optimization an appropriate moderate inversion model is introduced. A fully differential 900-MHz 0.35-μm CMOS LNA (plus output buffer) prototype achieves the following performances: 2-dB noise figure (NF), 17.5-dB power gain, -6-dBm IIP3 with 8-mA current consumption from a 2.7-V voltage supply. To the author's knowledge, this is the lowest reported NF for a fully differential CMOS LNA operating at this power consumption level. As an additional feature, this LNA has a programmable gain     

改进型双频段低噪声放大器设计

设计了一种电流复用结构的双频段低噪声放大器,其中心频率为900 MHz和1 900 MHz。为减少芯片面积和提高电路性能,给出了一种改进的输入端和级间匹配网络,利用小电感LC网络代替大电感的栅极电感Lg和级间电感Ld1。仿真结果表明:该低噪放在两个需要的频带内功率增益(S21)大于16.0 dB;输入反射系数(S11)小于-18.6 dB;输出反射系数(S22)小于-12 dB;反向隔离(S12)小于-40 dB;噪声系数(NF)小于2.8 dB;线性度(IP3)大于-9.5 dBm。设计采用SMIC 0.18μmCMOS工艺,功耗为8.64 mW,电源电压1.8 V。     

A 20-GHz low-noise amplifier with active balun in a 0.25-/spl mu/m SiGe BICMOS technology

A 20-GHz low-noise amplifier (LNA) with an active balun fabricated in a 0.25-/spl mu/m SiGe BICMOS (f/sub t/=47 GHz) technology was presented by the authors in 2004. The LNA achieves close to 7 dB of gain and a noise figure of 4.9 dB with all ports simultaneously matched to 50 /spl Omega/ with better than -16 dB of return loss. The amplifier is highly linear with an IP/sub 1dB/ of 0 dBm and IIP/sub 3/ of 9 dBm, while consuming 14 mA of quiescent current from a 3.3-V rail, with temperature-compensated biasing. To the authors' knowledge, the LNA delivers the lowest reported noise figure and highest linearity for a silicon implementation of a combined active balun and LNA at 20 GHz, and is the first implementation of an active balun with an LC degenerated emitter-coupled pair. Here we expand on that work, with an analysis of the balun operation and noise optimization of the design.     

Design of differential low-noise amplifier with cross-coupled-SCR ESD protection scheme

The pin-to-pin electrostatic discharge (ESD) stress was one of the most critical ESD events for differential input pads. The pin-to-pin ESD issue for a differential low-noise amplifier (LNA) was studied in this work. A new ESD protection scheme for differential input pads, which was realized with cross-coupled silicon-controlled rectifier (SCR), was proposed to protect the differential LNA. The cross-coupled-SCR ESD protection scheme was modified from the conventional double-diode ESD protection scheme without adding any extra device. The SCR path was established directly from one differential input pad to the other differential input pad in this cross-coupled-SCR ESD protection scheme, so the pin-to-pin ESD robustness can be improved. The test circuits had been fabricated in a 130-nm CMOS process. Under pin-to-pin ESD stresses, the human-body-model (HBM) and machine-model (MM) ESD levels of the differential LNA with the cross-coupled-SCR ESD protection scheme are >8 kV and 800 V, respectively. Experimental results had shown that the new proposed ESD protection scheme for the differential LNA can achieve excellent ESD robustness and good RF performances.     

A capacitor cross-coupled common-gate low-noise amplifier

The conventional common-gate low-noise amplifier (CGLNA) exhibits a relatively high noise figure (NF) at low operating frequencies relative to the MOSFET f/sub T/, which has limited its adoption notwithstanding its superior linearity, input matching, and stability compared to the inductively degenerated common-source LNA (CSLNA). A capacitor cross-coupled g/sub m/-boosting scheme is described that improves the NF and retains the advantages of the CGLNA topology. The technique also enables a significant reduction in current consumption. A fully integrated capacitor cross-coupled CGLNA implemented in 180-nm CMOS validates the g/sub m/-boosting technique. It achieves a measured NF of 3.0 dB at 6.0 GHz and consumes only 3.6 mA from 1.8 V; the measured input-referred third-order intercept ( IIP3) value is 11.4 dBm. The capacitor cross-coupled g/sub m/-boosted CGLNA is attractive for low-power fully integrated applications in fine-line CMOS technologies.     

LC振荡器的设计要点

主要介绍了LC振荡器的设计要点.从LC振荡器的模型出发,研究了VCO的电路结构、谐振回路对于输出幅度的影响、VCO的噪声源、VCO的相位噪声以及谐振回路的Q值对于VCO的影响.给出了LC振荡器的设计要点及设计中需要考虑的约束条件.     

LC振荡器的设计要点

主要介绍了LC振荡器的设计要点. 从LC振荡器的模型出发，研究了VCO的电路结构、谐振回路对于输出幅度的影响、VCO的噪声源、VCO的相位噪声以及谐振回路的Q值对于VCO的影响. 给出了LC振荡器的设计要点及设计中需要考虑的约束条件.