Thermionic emission model for contact resistance in organic field-effect transistor

Injection mechanism of top-contact pentacene field-effect transistor (OFET) was investigated in respect to the internal field. The contact resistance was evaluated by the transmission line method for various applied external voltages as well as various pentacene film thicknesses. The behaviour of contact resistance was described in terms of the thermionic emission model (Schottky injection) and internal electric field generated by excess charges accumulated on pentacene–gate insulator interface. It was shown that pentacene film thickness changes the internal electric field affecting the carrier injection barrier. It was concluded that the space-charge field effect made a significant contribution for smaller pentacene film thicknesses and therefore in accordance to the thermionic model was able to decrease contact resistance representing the potential drop.     

Substrate- and oxidation-induced roughness of individual terraces of pentacene thin films

The roughness at the surface of individual pentacene terraces on naturally oxidized silicon wafers was investigated with scanning force microscopy as function of film thickness (one to five layers) and sample exposure to ambient air. For pristine samples, the root-mean-square roughness on individual (001) pentacene terraces was 0.18 nm and varied by less than 0.02 nm between monolayer terraces and terraces in the fifth layer. Storing samples in air and ambient light led to a substantial increase of the roughness, which for terraces up to the third layer became 0.24 nm after four weeks. For fourth layer terraces, the roughness increased less, and terraces in the fifth layer exhibited no significant roughness increase. We explain the roughness increase by photo-oxidation of pentacene, particularly strong within the first layer, which is supported by the appearance of grain boundary widening with storage time. The observation that layers beyond the third one from the substrate are less affected by photo-oxidation (smaller terrace roughness) is likely due to better structural perfection in layers farther from the substrate, which reduces the effective cross-section of molecules for oxidation. These results indicate that native silicon oxide does not allow for the immediate formation of structurally perfect pentacene films in the range of one to three layers, which will reduce charge carrier mobility in pentacene thin film transistors. Thicker pentacene layers can protect underlying layers against oxidation.     

Tuning the bipolar conductance of an alkali-doped C(60) layer sandwiched between two tunneling barriers

Resonant tunneling through a C(60) monolayer doped with single Na, K, Rb, and Cs atoms was measured between the tip of a scanning tunneling microscope and a NiAl(110) substrate. By supporting the monolayer on a thin aluminum oxide film grown on the substrate, a double barrier tunnel junction is formed, consisting of the vacuum and oxide. This geometry enables conductance through an electronic state of the alkali-C(60) complex at both positive and negative sample bias. The positions of the conductance peaks can be varied by tuning the vacuum barrier. An opposite variation is found for Na and K as compared to Rb and Cs, suggesting the influence of bonding on nanoscale transport.     

Aging effects and electrical stability in pentacene thin film transistors

We have studied the transfer characteristic variations induced by aging effects and applied voltage in top contact pentacene thin film transistors (OTFTs) fabricated by using Polymethylmetacrylate buffer layer. The electrical stability of pentacene OTFTs was tested by applying prolonged bias stress (up to 10⁴ s) with gate voltage V_gstress = − 30 V and + 30 V. The environmental effects were analysed by measuring the degradation of electrical characteristics of OTFT exposed to air. The results have been analysed in terms of trap state model, evaluating the channel conductance using a one-dimensional approach. This allows us to correlate the transfer characteristics variations to changes in localised state distribution.     

Probing and modeling of carrier motion in organic devices by optical second harmonic generation

We here report a novel optical second harmonic generation (SHG) measurement that allows an electric field formed in organic solid to be probed. We examined the SHG intensity profile that changes depending on a space charge field caused by carrier injection. Experiments making use of time-resolved SHG technique has revealed dynamic changes of SHG intensity profiles arising from pentacene, and that carrier transport in OFET was diffusion-like. Calculations using drift-diffusion equation well accounted for the visualized carrier motion probed by time-resolved SHG. That is, interface charge propagation process dominates the carrier transport, which is regulated by applied gate-source voltage.     

Bias stress effects on different dielectric surfaces of pentacene thin-film transistors

In this paper, it was demonstrated that pentacene thin-film transistors (TFTs) were fabricated with an organic adhesion layer between an organic semiconductor and a gate insulator. In order to form polymeric film as an adhesion layer, a vapor deposition polymerization (VDP) process was introduced to substitute for the usual spin-coating process. Field effect mobility, threshold voltage, and on/off current ratio in pentacene TFTs with a 15 nm thick organic adhesion layer were about 0.4 cm2/Vs, -1 V, and 10(6), respectively. We also demonstrated that threshold voltage strongly depends on the stress time when a gate voltage has been applied for bias stress test. We suggest that a polyimide adhesion layer fabricated by the VDP method can be applied to realize organic TFTs with long-term stability because of lower threshold voltage shifts due to reduced charge trapping at the interface between the pentacene semiconductor and the polyimide layer.     

Study of surface-modified PVP gate dielectric in organic thin film transistors with the nano-particle silver ink source/drain electrode

We have fabricated the flexible pentacene based organic thin film transistors (OTFTs) with formulated poly[4-vinylphenol] (PVP) gate dielectrics treated by CF4/O2 plasma on poly[ethersulfones] (PES) substrate. The solution of gate dielectrics is made by adding methylated poly[melamine-co-formaldehyde] (MMF) to PVP. The PVP gate dielectric layer was cross linked at 90 degrees under UV ozone exposure. Source/drain electrodes are formed by micro contact printing (MCP) method using nano particle silver ink for the purposes of low cost and high throughput. The optimized OTFT shows the device performance with field effect mobility of the 0.88 cm2/V s, subthreshold slope of 2.2 V/decade, and on/off current ratios of 1.8 x 10(-6) at -40 V gate bias. We found that hydrophobic PVP gate dielectric surface can influence on the initial film morphologies of pentacene making dense, which is more important for high performance OTFTs than large grain size. Moreover, hydrophobic gate dielelctric surface reduces voids and -OH groups that interrupt the carrier transport in OTFTs.     

Organic field-effect transistor/memory devices with pentacene/polydiacetylene composite film as active channel material: a morphology dependence study

Composite films of pentacene and poly(10,12-pentacosadiynoic acid) were prepared and used as the active channel material in a top-contact, bottom-gate field-effect transistor. The transistors exhibited high field-effect mobility as well as large I-V hysteresis as a function of gate bias history. The polydiacetylenic moieties incorporated in the pentacene film served as charge storage vehicles, which affected the threshold voltage shifts and created the electric bistability needed in a memory device. The memory window, response, and retention highly depend on the morphology of the polydiacetylene film buried under. Detailed film structure analyses and correlation with the transistor/memory property are provided.     

Processing and performance of organic insulators as a gate layer in organic thin film transistors fabricated on polyethylene terephthalate substrate

Fabrication of organic thin film transistor (OTFT) on flexible substrates is a challenge, because of its low softening temperature, high roughness and flexible nature. Although several organic dielectrics have been used as gate insulator, it is difficult to choose one in absence of a comparative study covering processing of dielectric layer on polyethylene terephthalate (PET), characterization of dielectric property, pentacene film morphology and OTFT characterization. Here, we present the processing and performance of three organic dielectrics, poly(4-vinylphenol) (PVPh), polyvinyl alcohol (PVA) and poly(methyl methacrylate) (PMMA), as a gate layer in pentacene-based organic thin film transistor on PET substrate. We have used thermogravimetric analysis of organic dielectric solution to determine annealing temperature for spin-coated films of these dielectrics. Comparison of the leakage currents for the three dielectrics shows PVA exhibiting lowest leakage (in the voltage range of ?30 to +30 V). This is partly because solvent is completely eliminated in the case of PVA as observed by differential thermogravimetric analysis (DTGA). We propose that DTGA can be a useful tool to optimize processing of dielectric layers. From organic thin film transistor point of view, crystal structure, morphology and surface roughness of pentacene film on all the dielectric layers were studied using X-ray diffraction (XRD), atomic force microscopy (AFM) and scanning electron microscopy (SEM). We observe pyramidal pentacene on PVPh whereas commonly observed dendritic pentacene on PMMA and PVA surface. Pentacene morphology development is discussed in terms of surface roughness, surface energy and molecular nature of the dielectric layer.     

Grain size increase in pentacene thin films prepared in low-pressure gas ambient

We studied a mechanism of grain size increase (that is, island density decrease) in pentacene film prepared in hydrogen (H₂) ambient. The island densities of pentacene films prepared in helium and deuterium were lower than those of vacuum-deposited films. This indicates that the decrease in the island density was not due to the chemical interaction between H₂ and pentacene or the substrate surface. Furthermore, the temperature dependence of the island density indicates that there is no difference in the surface diffusion energy in a vacuum and in H₂. We also improved mobility significantly in the pentacene thin film transistor fabricated on film grown in H₂ ambient on a chemically treated substrate.     

Preparation of pentacene thin film deposited using organic material auto-feeding system for the fabrication of organic thin film transistor

In this study, pentacene organic thin film was prepared using newly developed organic material auto-feeding system integrated with linear cell and characterized. The newly developed organic material auto-feeding system consists of 4 major parts: reservoir, micro auto-feeder, vaporizer, and linear cell. The deposition of organic thin film could be precisely controlled by adjusting feeding rate, main tube size, position and size of nozzle. 10 nm thick pentacene thin film prepared on glass substrate exhibited high uniformity of 3.46% which is higher than that of conventional evaporation method using point cell. The continuous deposition without replenishment of organic material can be performed over 144 hours with regulated deposition control. The grain size of pentacene film which affect to mobility of OTFT, was controlled as a function of the temperature.     

Ion beam deposition of α-Ta films by nitrogen addition and improvement of diffusion barrier property

Ta thin films were deposited on Si (100) substrates by an ion beam deposition method at various substrate bias voltages under Ar + N₂ atmosphere with different pressure ratios of Ar and N₂. The effects of nitrogen pressure in the plasma gas and the substrate bias voltage on the surface morphology, crystalline microstructure, electrical resistivity and diffusion barrier property were investigated. It was found that the fraction of a metastable β-phase in the Ta film deposited at the substrate bias voltage of − 50 V films decreased by adding nitrogen gas, while the α-Ta phase became dominant. As a result, the Ta films deposited at the substrate bias voltage of − 50 V under Ar (9 Pa) + N₂ (3 Pa) atmosphere showed a dominant α-phase with good surface morphology, low resistivity, and superior thermal stability as a diffusion barrier.     

The properties of heterojunction based on CuI/pentacene/Al

To improve the injection of charge carriers from ITO electrode into the molecular semiconductor in the pentacene-based photovoltaic structures, we propose introducing an additional transport copper iodide (CuI) layer with high conductivity. The organic flexible barrier based on ITO/CuI/pentacene/Al was fabricated using flexible polyethyleneterephtalate substrate with conductive ITO layer by vacuum deposition technique. CuI films, annealed at the temperature of 523 K, exhibited optical transmittance ∼80% in the wavelength range 400-900 nm, minimum resistivity about 1.8 × 10³ Ω/sq, and developed surface. They were used for fabrication of photosensitive barrier structure on the basis of pentacene.     

Study of electrical and microstructure properties of high dielectric hafnium oxide thin film for MOS devices

Hafnium oxide (HfO₂) has emerged as the most promising highkdielectric for MOS devices. As-deposited sputtered HfO₂ thin films have large number of defects resulting in increased oxide charge and leakage current. In this paper the effect of sputtering voltage, bias sputtering and post deposition thermal annealing is investigated. The I–V and C–V characteristics of the dielectric film are studied employing Al–HfO₂–Si MOS capacitor structure. It is found that oxide charge increases with increasing sputtering voltage. Thermal annealing in oxygen reduces the interface/oxide charges and leakage current. It is shown that applying substrate bias during film deposition leakage current is further reduced by an order of magnitude. The microstructure of thin film is examined by AFM. The reduction in surface roughness with bias sputtering is shown. The experimental results are presented and discussed for device application.     

Influence of substrate bias voltage on properties of Pt thin films deposited by non-mass separated ion beam deposition method

Pt thin films were deposited on Si substrates by applying a negative substrate bias voltage using a non-mass separated ion beam deposition method. The effect of the substrate bias voltage on the properties of the deposited films was investigated. In the case of Pt thin films deposited without the substrate bias voltage, a columnar structure and small grains were observed. The electrical resistivity of the deposited Pt films was very high (49.3 ± 0.65 µΩ cm). By increasing the substrate bias voltage, no clear columnar structure was observed. At the substrate bias voltage of − 75 V, the resistivity of the Pt film showed a minimum value of 16.9 ± 0.2 µΩ cm closed to the value of bulk (10.6 µΩ cm).     

Investigation of the gate-bias induced instability for InGaZnO TFTs under dark and light illumination

Mechanism of the instability for indium–gallium–zinc oxide thin film transistors caused by gate-bias stress performed in the dark and light illumination was investigated in this paper. The parallel V_t shift with no degradation of subthreshold swing (S.S) and the fine fitting to the stretched-exponential equation indicate that charge trapping model dominates the degradation behavior under positive gate-bias stress. In addition, the significant gate-bias dependence of V_t shift demonstrates that electron trapping effect easily occurs under large gate-bias since the average effective energy barrier of electron injection decreases with increasing gate bias. Moreover, the noticeable decrease of threshold voltage (V_t) shift under illuminated positive gate-bias stress and the accelerated recovery rate in the light indicate that the charge detrapping mechanism occurs under light illumination. Finally, the apparent negative V_t shift under illuminated negative gate-bias stress was investigated in this paper. The average effectively energy barrier of electron and hole injection were extracted to clarify that the serious V_t degradation behavior comparing with positive gate-bias stress was attributed to the lower energy barrier for hole injection.     

Space charge field effect on light emitting from tetracene field-effect transistor under AC electric field

By applying square wave AC voltage to the Au source electrode of tetracene based field-effect transistor (FET), electroluminescence (EL) was obtained. The results suggest that electrons and holes were injected alternately from the source electrode and recombined each other, and lead to the EL. This type of EL was localized at the interface between the source electrode and tetracene, and enhanced periodically with two relaxation times in accordance with the applied AC voltage cycle. We modeled the carrier behavior in the FET and explained the decay of EL, taking into account the space charge field contribution. Finally, using an AC voltage superposed on DC bias voltage, it was shown that electron injection was prompted only by space charge field.     

Si基多孔SiO2薄膜的驻极体性能

通过控制制备工艺条件和充电参数,利用相应条件下样品的等温表面电位衰减,开路热刺激放电电流谱等。考察了利用溶胶－凝胶（sol-gel)方法制备的Si基多孔SiO2薄膜的驻极体性能,分析了各种工艺参数与蓦主极体性质之间的联系,同时利用Gauss拟合及初始上升法对薄膜驻极体的电荷阱深度进行了估算,实验结果表明,反应物中水的含量对薄膜驻极体的陷阱分布具有调节作用,估算出负电晕充电SiO2薄膜驻极体电荷的活化能为0．3 eV和1．0eV;环境湿度对电荷储存稳定性有一定的影响,降低栅压可以提高SiO2薄膜驻极体的电荷储存稳定性。     

High performance flexible organic thin film transistors (OTFTs) with octadecyltrichlorsilane/ Al2O3/poly(4-vinylphenol) multilayer insulators

The incorporation of a thin, atomic layer deposited Al2O3 layer in between a spin-coated poly-4-vinyl phenol (PVP) organic layer and octadecyltrichlorsilane (OTS) in the multilayer gate dielectric for pentacene organic thin film transistors on a n(+)-Si substrate reduced the gate leakage current and thereby significantly enhanced the current on/off ratio up to 2.8 x 10(6). Addition of the OTS monolayer on the UV-treated Al2O3 improved the crystallinity of the pentacene layer, where the OTS/UV-treated Al2O3 surfaces increased their contact angles to 100 degrees. X-ray diffraction (XRD) analysis revealed a more intense (001) crystal reflectance of pentacene deposited on OTS/UV-treated Al2O3 surface than that on OTS/Al2O3 surface. Moreover, the improved pentacene layer contributed to the field effect mobility (0.4 cm2/Vs) and subsequently improved the electrical performances of organic thin film transistor (OTFT) devices. This PVP/UV treated Al2O3/OTS multilayer gate dielectric stack was superior to those of the device with the single PVP gate dielectrics due to the improved crystallinity of pentacene.     

Instability of threshold voltage under constant bias stress in pentacene thin film transistors employing polyvinylphenol gate dielectric

The instability of threshold voltage and mobility of pentacene thin film transistors using a poly(4-vinylphenol) gate dielectric have been investigated under constant bias stress. The mobility was very stable in vacuum by exhibiting 2% variation after 6 h stress even under the high gate bias stress of V_GS = − 20 V. Meanwhile, we observe a negative shift of threshold voltage under stress in vacuum. This shift is attributed to charges trapped in deep electronic states in pentacene near the gate interface. We propose a model for the negative shift of the threshold voltage and extract the hole concentration, 4.5 × 10¹¹ cm^− 2, needed to avoid the onset of stress effects, resulting in a design rule of the channel width to length ratio larger than 40.