Finishing of AT-cut quartz crystal wafer with nanometric thickness uniformity by pulse-modulated atmospheric pressure plasma etching

Quartz resonator is a very important device to generate a clock frequency for information and telecommunication system. Improvement of the productivity of the quartz resonator is always required because a huge amount of the resonator is demanded for installing to various electronic devices. Resonance frequency of the quartz resonator is decided by the thickness of the quartz crystal wafer. Therefore, it is necessary to uniform the thickness distribution of the wafer with nanometric level. We have proposed the improvement technique of the thickness distribution of the quartz crystal wafer by numerically controlled correction using atmospheric pressure plasma which is non-contact and chemical removal technique. Heating effects of the quartz wafer in the removal rate and the correction accuracy were investigated. The heating of the substrate and compensate of the scanning speed of the worktable according to the variation of the surface temperature enabled an increase of 50% in the etching rate and 10-nanometric-level accuracy in the correction of the thickness distribution of the quartz wafer, respectively.     

Wafer-scale fabrication of polymer-based microdevices via injection molding and photolithographic micropatterning protocols

Because of their broad applications in biomedical analysis, integrated, polymer-based microdevices incorporating micropatterned metallic and insulating layers are significant in contemporary research. In this study, micropatterns for temperature sensing and microelectrode sets for electroanalysis have been implemented on an injection-molded thin polymer membrane by employing conventional semiconductor processing techniques (i.e., standard photolithographic methods). Cyclic olefin copolymer (COC) is chosen as the polymer substrate because of its high chemical and thermal stability. A COC 5-in. wafer (1-mm thickness) is manufactured using an injection molding method, in which polymer membranes (approximately 130 microm thick and 3 mm x 6 mm in area) are implemented simultaneously in order to reduce local thermal mass around micropatterned heaters and temperature sensors. The highly polished surface (approximately 4 nm within 40 microm x 40 microm area) of the fabricated COC wafer as well as its good resistance to typical process chemicals makes it possible to use the standard photolithographic and etching protocols on the COC wafer. Gold micropatterns with a minimum 5-microm line width are fabricated for making microheaters, temperature sensors, and microelectrodes. An insulating layer of aluminum oxide (Al2O3) is prepared at a COC-endurable low temperature (approximately 120 degrees C) by using atomic layer deposition and micropatterning for the electrode contacts. The fabricated microdevice for heating and temperature sensing shows improved performance of thermal isolation, and microelectrodes display good electrochemical performances for electrochemical sensors. Thus, this novel 5-in. wafer-level microfabrication method is a simple and cost-effective protocol to prepare polymer substrate and demonstrates good potential for application to highly integrated and miniaturized biomedical devices.     

Terahertz-Wave Antireflection Coating on Ge and GaAs with Fused Quartz

In the terahertz-wave region, fabrication of an antireflection (AR) coating is difficult because it must be as thick as several tens of micrometers, which is far thicker than that used in the optical region. We discuss a lapping method for fabricating an AR layer with a desired thickness for terahertz-wave optical devices. To demonstrate this method, we glued a thin fused-quartz plate to a surface of an undoped Ge or GaAs wafer and polished it to a thickness of one-quarter wavelength. This reduced the reflectivity of the AR surface to 1/720 of the reflection of an uncoated surface, as expected from optical theory.     

Transfer of single crystalline silicon nanolayer onto alien substrate

Starting from the 60-nm node, future generations of mainstream semiconductor devices (i.e., CMOS) will be mostly manufactured from silicon-on-insulator (SOI) initial substrates with the top silicon layer having a thickness 50 nm or less. We describe a process that is capable for transfer of nanoscale thick layers. The layer is delaminated from a single crystalline silicon substrate and laminated onto another substrate, thus resulting in SOI. The process includes: 1) forming a trap layer for hydrogen in an initial substrate; 2) delivery of hydrogen to the traps by diffusion of monatomic hydrogen; 3) evolving the trapped hydrogen into a layer of hydrogen platelets; 4) stiffening of the surface of the initial substrate by laminating to another substrate; and 5) delaminating a layer from the initial substrate along the hydrogen platelet layer. Details of the new layer transfer process are described. A depth where the buried trap layer locates is critical for the process. An implantation of heavy ions is used to form the trap layer. A trap capacity for hydrogen is evaluated as a function of implantation conditions. Plasma hydrogenation is used to deliver atomic hydrogen to the traps. Electron cyclotron resonance, microwave, RF, and dc plasma are compared as the hydrogenation sources. Dependence of a thickness of a transferred layer as a function of the mass of implanted ions and implantation energy is described. Types of layer transfer faults are also described. Mechanisms of the layer transfer faults are suggested. We discuss limits of scaling down of the thickness of the layer that is transferred from one substrate to another. The scaling limit of our process is compared to the limits of other (SIMOX, Smart-Cut, and ELTRAN) processes.     

Ultrathin Crystalline Silicon Nano and Micro Membranes with High Areal Density for Low-Cost Flexible Electronics

Ultrathin crystalline silicon is widely used as an active material for high-performance, flexible, and stretchable electronics, from simple passive and active components to complex integrated circuits, due to its excellent electrical and mechanical properties. However, in contrast to conventional silicon wafer-based devices, ultrathin crystalline silicon-based electronics require an expensive and rather complicated fabrication process. Although silicon-on-insulator (SOI) wafers are commonly used to obtain a single layer of crystalline silicon, they are costly and difficult to process. Therefore, as an alternative to SOI wafers-based thin layers, here, a simple transfer method is proposed for printing ultrathin multiple crystalline silicon sheets with thicknesses between 300 nm to 13 µm and high areal density (>90%) from a single mother wafer. Theoretically, the silicon nano/micro membrane can be generated until the mother wafer is completely consumed. In addition, the electronic applications of silicon membranes are successfully demonstrated through the fabrication of a flexible solar cell and flexible NMOS transistor arrays.     

Development of numerically controlled local wet etching

Numerically controlled local wet etching (NC-LWE) has been developed as a novel noncontact subaperture deterministic figuring method for fabricating ultraprecision optics or for finishing functional materials. In this method, a localized wet etching area is formed using a combined nozzle that is constructed by coaxially arranging the supply part and the suction part of the etchant. The removal volume anywhere on the workpiece surface is determined by the convolution of the removal function and the dwelling time distribution of the nozzle. The machining properties of this method are insensitive to external disturbances, such as vibration or thermal deformation, because the removal process is performed under a noncontact condition.I applied NC-LWE to finish a 6 in photomask substrate made of synthesized quartz glass having size of 6 in, and improved the flatness of the substrate from 260 to 69 nm by only one NC-LWE correcting process.     

Hybrid silicon integration

An overview is presented of the hybrid AlGaInAs-silicon platform that enables wafer level integration of III-V optoelectronic devices with silicon photonic devices based on silicon-on-insulator (SOI). Wafer bonding AlGaInAs quantum wells to an SOI wafer allows large scale hybrid integration without any critical alignment steps. Discrete hybrid silicon optical amplifiers, lasers and photodetectors are described, and the integration of a ring laser with on-chip and photo-detector and amplified spontaneous emission (ASE) seed to enable unidirectional lasing.     

The stress analysis of Si MEMS devices by micro-Raman technique

In this paper, the micro-Raman technique was used to measure the residual stress and its variation in Si MEMS devices and carried out on two platforms. Firstly, it was observed that there is a good correlation between the wafer's centre deflection and Raman shift. Secondly, using diaphragms fabricated from a SOI wafer, it was observed that a thinner diaphragm results in more Raman shift and vice versa. After a thin metal film layer (Cr/Au) is sputtered onto the diaphragm, it was observed that the Raman shift is more significant as the metal layer represents an amplification effect. These results show that the micro-Raman technique is a powerful method to investigate the residual stress of Si MEMS devices, especially how the stress changes during the fabrication process. All these could help select and optimize the fabrication parameters during the device manufacturing process.     

Quantum mechanical device modeling: FinFET having an isolated n+/p+ gate region strapped with poly-silicon

In this paper, we present our numerical study on FinFET having an isolated n+/p+ gate region strapped with metal and poly-silicon structure. Our theoretical work is based on 2-D quantum-mechanical simulator with a self-consistent solution of Poisson-Schr?dinger equation. Our numerical simulation revealed that the threshold voltage (VT) is controlled within -0.1 approximately +0.2 V with varying the doping concentration of the n+ and p+ polysilicon gate region from 1.0 x 10(17) to 1.0 x 10(18) cm(-3). We also confirmed that the better VT tolerance of the FinFET on the variation of the fin thickness can be expected over the conventional FinFET structure. For instance, the VT of the FinFET under this work exhibited 0.02 V tolerance with respect to the variation of the fin thickness change of 5 nm (from 30 to 35 nm) while the traditional FinFET demonstrates the tolerance of 0.12 V for the same variation of the fin thickness.     

Ultra fast and parsimonious materials screening for polymer solar cells using differentially pumped slot-die coating

We present a technique that enables the probing of the entire parameter space for each parameter with good statistics through a simple roll-to-roll processing method where gradients of donor, acceptor, and solvent are applied by differentially pumped slot-die coating. We thus demonstrate how the optimum donor-acceptor ratio and device film thickness can be determined with improved accuracy by varying the composition in small steps. We give as an example P3HT-PCBM devices and vary the composition between P3HT and PCBM in steps of 0.5-1% giving 100-200 individual solar cells. The coating experiment itself takes less than 4-8 min and requires 15-30 mg each of donor and acceptor material. The optimum donor-acceptor composition of P3HT and PCBM was found to be a broad maximum centered on a 1:1 ratio. We demonstrate how the optimal thickness of the active layer can be found by the same method and materials usage by variation of the layer thickness in small steps of 1.5-4 nm. Contrary to expectation we did not find oscillatory variation of the device performance with device thickness because of optical interference. We ascribe this to the nature of the solar cell type explored in this example that employs nonreflective or semitransparent printed electrodes. We further found that very thick active layers on the order of 1 μm can be prepared without loss in performance and estimate the active layer thickness could easily approach 4-5 μm while maintaining photovoltaic properties.     

氢氧复合注入对SOI-SIMOX埋层结构影响的研究

实验研究了氢、氧复合注入对注氧隔离技术制备SOI（Silicon On Insulator)材料埋层结构的影响。用截面透射电子显微镜和二次离子质谱技术分析了退火前后材料的微结构变化。研究表明，氢离子的注入有利于注氧隔离制备的SOI材料埋层的增宽。进一步的结果表明，室温氢离子注入导致的增宽效应比高温注入明显。     

Fabrication and characterization of micromachined high-frequency tonpilz transducers derived by PZT thick films

Miniaturized tonpilz transducers are potentially useful for ultrasonic imaging in the 10 to 100 MHz frequency range due to their higher efficiency and output capabilities. In this work, 4 to 10-microm thick piezoelectric thin films were used as the active element in the construction of miniaturized tonpilz structures. The tonpilz stack consisted of silver/lead zirconate titanate (PZT)/lanthanum nickelate (LaNiO3)/silicon on insulator (SOI) substrates. First, conductive LaNiO3 thin films, approximately 300 nm in thickness, were grown on SOI substrates by a metalorganic decomposition (MOD) method. The room temperature resistivity of the LaNiO3 was 6.5 x 10(-6) omega x m. Randomly oriented PZT (52/48) films up to 7-microm thick were then deposited using a sol-gel process on the LaNiO3-coated SOI substrates. The PZT films with LaNiO3 bottom electrodes showed good dielectric and ferroelectric properties. The relative dielectric permittivity (at 1 kHz) was about 1030. The remanent polarization of PZT films was larger than 26 microC/cm2. The effective transverse piezoelectric e31,f coefficient of PZT thick films was about -6.5 C/m2 when poled at -75 kV/cm for 15 minutes at room temperature. Enhanced piezoelectric properties were obtained on poling the PZT films at higher temperatures. A silver layer about 40-microm thick was prepared by silver powder dispersed in epoxy and deposited onto the PZT film to form the tail mass of the tonpilz structure. The top layers of this wafer were subsequently diced with a saw, and the structure was bonded to a second wafer. The original silicon carrier wafer was polished and etched using a Xenon difluoride (XeF2) etching system. The resulting structures showed good piezoelectric activity. This process flow should enable integration of the piezoelectric elements with drive/receive electronics.     

Site-specific and patterned growth of TiO(2) nanotube arrays from e-beam evaporated thin titanium film on Si wafer

Growth of TiO(2) nanotubes on thin Ti film deposited on Si wafers with site-specific and patterned growth using a photolithography technique is demonstrated for the first time. Ti films were deposited via e-beam evaporation to a thickness of 350-1000?nm. The use of a fluorinated organic electrolyte at room temperature produced the growth of nanotubes with varying applied voltages of 10-60?V (DC) which remained stable after annealing at 500?°C. It was found that variation of the thickness of the deposited Ti film could be used to control the length of the nanotubes regardless of longer anodization time/voltage. Growth of the nanotubes on a SiO(2) barrier layer over a Si wafer, along with site-specific and patterned growth, enables potential application of TiO(2) nanotubes in NEMS/MEMS-type devices.     

Synthesis and characterization of silica aerogel films for inter-metal dielectrics via ambient drying

Low-dielectric silica aerogel films could be synthesized via solvent exchange-ambient drying of wet gel films that were obtained by spin-coating the isopropanol based silica sol on a p-Si (100) wafer. Using isopropanol as a drying solvent, the thickness and the dielectric constant of silica films significantly changed from 1100 nm to 350 nm and from 2.1 to 3.6, respectively, with the drying pressure of [8 MPa (270 °C)→2.6 MPa (200 °C)]. However, when isopropanol in pores was exchanged with n-heptane followed by ambient drying technique, the aerogel films had 1350 nm thickness, 80% porosity, and 2.0 dielectric constant, regardless of the drying pressure. The degree of planarization and the gap filling capability on 0.7 μm tungsten patterning wafer were excellent. It was proven that the ambient-dried aerogel films have a possibility of an application to IMD (inter-metal dielectrics) materials in the next generation of semiconductor devices beyond the giga level.     

Microelectromechanical system pressure sensor integrated onto optical fiber by anodic bonding

Optical microelectromechanical system pressure sensors based on the principle of Fabry-Perot interferometry have been developed and fabricated using the technique of silicon-to-silicon anodic bonding. The pressure sensor is then integrated onto an optical fiber by a novel technique of anodic bonding without use of any adhesives. In this anodic bonding technique we use ultrathin silicon of thickness 10 microm to bond the optical fiber to the sensor head. The ultrathin silicon plays the role of a stress-reducing layer, which helps the bonding of an optical fiber to silicon having conventional wafer thickness. The pressure-sensing membrane is formed by 8 microm thick ultrathin silicon acting as a membrane, thus eliminating the need for bulk silicon etching. The pressure sensor integrated onto an optical fiber is tested for static response, and experimental results indicate degradation in the fringe visibility of the Fabry-Perot interferometer. This effect was mainly due to divergent light rays from the fiber degrading the fringe visibility. This effect is demonstrated in brief by an analytical model.     

Measuring the thickness profiles of wafers to subnanometer resolution using Fabry-Perot interferometry

The resolution of an angle-scanning technique for measuring transparent optical wafers is analyzed, and it is shown both theoretically and experimentally that subnanometer resolution can be readily achieved. Data are acquired simultaneously over the whole area of the wafer, producing two-dimensional thickness variation maps in as little as 10 s. Repeatabilities of 0.07 nm have been demonstrated, and wafers of up to 100 mm diameter have been measured, with 1 mm or better spatial resolution. A technique for compensating wafer and system aberrations is incorporated and analyzed.     

Fast interface characterization of tunnel oxide MOS structures

As new gate materials become increasingly interesting in conjunction with tunnel oxides, a fast and reliable interface characterization technique becomes indispensable. Fast turnaround times require a method which can be applied to simple test structures like planar capacitors. For the first time, we demonstrate an automatic extraction of physical oxide thickness and flatband potential from capacitance-voltage measurements which includes quantum confinement effects and Fermi-Dirac statistics. Automatic extraction is necessary for uniformity analysis across a whole wafer. New gate materials are typically binary or ternary alloys where the interface to the gate dielectric is very sensitive to deposition parameters. Such systems are likely to show higher nonuniformities than polysilicon electrodes. An example is presented where polysilicon gates exhibit a uniformity in flatband potential within a wafer of less than /spl plusmn/15 mV while a thickness variation of 0.1 nm has been observed.     

Controlling gate-CD uniformity by means of a CD prediction model and wafer-temperature distribution control

A technique for predicting wafer temperature was developed, and a model for predicting critical dimension (CD) was devised. Using this technique and model in combination makes it possible to calculate wafer temperature during gate etching within an accuracy of 1 °C and to predict CD distribution after plasma etching. Etching at a temperature for uniform CD given by the CD prediction model reduces the CD variation (3σ) during gate etching from 2.3 to 1.5 nm. Applying this temperature prediction technique and CD prediction model together will contribute to improving etching apparatus design and process development.     

低剂量SOI圆片的无损电学表征测试

通过应用一种新的模型来进行电学测试和参数提取，可以获取SIMOX（离子束注入隔离氧化层）SOI圆片的上界面和下界面的界面态参数以及埋氧层的质量参数，传统的MOS电容结构测试电学特性应用到SOI圆片是有其局限性的，在本实验中直接利用SOI圆片的SIS（Silicon-Insulator-Silicon)结构，将SOI圆片的无损电学表征方法应用到实际的表征当中去，实验采用自行制备的低剂量超薄SIMOXSOI圆片，得到比较可靠的实验结果。     

Highly efficient damage-free correction of thickness distribution of quartz crystal wafers by atmospheric pressure plasma etching - [letters]

A new finishing method was developed to correct the thickness distribution of a quartz crystal wafer by the numerically controlled scanning of a localized atmospheric pressure plasma. The thickness uniformity level of a commercially available AT-cut quartz crystal wafer was improved to less than 50 nm without any subsurface damage by applying one correction process. Furthermore, applying a pulse-modulated plasma markedly decreased the correction time of the thickness distribution without breaking the quartz crystal wafer by thermal stress.