Mixer for low voltage operation

A very high conversion gain mixer of frequency 350 MHz is designed using the injection-locked technique. The mixer is based on a common-base Clapp oscillator which is free-running at a frequency of 350 MHz. Using the injection-locked technique, the nonlinear resistance of the oscillator is modulated by the injection source which provides negative resistance amplification to the RF signal. It gives conversion gain as high as 30 dB with good noise performance     

An SOI-DRAM with wide operating voltage range by CMOS/SIMOXtechnology

An SOI-DRAM test device (64-Kb scale) with 100-nm-thick SOI film has been fabricated in 0.5-μm CMOS/SIMOX technology and the basic DRAM function has been successfully observed. A partially depleted transistor was used to solve the floating-body effect, resulting in improved operation. The newly introduced body-synchronized sensing scheme enhances the lower Vcc margin. The p-n junction capacitance between source/drain and a substrate for SOI structure is reduced by 25%. RAS access time tRAC is 70 ns with a 2.7-V power supply, which is as fast as the equivalent bulk-Si device with a 4-V power supply. The active current consumption is 1.1 mA (Vcc=3.0 V, 260-ns cycle) for this SOI-DRAM, which is a reduction of 65%, compared with 3.2 mA for the reference bulk-Si DRAM. The mean value of data retention time for this chip at 80°C is longer than 20 s (Vcc=3.3 V), which is the same value as mass-produced 16-Mb DRAM's. The SOI-DRAM has an operating Vcc range from 2.3 V to 4.0 V. The observed speed enhancement and the wide operating voltage range indicate high performance at the low voltage operation suitable for battery-operated DRAM's     

Tunable allpass filter for low voltage operation

A novel high-performance first-order allpass filter with electronically adjustable filter parameters is presented. The core of the circuit is an inverting unity gain amplifier with electronically adjustable output resistance, which leads to an allpass filter realisation with tunable time constant. The circuit is composed of a simple CMOS cascode circuit and a level shifter and is also very suitable for low voltage operation, since it employs two active devices between its rails. SPICE simulation and experimental results verifying theoretical analyses are also given.     

Dual-regulator dual-decoding-trimmer DRAM voltage limiter forburn-in test

The authors present a dynamic RAM (DRAM) voltage limiter with a burn-in test mode. It features a dual-regulator dual-trimmer scheme that provides a precise stress voltage in a burn-in test while maintaining a constant limited voltage under normal operation. A regulator is used to preserve a constant difference between the internal burn-in voltage and the supply voltage. Two sets of trimmers reduce the voltage deviations of both the burn-in and normal-operation voltages within ±0.13 V. The circuits are implemented in a 16-Mb CMOS DRAM. A burn-in voltage regulated to ±50 mV at an ambient temperature up to 120°C is obtained simply by elevating the supply voltage to 8 V as in conventional burn-in procedures     

Energy-efficient strategy for work node by DRAM voltage regulation in storm

Focused on the problem that traditional energy-efficient strategies never consider about the real time of data processing and transmission,models of directed acyclic graph,parallelism of instance,resource allocation for task and critical path were set up based on the features of data stream processing and the structure of storm cluster.Meanwhile,the WNDVR-storm (energy-efficient strategy for work node by dram voltage regulation in storm) was proposed according to the analysis of critical path and system performance,which included two energy-efficient algorithms aiming at whether there were any work nodes executing on the non-critical path of a topology.Finally,the appropriate threshold values fit for the CPU utilization of work node and the volume of transmitted data were determined based on the data processing and transmission constraints to dynamically regulate the DRAM voltage of the system.The experimental result shows that the strategy can reduce energy consumption effectively.Moreover,the fewer constraints are,the higher energy efficiency is.     

SOI-DRAM circuit technologies for low power high speed multigigascale memories

This paper describes a silicon on insulator (SOI) DRAM which has a body bias controlling technique for high-speed circuit operation and a new type of redundancy for low standby power operation, aimed at high yield. The body bias controlling technique contributes to super-body synchronous sensing and body-bias controlled logic. The super-body synchronous sensing achieves 3.0 ns faster sensing than body synchronous sensing and the body-bias controlled logic realizes 8.0 ns faster peripheral logic operation compared with a conventional logic scheme, at 1.5 V in a 4 Gb-level SOI DRAM. The body-bias controlled logic also realizes a body-bias change current reduction of 1/20, compared with a bulk well-structure. A new type of redundancy that overcomes the standby current failure resulting from a wordline-bitline short is also discussed in respect of yield and area penalty     

Advanced controlling scheme for a DRAM voltage generator system

An brief overview is given of the voltage generator system of a 1-Gb synchronous DRAM. The design serves as an example for a state-of-the-art DRAM voltage generator system. A general analysis of the required controlling functionality is derived. A universal and flexible controlling scheme for a voltage generator system is presented, which can easily be modified for future voltage generator design. The main aspect of this controlling scheme is a clear separation between logic (digital) controlling functions and (analog) voltage generating functions. A control path that supplies the various voltage generator blocks with configuration information is introduced. Last, the control path is shown to have an additional advantage of increased testability. Hardware results verifying the concept are presented     

Piezoelectrically actuated RF MEMS DC contact switches with low voltage operation

In this paper, fully integrated radio frequency (RF) microelectromechanical system (MEMS) switches with piezoelectric actuation have been proposed, designed, fabricated, and characterized. At a very low operation voltage of 2.5V, reliable and reproducible operation of the fabricated switch was obtained. The proposed RF MEMS switch is comprised of a piezoelectric cantilever actuator with a floated contact electrode and isolated CPW transmission line suspended above the silicon substrate. The measured insertion loss and isolation of the fabricated piezoelectric switch are -0.22 dB and -42dB at a frequency of 2GHz, respectively.     

A 34-ns 16-Mb DRAM with controllable voltage down-converter

A high-speed 16-Mb DRAM with high reliability is reported. A multidivided column address decoding scheme and a fully embedded sense-amplifier driving scheme were used to meet the requirements for high speed. A low-power hybrid internal power supply voltage converter with an accelerated life-test function is also proposed and was demonstrated. A novel substrate engineering technology, a retrograded well structure formed by a megaelectronvolt ion-implantation process, provides a simple process sequence and high reliability in terms of soft error and latch-up immunity.<>     

High mobility and low operation voltage organic field effect transistors by using polymer-gel dielectric and molecular doping

In this work, we present a method to increase the performance in solution processed organic field effect transistors (OFET) by using gel as dielectric and molecular doping to the active organic semiconductor. In order to compare the performance improvement, Poly (methylmethacrylate) (PMMA) and Poly (3-hexylthiophene-2,5-diyl) P3HT material system were used as a reference. Propylene carbonate (PC) is introduced into PMMA to form the gel for using as gate dielectric. The mobility increases from 5.72×10⁻³ to 0.26 cm² V s^–1 and operation voltage decreases from −60 to −0.8 with gel dielectric. Then, the molecular dopant 2,3,5,6-tetrafluoro-7,7,8,8-tetracyanoquinodimethane (F4-TCNQ) is introduced into P3HT via co-solution. The mobility increases up to 1.1 cm² V s^–1 and the threshold voltage downs to −0.09 V with doping. The increase in performance is discussed in terms of better charge inducing by high dielectric properties of gel and trap filling due to the increased carrier density in active semiconductor by molecular doping.     

一种低压APF和TSC并联最优运行的方法

针对低压电网中传统有源电力滤波器(APF)和晶闸管投切电容器(TSC)简单并联运行时出现的系统不稳、TSC频繁投切等问题,提出了一种基于FBD法的统一APF和TSC且共用电抗器的控制方法。该方法只通过一个控制器同时计算出APF的补偿指令电流和TSC投切组数控制信号。通过负载电流的变化率dILq/dt判断负载是否处于暂态过程,来决定是否更新TSC的投切状态,从而避免TSC的频繁投切和系统振荡。共用电抗器的拓扑结构还能节约经济成本,减小装置体积。通过仿真实验,验证了系统的可行性及有效性,是一种高性价比且性能优良的无功及谐波补偿方法。     

0.4kV低压配电线路长期过载运行产生的后果

电力企业为社会快速发展、人民正常生活提供保障.0.4kV低压配电线路对电力系统具有重要作用,但其经常因过载运行而发生线路故障.本文以0.4kV低压配电线路为研究对象,分析其长期过载运行产生的后果,并提出控制建议.     

无电阻低压低温漂的CMOS基准电压源

结合工作在亚阈值区、饱和区和线性区的MOS管,提出一种纯MOS结构的基准电压源,其结构能有效补偿MOS管的栽流子迁移率和亚闽值斜率的温度系数。基于SMIC0．13μm的CMOS工艺的仿真结果表明,在-5-90℃的范围内。输出电压的温度系数为5ppm／℃。在室温时,整个电路能在低到0．9V的电源电压下工作并消耗0．68μW的功耗。     

无电阻低压低温漂的CMOS基准电压源

结合工作在亚阈值区、饱和区和线性区的MOS管,提出一种纯MOS结构的基准电压源,其结构能有效补偿MOS管的载流子迁移率和亚阈值斜率的温度系数.基于SMIC 0.13 μm的CMOS工艺的仿真结果表明,在温度为-55～90 ℃的范围内,输出电压的温度系数为5 ppm/℃.在室温时,整个电路能在低到0.9 V的电源电压下工作并消耗0.68 μW的功耗.     

A 64K DRAM with 35 ns static column operation

A 64K dynamic RAM with a function mode similar to static memory operation is described. The device has multiplexed address inputs and a one-address strobe clock (RAS). After a row address is applied to the device, column selection is performed as in static memory, resulting in fast cycle time and simplicity of use. Column address access time and cycle times of 35 ns are achieved. The device has some other functions to reduce critical timings. Address transition detector circuits are used for column selection. An improved column decoder is provided to allow column address input skew. The device uses NMOS single transistor memory cells and is packaged in a standard 300-mil 16-pin DIP.     

Dynamic threshold voltage damascene metal gate MOSFET (DT-DMG-MOS)technology for very low voltage operation of under 0.7 V

We propose dynamic threshold-voltage damascene metal gate MOSFET (DT-DMG-MOS) technology for very low voltage operation (under 0.7 V). In this technology the metal gate is formed by the damascene gate process and directly connected to the well region (Si-body). Therefore, the connection between gate electrode and silicon body can be more easily fabricated in the DT-DMG transistor than with conventional technologies. Furthermore, we found that low threshold voltage (about 0.15 V reduction for CMOS), high drive current, excellent subthreshold swing (about 60 mV/decade), and uniform electrical characteristics (great reduction of threshold voltage deviation) were obtained in the transistors with midgap work function metal gates (Al/TiN or W/TiN) and low supply voltage (0.7 V)     

A 12 MHz data cycle 4 Mb DRAM with pipeline operation

A 12 MHz data-cycle 4 Mb DRAM (dynamic RAM) with pipeline operation was designed and fabricated using 0.8 μm twin-tub CMOS technology. The pipeline DRAM outputs data corresponding to addresses that were accepted in the previous inverted random access storage (RAS) input cycle. The latter half of the previous read operation and the first half of the next read operation take place simultaneously, so the inverted RAS input cycle time is reduced. This pipeline DRAM technology needs no additional chip area and no process modification. A 95 ns inverted RAS input cycle time was obtained under worst conditions while this value is 125 ns for conventional DRAMs     

Alpha particle emission from platinum and its influence on DRAM operation

Ferroelectrics such as SrTiO/sub 3/ have been studied as DRAM capacitor insulators. Platinum is commonly used as their electrode material. However, platinum contains the isotope Pt/sup 190/, emitting alpha particles which cause soft errors. The authors measured the alpha particle emissivity of platinum coated silicon wafers. The resultant emissivity is consistent with the calculation. The impact on DRAM operation was estimated.<>     

An experimental 80-ns 1-Mbit DRAM with fast page operation

An experimental general purpose 5-V 1-Mb dynamic RAM has been designed for increased performance, high density, and enhanced reliability. The array consists of a one-device overlapped I/O cell with a metal bitline architecture. The cell measures 4.1 /spl mu/m by 8.8 /spl mu/m, which yields a chip size of 5.5 mm by 10.5 mm with an array to chip area ratio of 65.5%. The chip was designed in a double-poly single-metal NMOS technology with selected 1-/spl mu/m levels and an average feature size of 1.5 /spl mu/m. Key design features include a fast page mode cycle with minimum column precharge delay and improved protection for short error rate using a boosted word-line after sense amplifier set scheme. The CAS access time is 40 ns and the cycle is 65 ns at 4.5 V and 85/spl deg/C. The RAS access time is 80 ns and the cycle is 160 ns at 4.5 V and 85/spl deg/C with a typical active power of 625 mW. The chip is usable as a X1, X2, or X4 with the use of block select inputs and the selected package option. The package options include a 500-mil/SUP 2/ pin grid array module with 23 pins, and a 22 pin or 26 pin 300-mil surface solder plastic package.     

A precise on-chip voltage generator for a gigascale DRAM with anegative word-line scheme

A precise on-chip voltage generator for gigascale DRAM's with a negative word-line scheme is described. It combines a charge-pump regulator and a series-pass regulator, and it also includes a positive and negative offset voltage generator that uses a bandgap generator with a differential amplifier. The proposed circuit was experimentally evaluated with a test device fabricated using a 0.3-μm process. The simulation results show that the series-pass regulator suppresses the noise on a word-line low voltage (negative) to below 30 mV for the word-line transient and V_BB bouncing. A dc-voltage error of less than 6% without trimming is confirmed for the positive and negative offset voltage generator through the test device. These results show that the described scheme can be used in future low-voltage gigascale DRAM's