光电转换器件的伏安特性的快速测试方法设计及实现

通过硅光电转换器件的热平衡方程及其单指数模型?分析了温度改变对器件的实际测试精度的影响，基于数字源 表和虚拟仪器平台LABVIEW，针对电压线性扫描测试过程中脉冲上升沿对测试时间的限制问题，设计了电压脉冲上升沿进行器件伏安特性测试方案，测试时间缩短为130μｓ，开路电压及光电转换效率均有1％~2％的提升，实验证明该方法能够实现对光电器件的伏安特性的快速测量及有效提高测试精度。     

单壁碳纳米管阵列场效应特性的研究

单壁碳纳米管(Single-walled carbon nanotube,SWCNT)有许多异常的电特性,要完全实现其在实际电子系统中的潜在应用价值,需要在器件与电路的结合上有不断创新的方法。由于SWCNT在电子学上分为金属型和半导体型两大类,其中每一大类根据手性的不同在电特性上又各有差异,再加上要合成或合成后分离出单一手性的SWCNT,目前的技术还存在相当大的难度。结合化学气相沉积中的控制生长、控制转移排列整齐有序的SWC-NT阵列与微加工工艺等方法,将SWCNT阵列作为一个器件单元来进行测试,测试结果显示了一定的场效应特性。     

高速半导体激光二极管的微波特性研究

本文通过测试器件的微波Ｓ参量，对半导体量子阱激光二极管的微波特性进行了深入的研究。在计及器件本身特性以及器件在微波频率下的寄生参量的前提下给出了器件微波等效电路和相应的数字模拟方法。由测量出的微波Ｓ１１参量建立适当的目标函数，选择正确的计算方法，成功地模拟出电路各参量。     

一种新型高精度线性压电激励器的研制

报道了一种新型压电线性激励器，设计出它的结构，完成了器件制作。设计测试系统对其性能进行测试。器件的线性步进位移特性明显，具有步进模式和连续线性位移模式。行程可达几个厘米、位移分辨率为0．1μm、运行速度可达0．6mm/s。激励器结构简单，控制方便，适于研制闭环控制高精度定位系统。     

压电器件阻抗测试系统的研制

基于压电器件的等效电路模型,利用导纳圆理论图测量压电器件阻抗特性参数及过零检测相位差测量原理,构建了一套完整的压电器件性能参数阻抗测试系统。通过单片机控制信号产生幅值固定、频率可变的正弦信号,经功率放大后驱动压电器件产生超声高频振动,并采集压电器件两端的电压、电流及相位差信号,通过串口传给上位机。上位机采用基于Labview人机交互界面,实现压电器件阻抗特性参数计算和图形显示。实验结果表明,本测试系统能测量压电器件各主要相关参数,并动态显示阻抗特性曲线,可用于压电器件的参数测试与性能评估。     

压电器件阻抗测试系统的研制

基于压电器件的等效电路模型,利用导纳圆理论图测量压电器件阻抗特性参数及过零检测相位差测量原理,构建了一套完整的压电器件性能参数阻抗测试系统。通过单片机控制信号产生幅值固定、频率可变的正弦信号,经功率放大后驱动压电器件产生超声高频振动,并采集压电器件两端的电压、电流及相位差信号,通过串口传给上位机。上位机采用基于Labview人机交互界面,实现压电器件阻抗特性参数计算和图形显示。实验结果表明,本测试系统能测量压电器件各主要相关参数,并动态显示阻抗特性曲线,可用于压电器件的参数测试与性能评估。     

纳米结构器件材料结构参数的新测试方法

使用Monte Carlo模拟方法和器件振荡特性测试研究了异质谷间转移电子器件的直流隧穿特性和射频振荡性能与器件结构参数之间的关系.理论计算结果与实验数据间吻合得很好.在此基础上提出了通过电性能测试来分析器件结构参数的新方法.使用逐层化学腐蚀C-V测试测定了有源层的掺杂分布.通过低场电阻测量确定了量子阱的宽度.最后从器件振荡特性与Monte Carlo模拟曲线的对照中得出了掺杂接口的浓度.由此建立了器件结构参数的一套完整的测试分析方法.使用这套测试监控方法,已成功地研制出MBE和MOCVD工艺的高效、大功率振荡器件.     

集成电路抗ESD设计中的TLP测试技术

介绍了一种研究器件和电路结构在ESD期间新的特性测试方法——TLP法，该方法不仅可替代HBM测试，还能帮助电路设计师详细地分析器件和结构在ESD过程中的运行机制，有目的地进行器件ESD保护电路的设计，提高器件的抗ESD水平。     

离线式IGBT开关特性测试技术综述

IGBT功率开关器件在现代大功率变换器中的应用非常广泛,其开关特性直接影响到变换器的性能。获得实际工作条件下的开关器件特性具有重要的实用价值。如何准确测量并记录器件开关过程自然成为研究热点。文中分析了IGBT器件开关特性测试中的关键问题,总结了大功率下电流电压测量的各种方法,并对国内外的开关特性测试研究现状进行了分类和总结。     

一种用于微镜阵列投影测试的系统设计

在微镜器件的研制过程中,对其光学特性的测试需要借助很多仪器和测试平台,测试过程比较繁琐,测试成本也很高。设计了一种用于微镜阵列测试的电路系统,利用该系统可以将微镜阵列的工作状态以投影的方式显现出来,以便进行直观有效的测试。该测试电路以STM32微控制器为控制核心,用UHP灯(高压汞灯)和色轮作为投影光源,驱动AMD(先进微镜器件)的微镜阵列进行投影,相当于一个简洁的投影机控制主板,其特点是简单、实用、可靠性好。     

An effective BIST scheme for SRAM full speed test

This article presents a novel built-in self-test (BIST) scheme at full speed test where access time test is performed. Based on normal BIST circuits, we harness an all digital phase locked loop to generate a high-frequency clock for static random access memory (SRAM) performance test at full speed. A delay chain is incorporated to achieve the four-phase clock. As inputs to SRAM, clock, address, data are generated in terms of the four-phase clock. Key performance parameters, such as access time, address setup and hold times, are measured. The test chip has been fabricated by United Microelectronics Corporation 55?nm CMOS logic standard process. According to test results, the maximum test frequency is about 1.3?GHz, and the test precision is about 35?ps at the typical process corner with supply voltage 1.0?V and temperature 25°C.     

A 4096-B one-transistor per bit random-access memory with internal timing and low dissipation

Some details of a 4096-b p-channel random-access memory with a one-transistor per bit cell are discussed. The main features of the design are the sensitive sense-refresh amplifier, allowing a storage capacitance of only 0.065 pF, application of the bootstrap principle to obtain an access time of 400 ns, a power dissipation of 150 mW, and the implementation of a new, fast shift register as an internal timing circuit. This timing circuit generates the memory clock signals, reducing the number of external clock signals to one clock and a chip select signal. The chip size is 3.01/spl times/4.44 mm/SUP 2/.     

A WiSN node SoC with real-time image compressor and IEEE 802.15.4 MAC accelerator

This article presents a wireless image sensor node SoC (system-on-a-chip) for low-power wireless image sensor network (WiSN), in which camera chip interface, high-quality image compression and IEEE 802.15.4 compliant acceleration modules are integrated on chip. The proposed SoC contains a hardware-implemented real-time lossless JPEG (JPEG-LS) compression engine for Bayer Color Filter Arrays (Bayer CFA), reaching a 3.5 bits/pixel with peak signal to noise ratio (PSNR) greater than 46.3 dB and achieving a maximum 5 frames/s @16 MHz for VGA (640 × 480) colour images. The proposed hardware accelerator for IEEE 802.15.4 media access control (MAC) layer covers crucial protocol defined functions and algorithms, and reduces 45% software code in the host processor. This SoC has been fabricated in UMC 0.18 µm 1P6M CMOS process. The average power of the prototype chip is 18.2 mW at 3.0 V power supply and 16 MHz clock rate.     

Fast locking delay-locked loop using initial delay measurement

A delay-locked loop (DLL) architecture capable of incorporating fast locking and low jitter features simultaneously is reported. A test chip was fabricated in a 0.6 μm CMOS process to prove its functionality. The proposed DLL can align the internal clock to the external reference clock within two cycles and maintain its locking state with the aid of feedback operation     

一款SRAM芯片的设计与测试

基于Chartered 0.35μm EEPROM CMOS工艺,采用全定制方法设计了一款应用于低功耗和低成本电子设备的8×8 bit SRAM芯片。测试结果表明,在电源电压为3.3 V,时钟频率为20MHz的条件下,芯片功能正确、性能稳定、达到设计要求,存取时间约为6.2 ns,最大功耗约为6.12 mW。     

基于QtEmbedded的网络收音机的设计与开发

为了实现网络收音机的功能,提出了一种基于QtEmbedded的网络收音机系统的设计与实现。系统硬件以S3C6410为核心处理器,利用开源播放软件MPlayer作为播放器。该装置支持传统收音机、家庭网络和闹钟等功能,同时支持无线网络和有线网络这两种接入方式。由于该款产品界面友好、功能强大,在国外市场获得了巨大的成功。     

Mitigating Memory Wall Effects in High-Clock-Rate and Multicore CMOS 3-D Processor Memory Stacks

Three-dimensional chip (3-D) stacking technology provides a new approach to address the so-called memory wall problem. Memory processor chip stacking reduces this memory wall problem, permitting faster clock rates (with suitable processor logic) or permitting multicore access to shared memory using a large number of vertical vias between tiers in the stack, for ultrawide bit path transfer of data and address information to and from various levels of cache. Although a limited amount of parallel access is possible using conventional two-dimensional (2-D) chip memory-processor approaches, 3-D memory-processor stacking greatly extends this to much larger capacity memories. We evaluate high-clock-rate processors as well as shared memory processors with a large number of cores. Various architectural design options to reduce the impact of the memory wall on the processor performance are explored and validated through simulations. Certain architectural features can be implemented in a 3-D chip, such as an ultrawide, ultrashort vertical bus with low parasitic resistance and the elimination of conventional electrostatic discharge, and packaging parasitics required in multiple package 2-D solutions. The objective is to reduce the clocks per instruction figure of merit for high clock speeds in order to deliver significant performance levels. High-clock-rate processors can be designed with SiGe heterostructure bipolar transistors to obtain processors operating on the order of 16 or 32 GHz.      

A high-speed 128-kb MRAM core for future universal memory applications

A 128-kb magnetic random access memory (MRAM) test chip has been fabricated utilizing, for the first time, a 0.18-/spl mu/m V/sub DD/=1.8 V logic process technology with Cu metallization. The presented design uses a 1.4-/spl mu/m/sup 2/ one-transistor/one-magnetic tunnel junction (1T1MTJ) cell and features a symmetrical high-speed sensing architecture using complementary reference cells and configurable load devices. Extrapolations from test chip measurements and circuit assessments predict a 5-ns random array read access time and random write operations with <5-ns write pulse width.     

A 140 Mbit/s CMOS LSI framer chip for a broad-band ISDN localaccess system

A LSI framer chip, which provides a SONET-like time-division-multiplexed frame structure and which has been implemented in a production 2-μm CMOS technology, is described. Current samples of the chip have been tested functional to 160 Mb/s. The primary attributes presented include the circuit features used to achieve high-bit-rate operation, the level translation circuits which afford direct interfacing to ECL level clock and data signals, and the functional capabilities which lead to broad application of the chip in communications networks. Several examples of its use in a prototype broadband local access network are also described. The ship operates from a single 5-V supply, dissipates approximately 420 mW, and is packaged in a 68-pin leadless ceramic chip carrier (LCCC) package     

Design of a single-chip digital lattice equalizer filter

One lattice equalizer stage is designed on a single chip using 4-/spl mu/m NMOS technology. All the arithmetic operations of the chip are performed bit-serially under the control of a global two-phase clock, and they are totally pipelined. The data are represented as 16-bit two's complement fixed-point numbers. A built-in test scheme allows the offline testing of the chip with high fault coverage at a minimal hardware overhead. Direct coupling between chips permits the realization of filters of higher order. In addition, the structure of the lattice equalizer permits the use of the same chip in linear prediction problems. SPICE simulation results and fabrication of the major blocks in the design demonstrated that operating clock frequencies of up to 8 MHz are possible. At the maximum estimated operating clock frequency, the chip can accommodate applications with data rates of up to 500 kHz.